diff --git a/kernel/drivers/module-bbswitch/pspec.xml b/kernel/drivers/module-bbswitch/pspec.xml
index 178bfa3c..3d782e20 100644
--- a/kernel/drivers/module-bbswitch/pspec.xml
+++ b/kernel/drivers/module-bbswitch/pspec.xml
@@ -13,7 +13,7 @@
Kernel module allowing to switch dedicated graphics card on Optimus laptops
kernel module allowing to switch dedicated graphics card on Optimus laptops
- kernel-module-headers
+ kernel-module-headers
https://github.com/Bumblebee-Project/bbswitch/archive/v0.8.tar.gz
@@ -24,7 +24,7 @@
module-bbswitch
- kernel
+ kernel
bbswitch-common
@@ -62,6 +62,13 @@
+
+ 2021-11-10
+ 0.8
+ Rebuild
+ Ä°dris Kalp
+ idriskalp@gmail.com
+
2021-11-08
0.8
diff --git a/kernel/drivers/module-broadcom-wl/pspec.xml b/kernel/drivers/module-broadcom-wl/pspec.xml
index b5b9cc2b..8a65bc25 100755
--- a/kernel/drivers/module-broadcom-wl/pspec.xml
+++ b/kernel/drivers/module-broadcom-wl/pspec.xml
@@ -15,7 +15,7 @@
https://docs.broadcom.com/docs-and-downloads/docs/linux_sta/hybrid-v35-nodebug-pcoem-6_30_223_271.tar.gz
https://docs.broadcom.com/docs-and-downloads/docs/linux_sta/hybrid-v35_64-nodebug-pcoem-6_30_223_271.tar.gz
- kernel-module-headers
+ kernel-module-headers
broadcom-wl-6.30.223.271-debian-fix-kernel-warnings.patch
@@ -41,7 +41,7 @@
module-broadcom-wl
- kernel
+ kernel
module-broadcom-wl-userspace
@@ -70,6 +70,13 @@
+
+ 2021-11-10
+ 6.30.223.271
+ Rebuild
+ Ä°dris Kalp
+ idriskalp@gmail.com
+
2021-11-08
6.30.223.271
diff --git a/kernel/drivers/module-virtualbox-guest/pspec.xml b/kernel/drivers/module-virtualbox-guest/pspec.xml
index ca800354..fc360233 100644
--- a/kernel/drivers/module-virtualbox-guest/pspec.xml
+++ b/kernel/drivers/module-virtualbox-guest/pspec.xml
@@ -14,7 +14,7 @@
This package provides the kernel modules needed for mouse integration and shared folder support between VirtualBox host and guest systems.
https://sourceforge.net/projects/pisilinux/files/source/module-virtualbox-guest-6.1.28.tar.xz
- kernel-module-headers
+ kernel-module-headers
@@ -24,7 +24,7 @@
module-virtualbox-guest
- kernel
+ kernel
baselayout
module-virtualbox-guest-userspace
@@ -55,6 +55,13 @@
+
+ 2021-11-11
+ 6.1.28
+ Version bump.
+ Ä°dris Kalp
+ idriskalp@gmail.com
+
2021-11-08
6.1.28
diff --git a/kernel/drivers/module-virtualbox/pspec.xml b/kernel/drivers/module-virtualbox/pspec.xml
index a413d639..9ef2cf21 100644
--- a/kernel/drivers/module-virtualbox/pspec.xml
+++ b/kernel/drivers/module-virtualbox/pspec.xml
@@ -14,7 +14,7 @@
This package provides the kernel support for VirtualBox.
https://sourceforge.net/projects/pisilinux/files/source/module-virtualbox-6.1.28.tar.xz
- kernel-module-headers
+ kernel-module-headers
- patches/linux/patch-5.10.78.xz
+ patches/linux/patch-5.15.1.xz
- patches/mageia/fs-aufs5.10.patch
- patches/mageia/fs-aufs5.10-symbol-exports.patch
- patches/mageia/fs-aufs5.10-tristate.patch
+ patches/mageia/fs-aufs5.15.patch
+ patches/mageia/fs-aufs5.15-symbol-exports.patch
+ patches/mageia/fs-aufs5.15-tristate.patch
+
+ patches/mageia/fs-procfs-do-not-list-TID-0-in-proc-pid-task.patch
+
patches/mageia/CVE-2019-12379.patch
patches/mageia/CVE-2020-16119-DCCP-CCID-structure-use-after-free.patch
+
+ patches/mageia/platform-x86-add-shuttle-wmi-driver.patch
+ patches/mageia/platform-x86-shuttle-wmi-drop-devinit-exit.patch
+ patches/mageia/platform-x86-shuttle-wmi-4.2-buildfix.patch
+ patches/mageia/platform-x86-shuttle-wmi-4.13-buildfix.patch
+ patches/mageia/platform-x86-shuttle-wmi-kernel-5.5.patch
patches/mageia/3rd-3rdparty-tree.patch
patches/mageia/3rd-3rdparty-merge.patch
@@ -52,7 +61,8 @@
patches/mageia/3rd-rtl8812au.patch
patches/mageia/3rd-rtl8812au-Kconfig-Makefile.patch
patches/mageia/3rd-rtl8812au-rename.patch
-
+ patches/mageia/3rd-rtl8812au-kernel-5.12.patch
+ patches/mageia/3rd-rtl8812au-kernel-5.15.patch
patches/mageia/3rd-rtl8723de.patch
patches/mageia/3rd-rtl8723de-Kconfig-Makefile.patch
@@ -72,6 +82,8 @@
patches/mageia/3rd-rtl8821ce-Kconfig-Makefile.patch
patches/mageia/3rd-rtl8821ce-5.8-fix.patch
patches/mageia/3rd-rtl8821ce-kernel-5.10.patch
+ patches/mageia/3rd-rtl8821ce-kernel-5.12.patch
+ patches/mageia/3rd-rtl8821ce-kernel-5.15.patch
patches/mageia/3rd-fix-kconfig.patch
@@ -142,6 +154,17 @@
+
+ 2021-11-10
+ 5.15.1
+ Version bump.
+ security
+
+ systemRestart
+
+ Ä°dris Kalp
+ idriskalp@gmail.com
+
2021-11-08
5.10.78
diff --git a/kernel/tools/cpupowertools/files/patches/linux/patch-5.10.50.xz b/kernel/tools/cpupowertools/files/patches/linux/patch-5.10.50.xz
deleted file mode 100644
index 4a9a6f46..00000000
Binary files a/kernel/tools/cpupowertools/files/patches/linux/patch-5.10.50.xz and /dev/null differ
diff --git a/kernel/tools/cpupowertools/files/patches/linux/patch-5.10.58.xz b/kernel/tools/cpupowertools/files/patches/linux/patch-5.10.58.xz
deleted file mode 100644
index 26233d4b..00000000
Binary files a/kernel/tools/cpupowertools/files/patches/linux/patch-5.10.58.xz and /dev/null differ
diff --git a/kernel/tools/cpupowertools/files/patches/linux/patch-5.10.63.xz b/kernel/tools/cpupowertools/files/patches/linux/patch-5.10.63.xz
deleted file mode 100644
index 9722c92d..00000000
Binary files a/kernel/tools/cpupowertools/files/patches/linux/patch-5.10.63.xz and /dev/null differ
diff --git a/kernel/tools/cpupowertools/files/patches/linux/patch-5.10.70.xz b/kernel/tools/cpupowertools/files/patches/linux/patch-5.10.70.xz
deleted file mode 100644
index 0c2fd6a6..00000000
Binary files a/kernel/tools/cpupowertools/files/patches/linux/patch-5.10.70.xz and /dev/null differ
diff --git a/kernel/tools/cpupowertools/files/patches/linux/patch-5.10.78.xz b/kernel/tools/cpupowertools/files/patches/linux/patch-5.10.78.xz
deleted file mode 100644
index dbd6b8a9..00000000
Binary files a/kernel/tools/cpupowertools/files/patches/linux/patch-5.10.78.xz and /dev/null differ
diff --git a/kernel/tools/cpupowertools/files/patches/linux/patch-5.15.1.xz b/kernel/tools/cpupowertools/files/patches/linux/patch-5.15.1.xz
new file mode 100644
index 00000000..55e0279d
Binary files /dev/null and b/kernel/tools/cpupowertools/files/patches/linux/patch-5.15.1.xz differ
diff --git a/kernel/tools/cpupowertools/files/patches/mageia/3rd-3rdparty-merge.patch b/kernel/tools/cpupowertools/files/patches/mageia/3rd-3rdparty-merge.patch
index 1bae65c0..78d502ec 100644
--- a/kernel/tools/cpupowertools/files/patches/mageia/3rd-3rdparty-merge.patch
+++ b/kernel/tools/cpupowertools/files/patches/mageia/3rd-3rdparty-merge.patch
@@ -16,38 +16,42 @@ Signed-off-by: Thomas Backlund
arch/x86/Kconfig | 2 ++
4 files changed, 7 insertions(+), 1 deletion(-)
---- linux-5.8/arch/arm64/Kconfig.orig 2020-08-05 16:08:02.466740952 +0200
-+++ linux-5.8/arch/arm64/Kconfig 2020-08-05 16:08:13.368741815 +0200
-@@ -1910,3 +1910,5 @@ source "arch/arm64/kvm/Kconfig"
- if CRYPTO
- source "arch/arm64/crypto/Kconfig"
- endif
-+
-+source "3rdparty/Kconfig"
---- linux-5.8/Makefile.orig 2020-08-05 16:09:32.265748061 +0200
-+++ linux-5.8/Makefile 2020-08-05 16:10:02.553750458 +0200
-@@ -651,7 +651,7 @@ endif
- ifeq ($(KBUILD_EXTMOD),)
- # Objects we will link into vmlinux / subdirs we need to visit
- core-y := init/ usr/
--drivers-y := drivers/ sound/
-+drivers-y := drivers/ sound/ 3rdparty/
- drivers-$(CONFIG_SAMPLES) += samples/
- drivers-y += net/ virt/
- libs-y := lib/
---- linux-5.8/arch/x86/Kconfig.orig 2020-08-05 16:10:48.805754119 +0200
-+++ linux-5.8/arch/x86/Kconfig 2020-08-05 16:11:04.602755370 +0200
-@@ -2913,3 +2913,5 @@ source "drivers/firmware/Kconfig"
- source "arch/x86/kvm/Kconfig"
-
- source "arch/x86/Kconfig.assembler"
-+
-+source "3rdparty/Kconfig"
---- linux-5.8/arch/arm/Kconfig.orig 2020-08-05 16:12:08.314760413 +0200
-+++ linux-5.8/arch/arm/Kconfig 2020-08-05 16:12:22.786761559 +0200
-@@ -2064,3 +2064,5 @@ source "arch/arm/crypto/Kconfig"
+diff -Nurp linux-5.12/arch/arm/Kconfig linux-5.12-3rd/arch/arm/Kconfig
+--- linux-5.12/arch/arm/Kconfig 2021-04-25 23:49:08.000000000 +0300
++++ linux-5.12-3rd/arch/arm/Kconfig 2021-04-26 18:10:06.513775304 +0300
+@@ -2016,3 +2016,5 @@ source "arch/arm/crypto/Kconfig"
endif
source "arch/arm/Kconfig.assembler"
+
+source "3rdparty/Kconfig"
+diff -Nurp linux-5.12/arch/arm64/Kconfig linux-5.12-3rd/arch/arm64/Kconfig
+--- linux-5.12/arch/arm64/Kconfig 2021-04-25 23:49:08.000000000 +0300
++++ linux-5.12-3rd/arch/arm64/Kconfig 2021-04-26 18:10:06.512775257 +0300
+@@ -1959,3 +1959,5 @@ source "arch/arm64/kvm/Kconfig"
+ if CRYPTO
+ source "arch/arm64/crypto/Kconfig"
+ endif
++
++source "3rdparty/Kconfig"
+diff -Nurp linux-5.12/arch/x86/Kconfig linux-5.12-3rd/arch/x86/Kconfig
+--- linux-5.12/arch/x86/Kconfig 2021-04-25 23:49:08.000000000 +0300
++++ linux-5.12-3rd/arch/x86/Kconfig 2021-04-26 18:10:06.512775257 +0300
+@@ -2909,3 +2909,5 @@ source "drivers/firmware/Kconfig"
+ source "arch/x86/kvm/Kconfig"
+
+ source "arch/x86/Kconfig.assembler"
++
++source "3rdparty/Kconfig"
+diff -Nurp linux-5.14/Makefile linux-5.14-3rd/Makefile
+--- linux-5.14/Makefile
++++ linux-5.14-3rd/Makefile
+@@ -670,7 +670,7 @@ endif
+ ifeq ($(KBUILD_EXTMOD),)
+ # Objects we will link into vmlinux / subdirs we need to visit
+ core-y := init/ usr/ arch/$(SRCARCH)/
+-drivers-y := drivers/ sound/
++drivers-y := drivers/ sound/ 3rdparty/
+ drivers-$(CONFIG_SAMPLES) += samples/
+ drivers-$(CONFIG_NET) += net/
+ drivers-y += virt/
diff --git a/kernel/tools/cpupowertools/files/patches/mageia/3rd-fix-kconfig.patch b/kernel/tools/cpupowertools/files/patches/mageia/3rd-fix-kconfig.patch
index 6d1a4406..783807d7 100644
--- a/kernel/tools/cpupowertools/files/patches/mageia/3rd-fix-kconfig.patch
+++ b/kernel/tools/cpupowertools/files/patches/mageia/3rd-fix-kconfig.patch
@@ -9,17 +9,6 @@ diff -up ./3rdparty/rtl8723de/Kconfig.tv ./3rdparty/rtl8723de/Kconfig
+ help
Help message of RTL8723DE
-diff -up ./3rdparty/rtl8812au/Kconfig.tv ./3rdparty/rtl8812au/Kconfig
---- ./3rdparty/rtl8812au/Kconfig.tv 2020-10-13 21:02:36.391016614 +0200
-+++ ./3rdparty/rtl8812au/Kconfig 2020-10-13 20:59:07.421226249 +0200
-@@ -1,6 +1,6 @@
- config RTL8812AU
- tristate "Realtek 8812au USB WiFi"
- depends on USB
-- ---help---
-+ help
- Help message of 8812au
-
diff -up ./3rdparty/rtl8821ce/Kconfig.tv ./3rdparty/rtl8821ce/Kconfig
--- ./3rdparty/rtl8821ce/Kconfig.tv 2020-10-13 16:09:11.157856145 +0200
+++ ./3rdparty/rtl8821ce/Kconfig 2020-10-13 20:58:17.242118685 +0200
diff --git a/kernel/tools/cpupowertools/files/patches/mageia/3rd-rtl8723de.patch b/kernel/tools/cpupowertools/files/patches/mageia/3rd-rtl8723de.patch
index 44a2eb25..d7e94407 100644
--- a/kernel/tools/cpupowertools/files/patches/mageia/3rd-rtl8723de.patch
+++ b/kernel/tools/cpupowertools/files/patches/mageia/3rd-rtl8723de.patch
@@ -50102,7 +50102,7 @@ diff -Nurp linux-5.6.3/3rdparty/rtl8723de/core/rtw_mlme_ext.c linux-5.6.3-rtl872
+
+ rtw_phydm_ability_backup(padapter);
+
-+ sitesurvey_set_ici(padapter);
++ sitesurvey_set_igi(padapter);
+
+ /* config dynamic functions for off channel */
+ rtw_phydm_func_for_offchannel(padapter);
diff --git a/kernel/tools/cpupowertools/files/patches/mageia/3rd-rtl8812au-kernel-5.10.patch b/kernel/tools/cpupowertools/files/patches/mageia/3rd-rtl8812au-kernel-5.10.patch
deleted file mode 100644
index da512338..00000000
--- a/kernel/tools/cpupowertools/files/patches/mageia/3rd-rtl8812au-kernel-5.10.patch
+++ /dev/null
@@ -1,281 +0,0 @@
-From ee9619ba0c8840db6d59d11989c31e24a8f0d806 Mon Sep 17 00:00:00 2001
-From: Carlos
-Date: Sun, 8 Nov 2020 12:25:43 +0000
-Subject: [PATCH] Fix kernel 5.10-rc1
-
----
- 3rdparty/rtl8812au/core/rtw_btcoex.c | 7 ++++++-
- 3rdparty/rtl8812au/core/rtw_wlan_util.c | 10 ++++++----
- 3rdparty/rtl8812au/os_dep/linux/os_intfs.c | 19 +++++++++++++-----
- 3rdparty/rtl8812au/os_dep/osdep_service.c | 43 +++++++++++++++++++++++++++--------------
- 4 files changed, 54 insertions(+), 25 deletions(-)
-
-diff --git a/3rdparty/rtl8812au/core/rtw_btcoex.c b/3rdparty/rtl8812au/core/rtw_btcoex.c
-index d5b89bdc..f5e0f567 100644
---- a/3rdparty/rtl8812au/core/rtw_btcoex.c
-+++ b/3rdparty/rtl8812au/core/rtw_btcoex.c
-@@ -1443,7 +1443,9 @@ u8 rtw_btcoex_sendmsgbysocket(_adapter *padapter, u8 *msg, u8 msg_size, bool for
- {
- u8 error;
- struct msghdr udpmsg;
-+#ifdef set_fs
- mm_segment_t oldfs;
-+#endif
- struct iovec iov;
- struct bt_coex_info *pcoex_info = &padapter->coex_info;
-
-@@ -1473,15 +1475,18 @@ u8 rtw_btcoex_sendmsgbysocket(_adapter *padapter, u8 *msg, u8 msg_size, bool for
- udpmsg.msg_control = NULL;
- udpmsg.msg_controllen = 0;
- udpmsg.msg_flags = MSG_DONTWAIT | MSG_NOSIGNAL;
-+#ifdef set_fs
- oldfs = get_fs();
- set_fs(KERNEL_DS);
--
-+#endif
- #if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 1, 0))
- error = sock_sendmsg(pcoex_info->udpsock, &udpmsg);
- #else
- error = sock_sendmsg(pcoex_info->udpsock, &udpmsg, msg_size);
- #endif
-+#ifdef set_fs
- set_fs(oldfs);
-+#endif
- if (error < 0) {
- RTW_INFO("Error when sendimg msg, error:%d\n", error);
- return _FAIL;
-diff --git a/3rdparty/rtl8812au/core/rtw_wlan_util.c b/3rdparty/rtl8812au/core/rtw_wlan_util.c
-index b4cecd11..e465e9b5 100644
---- a/3rdparty/rtl8812au/core/rtw_wlan_util.c
-+++ b/3rdparty/rtl8812au/core/rtw_wlan_util.c
-@@ -4744,7 +4744,9 @@ int rtw_dev_nlo_info_set(struct pno_nlo_info *nlo_info, pno_ssid_t *ssid,
-
- int i = 0;
- struct file *fp;
-+#ifdef set_fs
- mm_segment_t fs;
-+#endif
- loff_t pos = 0;
- u8 *source = NULL;
- long len = 0;
-@@ -4780,10 +4782,10 @@ int rtw_dev_nlo_info_set(struct pno_nlo_info *nlo_info, pno_ssid_t *ssid,
- RTW_INFO("Error, cipher array using default value.\n");
- return 0;
- }
--
-+#ifdef set_fs
- fs = get_fs();
- set_fs(KERNEL_DS);
--
-+#endif
- source = rtw_zmalloc(2048);
-
- if (source != NULL) {
-@@ -4791,10 +4793,10 @@ int rtw_dev_nlo_info_set(struct pno_nlo_info *nlo_info, pno_ssid_t *ssid,
- rtw_parse_cipher_list(nlo_info, source);
- rtw_mfree(source, 2048);
- }
--
-+#ifdef set_fs
- set_fs(fs);
- filp_close(fp, NULL);
--
-+#endif
- RTW_INFO("-%s-\n", __func__);
- return 0;
- }
-diff --git a/3rdparty/rtl8812au/os_dep/linux/os_intfs.c b/3rdparty/rtl8812au/os_dep/linux/os_intfs.c
-index 1085d6cd..a37e488b 100644
---- a/3rdparty/rtl8812au/os_dep/linux/os_intfs.c
-+++ b/3rdparty/rtl8812au/os_dep/linux/os_intfs.c
-@@ -4029,7 +4029,9 @@ static int route_dump(u32 *gw_addr , int *gw_index)
- struct msghdr msg;
- struct iovec iov;
- struct sockaddr_nl nladdr;
-+#ifdef set_fs
- mm_segment_t oldfs;
-+#endif
- char *pg;
- int size = 0;
-
-@@ -4067,16 +4069,18 @@ static int route_dump(u32 *gw_addr , int *gw_index)
- msg.msg_control = NULL;
- msg.msg_controllen = 0;
- msg.msg_flags = MSG_DONTWAIT;
--
-+#ifdef set_fs
- oldfs = get_fs();
- set_fs(KERNEL_DS);
-+#endif
- #if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 1, 0))
- err = sock_sendmsg(sock, &msg);
- #else
- err = sock_sendmsg(sock, &msg, sizeof(req));
- #endif
-+#ifdef set_fs
- set_fs(oldfs);
--
-+#endif
- if (err < 0)
- goto out_sock;
-
-@@ -4099,16 +4103,18 @@ static int route_dump(u32 *gw_addr , int *gw_index)
- #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 19, 0))
- iov_iter_init(&msg.msg_iter, READ, &iov, 1, PAGE_SIZE);
- #endif
--
-+#ifdef set_fs
- oldfs = get_fs();
- set_fs(KERNEL_DS);
-+#endif
- #if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 7, 0))
- err = sock_recvmsg(sock, &msg, MSG_DONTWAIT);
- #else
- err = sock_recvmsg(sock, &msg, PAGE_SIZE, MSG_DONTWAIT);
- #endif
-+#ifdef set_fs
- set_fs(oldfs);
--
-+#endif
- if (err < 0)
- goto out_sock_pg;
-
-@@ -4178,15 +4184,18 @@ static int route_dump(u32 *gw_addr , int *gw_index)
- msg.msg_controllen = 0;
- msg.msg_flags = MSG_DONTWAIT;
-
-+#ifdef set_fs
- oldfs = get_fs();
- set_fs(KERNEL_DS);
-+#endif
- #if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 1, 0))
- err = sock_sendmsg(sock, &msg);
- #else
- err = sock_sendmsg(sock, &msg, sizeof(req));
- #endif
-+#ifdef set_fs
- set_fs(oldfs);
--
-+#endif
- if (err > 0)
- goto restart;
- }
-diff --git a/3rdparty/rtl8812au/os_dep/osdep_service.c b/3rdparty/rtl8812au/os_dep/osdep_service.c
-index 7c6d1208..0769b49d 100644
---- a/3rdparty/rtl8812au/os_dep/osdep_service.c
-+++ b/3rdparty/rtl8812au/os_dep/osdep_service.c
-@@ -2164,11 +2164,21 @@ static int writeFile(struct file *fp, char *buf, int len)
- {
- int wlen = 0, sum = 0;
-
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 1, 0))
-+ if (!(fp->f_mode & FMODE_CAN_WRITE))
-+#else
- if (!fp->f_op || !fp->f_op->write)
-+#endif
- return -EPERM;
-
- while (sum < len) {
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 14, 0))
-+ wlen = kernel_write(fp, buf + sum, len - sum, &fp->f_pos);
-+#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 1, 0))
-+ wlen = __vfs_write(fp, buf + sum, len - sum, &fp->f_pos);
-+#else
- wlen = fp->f_op->write(fp, buf + sum, len - sum, &fp->f_pos);
-+#endif
- if (wlen > 0)
- sum += wlen;
- else if (0 != wlen)
-@@ -2191,19 +2201,19 @@ static int isFileReadable(const char *path, u32 *sz)
- {
- struct file *fp;
- int ret = 0;
-+#ifdef set_fs
- mm_segment_t oldfs;
-+#endif
- char buf;
-
- fp = filp_open(path, O_RDONLY, 0);
- if (IS_ERR(fp))
- ret = PTR_ERR(fp);
- else {
-+#ifdef set_fs
- oldfs = get_fs();
-- #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 1, 0))
- set_fs(KERNEL_DS);
-- #else
-- set_fs(get_ds());
-- #endif
-+#endif
-
- if (1 != readFile(fp, &buf, 1))
- ret = PTR_ERR(fp);
-@@ -2215,8 +2225,9 @@ static int isFileReadable(const char *path, u32 *sz)
- *sz = i_size_read(fp->f_dentry->d_inode);
- #endif
- }
--
-+#ifdef set_fs
- set_fs(oldfs);
-+#endif
- filp_close(fp, NULL);
- }
- return ret;
-@@ -2232,22 +2243,23 @@ static int isFileReadable(const char *path, u32 *sz)
- static int retriveFromFile(const char *path, u8 *buf, u32 sz)
- {
- int ret = -1;
-+#ifdef set_fs
- mm_segment_t oldfs;
-+#endif
- struct file *fp;
-
- if (path && buf) {
- ret = openFile(&fp, path, O_RDONLY, 0);
- if (0 == ret) {
- RTW_INFO("%s openFile path:%s fp=%p\n", __FUNCTION__, path , fp);
--
-+#ifdef set_fs
- oldfs = get_fs();
-- #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 1, 0))
- set_fs(KERNEL_DS);
-- #else
-- set_fs(get_ds());
-- #endif
- ret = readFile(fp, buf, sz);
- set_fs(oldfs);
-+#else
-+ ret = readFile(fp, buf, sz);
-+#endif
- closeFile(fp);
-
- RTW_INFO("%s readFile, ret:%d\n", __FUNCTION__, ret);
-@@ -2271,22 +2283,23 @@ static int retriveFromFile(const char *path, u8 *buf, u32 sz)
- static int storeToFile(const char *path, u8 *buf, u32 sz)
- {
- int ret = 0;
-+#ifdef set_fs
- mm_segment_t oldfs;
-+#endif
- struct file *fp;
-
- if (path && buf) {
- ret = openFile(&fp, path, O_CREAT | O_WRONLY, 0666);
- if (0 == ret) {
- RTW_INFO("%s openFile path:%s fp=%p\n", __FUNCTION__, path , fp);
--
-+#ifdef set_fs
- oldfs = get_fs();
-- #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 1, 0))
- set_fs(KERNEL_DS);
-- #else
-- set_fs(get_ds());
-- #endif
- ret = writeFile(fp, buf, sz);
- set_fs(oldfs);
-+#else
-+ ret = writeFile(fp, buf, sz);
-+#endif
- closeFile(fp);
-
- RTW_INFO("%s writeFile, ret:%d\n", __FUNCTION__, ret);
diff --git a/kernel/tools/cpupowertools/files/patches/mageia/3rd-rtl8812au-kernel-5.12.patch b/kernel/tools/cpupowertools/files/patches/mageia/3rd-rtl8812au-kernel-5.12.patch
new file mode 100644
index 00000000..c53561cf
--- /dev/null
+++ b/kernel/tools/cpupowertools/files/patches/mageia/3rd-rtl8812au-kernel-5.12.patch
@@ -0,0 +1,12 @@
+diff -urp linux/3rdparty/rtl8812au.orig/os_dep/linux/recv_linux.c linux/3rdparty/rtl8812au/os_dep/linux/recv_linux.c
+--- linux/3rdparty/rtl8812au.orig/os_dep/linux/recv_linux.c 2021-04-26 18:35:37.411027594 +0300
++++ linux/3rdparty/rtl8812au/os_dep/linux/recv_linux.c 2021-04-26 18:53:13.502814526 +0300
+@@ -353,7 +353,7 @@ static int napi_recv(_adapter *padapter,
+
+ rx_ok = _FALSE;
+
+-#ifdef CONFIG_RTW_GRO
++#if defined(CONFIG_RTW_GRO) && LINUX_VERSION_CODE < KERNEL_VERSION(5, 12, 0)
+ if (pregistrypriv->en_gro) {
+ if (rtw_napi_gro_receive(&padapter->napi, pskb) != GRO_DROP)
+ rx_ok = _TRUE;
diff --git a/kernel/tools/cpupowertools/files/patches/mageia/3rd-rtl8812au-kernel-5.15.patch b/kernel/tools/cpupowertools/files/patches/mageia/3rd-rtl8812au-kernel-5.15.patch
new file mode 100644
index 00000000..86a002fe
--- /dev/null
+++ b/kernel/tools/cpupowertools/files/patches/mageia/3rd-rtl8812au-kernel-5.15.patch
@@ -0,0 +1,66 @@
+
+From:
+https://github.com/aircrack-ng/rtl8812au/commit/47a38b7c736dd9e9baac9eb07a6dceb83429fb49
+
+diff -Nurp linux-5.15/3rdparty/rtl8812au.orig/core/rtw_br_ext.c linux-5.15/3rdparty/rtl8812au/core/rtw_br_ext.c
+--- linux-5.15/3rdparty/rtl8812au.orig/core/rtw_br_ext.c 2021-11-08 23:40:48.236272741 +0200
++++ linux-5.15/3rdparty/rtl8812au/core/rtw_br_ext.c 2021-11-08 23:49:12.118046953 +0200
+@@ -17,7 +17,10 @@
+ #ifdef __KERNEL__
+ #include
+ #include
++ #include
++#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 15, 0)
+ #include
++#endif
+ #include
+ #include
+ #include
+@@ -169,6 +172,7 @@ static __inline__ void __nat25_generate_
+ }
+
+
++#ifdef _NET_INET_IPX_H_
+ static __inline__ void __nat25_generate_ipx_network_addr_with_node(unsigned char *networkAddr,
+ unsigned int *ipxNetAddr, unsigned char *ipxNodeAddr)
+ {
+@@ -189,6 +193,7 @@ static __inline__ void __nat25_generate_
+ memcpy(networkAddr + 1, (unsigned char *)ipxNetAddr, 4);
+ memcpy(networkAddr + 5, (unsigned char *)ipxSocketAddr, 2);
+ }
++#endif
+
+
+ static __inline__ void __nat25_generate_apple_network_addr(unsigned char *networkAddr,
+@@ -330,6 +335,7 @@ static __inline__ int __nat25_network_ha
+ x = networkAddr[7] ^ networkAddr[8] ^ networkAddr[9] ^ networkAddr[10];
+
+ return x & (NAT25_HASH_SIZE - 1);
++#ifdef _NET_INET_IPX_H_
+ } else if (networkAddr[0] == NAT25_IPX) {
+ unsigned long x;
+
+@@ -337,6 +343,7 @@ static __inline__ int __nat25_network_ha
+ networkAddr[6] ^ networkAddr[7] ^ networkAddr[8] ^ networkAddr[9] ^ networkAddr[10];
+
+ return x & (NAT25_HASH_SIZE - 1);
++#endif
+ } else if (networkAddr[0] == NAT25_APPLE) {
+ unsigned long x;
+
+@@ -889,6 +896,7 @@ int nat25_db_handle(_adapter *priv, stru
+ }
+ }
+
++#ifdef _NET_INET_IPX_H_
+ /*---------------------------------------------------*/
+ /* Handle IPX and Apple Talk frame */
+ /*---------------------------------------------------*/
+@@ -1109,6 +1117,7 @@ int nat25_db_handle(_adapter *priv, stru
+
+ return -1;
+ }
++#endif
+
+ /*---------------------------------------------------*/
+ /* Handle PPPoE frame */
diff --git a/kernel/tools/cpupowertools/files/patches/mageia/3rd-rtl8812au-rename.patch b/kernel/tools/cpupowertools/files/patches/mageia/3rd-rtl8812au-rename.patch
index a255a558..bcf02987 100644
--- a/kernel/tools/cpupowertools/files/patches/mageia/3rd-rtl8812au-rename.patch
+++ b/kernel/tools/cpupowertools/files/patches/mageia/3rd-rtl8812au-rename.patch
@@ -4,15 +4,15 @@ Adjust driver bits so it keeps the name of the replaced driver
Signed-off-by: Thomas Backlund
---
- 3rdparty/rtl8812au/Kconfig | 6 +++---
+ 3rdparty/rtl8812au/Kconfig | 7 +++----
3rdparty/rtl8812au/Makefile | 8 ++++----
3rdparty/rtl8812au/hal/hal_com.c | 2 +-
3rdparty/rtl8812au/os_dep/linux/ioctl_cfg80211.c | 2 +-
- 4 files changed, 9 insertions(+), 9 deletions(-)
+ 4 files changed, 9 insertions(+), 10 deletions(-)
-diff -Nurp linux-5.5/3rdparty/rtl8812au.orig/hal/hal_com.c linux-5.5/3rdparty/rtl8812au/hal/hal_com.c
---- linux-5.5/3rdparty/rtl8812au.orig/hal/hal_com.c 2020-03-09 01:46:04.750166543 +0200
-+++ linux-5.5/3rdparty/rtl8812au/hal/hal_com.c 2020-03-11 18:23:33.839805026 +0200
+diff -Nurp linux-5.11/3rdparty/rtl8812au.orig/hal/hal_com.c linux-5.11/3rdparty/rtl8812au/hal/hal_com.c
+--- linux-5.11/3rdparty/rtl8812au.orig/hal/hal_com.c 2021-03-07 18:43:20.313672664 +0200
++++ linux-5.11/3rdparty/rtl8812au/hal/hal_com.c 2021-03-07 18:43:51.392141299 +0200
@@ -12879,7 +12879,7 @@ bypass_hw_pg:
_rtw_memset(hal_data->EEPROMMACAddr, 0, ETH_ALEN);
ret = _FAIL;
@@ -22,25 +22,25 @@ diff -Nurp linux-5.5/3rdparty/rtl8812au.orig/hal/hal_com.c linux-5.5/3rdparty/rt
return ret;
}
-diff -Nurp linux-5.5/3rdparty/rtl8812au.orig/Kconfig linux-5.5/3rdparty/rtl8812au/Kconfig
---- linux-5.5/3rdparty/rtl8812au.orig/Kconfig 2020-03-09 01:46:04.682163430 +0200
-+++ linux-5.5/3rdparty/rtl8812au/Kconfig 2020-03-11 18:21:33.457357175 +0200
-@@ -1,6 +1,6 @@
+diff -Nurp linux-5.11/3rdparty/rtl8812au.orig/Kconfig linux-5.11/3rdparty/rtl8812au/Kconfig
+--- linux-5.11/3rdparty/rtl8812au.orig/Kconfig 2021-03-07 18:43:20.369675309 +0200
++++ linux-5.11/3rdparty/rtl8812au/Kconfig 2021-03-07 18:45:22.910465892 +0200
+@@ -1,6 +1,5 @@
-config 88XXAU
- tristate "Realtek 88XXau USB WiFi"
+config RTL8812AU
+ tristate "Realtek 8812au USB WiFi"
depends on USB
- ---help---
+ help
- Help message of 88XXau
+-
+ Help message of 8812au
+diff -Nurp linux-5.11/3rdparty/rtl8812au.orig/Makefile linux-5.11/3rdparty/rtl8812au/Makefile
+--- linux-5.11/3rdparty/rtl8812au.orig/Makefile 2021-03-07 18:43:20.370675357 +0200
++++ linux-5.11/3rdparty/rtl8812au/Makefile 2021-03-07 18:43:51.401141725 +0200
+@@ -180,9 +180,9 @@ endif
-diff -Nurp linux-5.5/3rdparty/rtl8812au.orig/Makefile linux-5.5/3rdparty/rtl8812au/Makefile
---- linux-5.5/3rdparty/rtl8812au.orig/Makefile 2020-03-09 01:46:04.682163430 +0200
-+++ linux-5.5/3rdparty/rtl8812au/Makefile 2020-03-11 18:22:16.769317077 +0200
-@@ -179,9 +179,9 @@ endif
-
- ifeq ($(CONFIG_RTL8812A)_$(CONFIG_RTL8821A)_$(CONFIG_RTL8814A), y_y_y)
+ ifeq ($(CONFIG_RTL8812A)_$(CONFIG_RTL8821A)_$(CONFIG_RTL8814A), y_y_n)
-EXTRA_CFLAGS += -DDRV_NAME=\"rtl88XXau\"
+EXTRA_CFLAGS += -DDRV_NAME=\"rtl8812au\"
@@ -50,7 +50,7 @@ diff -Nurp linux-5.5/3rdparty/rtl8812au.orig/Makefile linux-5.5/3rdparty/rtl8812
endif
else
EXTRA_CFLAGS += -DDRV_NAME=\"rtl8812au\"
-@@ -2233,11 +2233,11 @@ $(MODULE_NAME)-y += $(_PLATFORM_FILES)
+@@ -2232,11 +2232,11 @@ $(MODULE_NAME)-y += $(_PLATFORM_FILES)
$(MODULE_NAME)-$(CONFIG_MP_INCLUDED) += core/rtw_mp.o
@@ -64,10 +64,10 @@ diff -Nurp linux-5.5/3rdparty/rtl8812au.orig/Makefile linux-5.5/3rdparty/rtl8812
all: modules
-diff -Nurp linux-5.5/3rdparty/rtl8812au.orig/os_dep/linux/ioctl_cfg80211.c linux-5.5/3rdparty/rtl8812au/os_dep/linux/ioctl_cfg80211.c
---- linux-5.5/3rdparty/rtl8812au.orig/os_dep/linux/ioctl_cfg80211.c 2020-03-09 01:46:04.798168741 +0200
-+++ linux-5.5/3rdparty/rtl8812au/os_dep/linux/ioctl_cfg80211.c 2020-03-11 18:24:09.196405329 +0200
-@@ -2639,7 +2639,7 @@ void rtw_cfg80211_unlink_bss(_adapter *p
+diff -Nurp linux-5.11/3rdparty/rtl8812au.orig/os_dep/linux/ioctl_cfg80211.c linux-5.11/3rdparty/rtl8812au/os_dep/linux/ioctl_cfg80211.c
+--- linux-5.11/3rdparty/rtl8812au.orig/os_dep/linux/ioctl_cfg80211.c 2021-03-07 18:43:20.371675404 +0200
++++ linux-5.11/3rdparty/rtl8812au/os_dep/linux/ioctl_cfg80211.c 2021-03-07 18:43:51.402141772 +0200
+@@ -2646,7 +2646,7 @@ void rtw_cfg80211_unlink_bss(_adapter *p
#endif
if (!wiphy) {
diff --git a/kernel/tools/cpupowertools/files/patches/mageia/3rd-rtl8812au.patch b/kernel/tools/cpupowertools/files/patches/mageia/3rd-rtl8812au.patch
index 0d550052..891f72c5 100644
--- a/kernel/tools/cpupowertools/files/patches/mageia/3rd-rtl8812au.patch
+++ b/kernel/tools/cpupowertools/files/patches/mageia/3rd-rtl8812au.patch
@@ -1,2910 +1,6 @@
-Cloned from:
- https://github.com/aircrack-ng/rtl8812au.git
-
-Signed-off-by: Nicolas Lécureuil
----
-
-diff --git linux-5.8/3rdparty/rtl8812au/Kconfig linux-5.8/3rdparty/rtl8812au/Kconfig
-new file mode 100644
-index 000000000..f63a78009
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/Kconfig
-@@ -0,0 +1,6 @@
-+config 88XXAU
-+ tristate "Realtek 88XXau USB WiFi"
-+ depends on USB
-+ ---help---
-+ Help message of 88XXau
-+
-diff --git linux-5.8/3rdparty/rtl8812au/LICENSE linux-5.8/3rdparty/rtl8812au/LICENSE
-new file mode 100644
-index 000000000..d159169d1
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/LICENSE
-@@ -0,0 +1,339 @@
-+ GNU GENERAL PUBLIC LICENSE
-+ Version 2, June 1991
-+
-+ Copyright (C) 1989, 1991 Free Software Foundation, Inc.,
-+ 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
-+ Everyone is permitted to copy and distribute verbatim copies
-+ of this license document, but changing it is not allowed.
-+
-+ Preamble
-+
-+ The licenses for most software are designed to take away your
-+freedom to share and change it. By contrast, the GNU General Public
-+License is intended to guarantee your freedom to share and change free
-+software--to make sure the software is free for all its users. This
-+General Public License applies to most of the Free Software
-+Foundation's software and to any other program whose authors commit to
-+using it. (Some other Free Software Foundation software is covered by
-+the GNU Lesser General Public License instead.) You can apply it to
-+your programs, too.
-+
-+ When we speak of free software, we are referring to freedom, not
-+price. Our General Public Licenses are designed to make sure that you
-+have the freedom to distribute copies of free software (and charge for
-+this service if you wish), that you receive source code or can get it
-+if you want it, that you can change the software or use pieces of it
-+in new free programs; and that you know you can do these things.
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-+anyone to deny you these rights or to ask you to surrender the rights.
-+These restrictions translate to certain responsibilities for you if you
-+distribute copies of the software, or if you modify it.
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-+gratis or for a fee, you must give the recipients all the rights that
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-+(2) offer you this license which gives you legal permission to copy,
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-+that everyone understands that there is no warranty for this free
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-+ 10. If you wish to incorporate parts of the Program into other free
-+programs whose distribution conditions are different, write to the author
-+to ask for permission. For software which is copyrighted by the Free
-+Software Foundation, write to the Free Software Foundation; we sometimes
-+make exceptions for this. Our decision will be guided by the two goals
-+of preserving the free status of all derivatives of our free software and
-+of promoting the sharing and reuse of software generally.
-+
-+ NO WARRANTY
-+
-+ 11. BECAUSE THE PROGRAM IS LICENSED FREE OF CHARGE, THERE IS NO WARRANTY
-+FOR THE PROGRAM, TO THE EXTENT PERMITTED BY APPLICABLE LAW. EXCEPT WHEN
-+OTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR OTHER PARTIES
-+PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED
-+OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-+MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK AS
-+TO THE QUALITY AND PERFORMANCE OF THE PROGRAM IS WITH YOU. SHOULD THE
-+PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL NECESSARY SERVICING,
-+REPAIR OR CORRECTION.
-+
-+ 12. IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING
-+WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MAY MODIFY AND/OR
-+REDISTRIBUTE THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES,
-+INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING
-+OUT OF THE USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED
-+TO LOSS OF DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY
-+YOU OR THIRD PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER
-+PROGRAMS), EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE
-+POSSIBILITY OF SUCH DAMAGES.
-+
-+ END OF TERMS AND CONDITIONS
-+
-+ How to Apply These Terms to Your New Programs
-+
-+ If you develop a new program, and you want it to be of the greatest
-+possible use to the public, the best way to achieve this is to make it
-+free software which everyone can redistribute and change under these terms.
-+
-+ To do so, attach the following notices to the program. It is safest
-+to attach them to the start of each source file to most effectively
-+convey the exclusion of warranty; and each file should have at least
-+the "copyright" line and a pointer to where the full notice is found.
-+
-+
-+ Copyright (C)
-+
-+ This program is free software; you can redistribute it and/or modify
-+ it under the terms of the GNU General Public License as published by
-+ the Free Software Foundation; either version 2 of the License, or
-+ (at your option) any later version.
-+
-+ This program is distributed in the hope that it will be useful,
-+ but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ GNU General Public License for more details.
-+
-+ You should have received a copy of the GNU General Public License along
-+ with this program; if not, write to the Free Software Foundation, Inc.,
-+ 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
-+
-+Also add information on how to contact you by electronic and paper mail.
-+
-+If the program is interactive, make it output a short notice like this
-+when it starts in an interactive mode:
-+
-+ Gnomovision version 69, Copyright (C) year name of author
-+ Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
-+ This is free software, and you are welcome to redistribute it
-+ under certain conditions; type `show c' for details.
-+
-+The hypothetical commands `show w' and `show c' should show the appropriate
-+parts of the General Public License. Of course, the commands you use may
-+be called something other than `show w' and `show c'; they could even be
-+mouse-clicks or menu items--whatever suits your program.
-+
-+You should also get your employer (if you work as a programmer) or your
-+school, if any, to sign a "copyright disclaimer" for the program, if
-+necessary. Here is a sample; alter the names:
-+
-+ Yoyodyne, Inc., hereby disclaims all copyright interest in the program
-+ `Gnomovision' (which makes passes at compilers) written by James Hacker.
-+
-+ , 1 April 1989
-+ Ty Coon, President of Vice
-+
-+This General Public License does not permit incorporating your program into
-+proprietary programs. If your program is a subroutine library, you may
-+consider it more useful to permit linking proprietary applications with the
-+library. If this is what you want to do, use the GNU Lesser General
-+Public License instead of this License.
-diff --git linux-5.8/3rdparty/rtl8812au/Makefile linux-5.8/3rdparty/rtl8812au/Makefile
-new file mode 100755
-index 000000000..27daceded
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/Makefile
-@@ -0,0 +1,2316 @@
-+EXTRA_CFLAGS += $(USER_EXTRA_CFLAGS) -fno-pie
-+EXTRA_CFLAGS += -O3
-+EXTRA_CFLAGS += -Wno-unused-variable
-+#EXTRA_CFLAGS += -Wno-unused-value
-+EXTRA_CFLAGS += -Wno-unused-label
-+#EXTRA_CFLAGS += -Wno-unused-parameter
-+EXTRA_CFLAGS += -Wno-unused-function
-+EXTRA_CFLAGS += -Wimplicit-fallthrough=0
-+#EXTRA_CFLAGS += -Wno-parentheses-equality
-+#EXTRA_CFLAGS += -Wno-pointer-bool-conversion
-+EXTRA_CFLAGS += -Wno-unknown-pragmas
-+#EXTRA_CFLAGS += -Wno-unused
-+EXTRA_CFLAGS += -Wno-vla -g
-+
-+#GCC_VER_49 := $(shell echo `$(CC) -dumpversion | cut -f1-2 -d.` \>= 4.9 | bc )
-+#ifeq ($(GCC_VER_49),1)
-+#EXTRA_CFLAGS += -Wno-date-time # Fix compile error && warning on gcc 4.9 and later
-+#endif
-+
-+EXTRA_CFLAGS += -I$(src)/include
-+EXTRA_LDFLAGS += --strip-all -O3
-+
-+########################## WIFI IC ############################
-+CONFIG_RTL8812A = y
-+CONFIG_RTL8821A = y
-+CONFIG_RTL8814A = y
-+######################### Interface ###########################
-+CONFIG_USB_HCI = y
-+########################### Android ###########################
-+CONFIG_SIGNAL_DISPLAY_DBM = y
-+########################## Features ###########################
-+CONFIG_NET_NS = y
-+CONFIG_MP_INCLUDED = y
-+CONFIG_POWER_SAVING = n
-+CONFIG_USB_AUTOSUSPEND = n
-+CONFIG_HW_PWRP_DETECTION = n
-+CONFIG_BT_COEXIST = n
-+CONFIG_INTEL_WIDI = n
-+CONFIG_WAPI_SUPPORT = n
-+CONFIG_EFUSE_CONFIG_FILE = y
-+CONFIG_EXT_CLK = n
-+CONFIG_TRAFFIC_PROTECT = n
-+CONFIG_LOAD_PHY_PARA_FROM_FILE = y
-+CONFIG_TXPWR_BY_RATE = y
-+CONFIG_TXPWR_BY_RATE_EN = n
-+CONFIG_TXPWR_LIMIT = y
-+CONFIG_TXPWR_LIMIT_EN = n
-+CONFIG_RTW_CHPLAN = 0xFF
-+CONFIG_RTW_ADAPTIVITY_EN = disable
-+CONFIG_RTW_ADAPTIVITY_MODE = normal
-+CONFIG_SIGNAL_SCALE_MAPPING = n
-+CONFIG_80211W = y
-+CONFIG_REDUCE_TX_CPU_LOADING = n
-+CONFIG_BR_EXT = y
-+CONFIG_TDLS = n
-+CONFIG_WIFI_MONITOR = y
-+CONFIG_DISABLE_REGD_C = y
-+CONFIG_MCC_MODE = n
-+CONFIG_APPEND_VENDOR_IE_ENABLE = n
-+CONFIG_RTW_NAPI = y
-+CONFIG_RTW_GRO = y
-+CONFIG_RTW_NETIF_SG = y
-+CONFIG_TX_CSUM_OFFLOAD = n
-+CONFIG_RTW_IPCAM_APPLICATION = n
-+CONFIG_RTW_REPEATER_SON = n
-+CONFIG_RTW_WIFI_HAL = n
-+CONFIG_ICMP_VOQ = n
-+CONFIG_IP_R_MONITOR = n #arp VOQ and high rate
-+########################## Debug ###########################
-+CONFIG_RTW_DEBUG = n
-+# default log level is _DRV_INFO_ = 4,
-+# please refer to "How_to_set_driver_debug_log_level.doc" to set the available level.
-+CONFIG_RTW_LOG_LEVEL = 2
-+######################## Wake On Lan ##########################
-+CONFIG_WOWLAN = n
-+#bit2: deauth, bit1: unicast, bit0: magic pkt.
-+CONFIG_WAKEUP_TYPE = 0x7
-+#bit0: disBBRF off, #bit1: Wireless remote controller (WRC)
-+CONFIG_SUSPEND_TYPE = 0
-+CONFIG_WOW_STA_MIX = n
-+CONFIG_GPIO_WAKEUP = n
-+CONFIG_WAKEUP_GPIO_IDX = default
-+CONFIG_HIGH_ACTIVE_DEV2HST = n
-+######### only for USB #########
-+CONFIG_ONE_PIN_GPIO = n
-+CONFIG_HIGH_ACTIVE_HST2DEV = n
-+CONFIG_PNO_SUPPORT = n
-+CONFIG_PNO_SET_DEBUG = n
-+CONFIG_AP_WOWLAN = n
-+######### Notify SDIO Host Keep Power During Syspend ##########
-+CONFIG_RTW_SDIO_PM_KEEP_POWER = y
-+###################### MP HW TX MODE FOR VHT #######################
-+CONFIG_MP_VHT_HW_TX_MODE = n
-+###################### Platform Related #######################
-+CONFIG_PLATFORM_I386_PC = y
-+CONFIG_PLATFORM_ANDROID_ARM64 = n
-+CONFIG_PLATFORM_ARM_RPI = n
-+CONFIG_PLATFORM_ARM64_RPI = n
-+CONFIG_PLATFORM_ARM_NV_NANO = n
-+CONFIG_PLATFORM_ANDROID_X86 = n
-+CONFIG_PLATFORM_ANDROID_INTEL_X86 = n
-+CONFIG_PLATFORM_JB_X86 = n
-+CONFIG_PLATFORM_OPENWRT_NEO2 = n
-+CONFIG_PLATFORM_ARM_S3C2K4 = n
-+CONFIG_PLATFORM_ARM_PXA2XX = n
-+CONFIG_PLATFORM_ARM_S3C6K4 = n
-+CONFIG_PLATFORM_MIPS_RMI = n
-+CONFIG_PLATFORM_RTD2880B = n
-+CONFIG_PLATFORM_MIPS_AR9132 = n
-+CONFIG_PLATFORM_RTK_DMP = n
-+CONFIG_PLATFORM_MIPS_PLM = n
-+CONFIG_PLATFORM_MSTAR389 = n
-+CONFIG_PLATFORM_MT53XX = n
-+CONFIG_PLATFORM_ARM_MX51_241H = n
-+CONFIG_PLATFORM_FS_MX61 = n
-+CONFIG_PLATFORM_ACTIONS_ATJ227X = n
-+CONFIG_PLATFORM_TEGRA3_CARDHU = n
-+CONFIG_PLATFORM_TEGRA4_DALMORE = n
-+CONFIG_PLATFORM_ARM_TCC8900 = n
-+CONFIG_PLATFORM_ARM_TCC8920 = n
-+CONFIG_PLATFORM_ARM_TCC8920_JB42 = n
-+CONFIG_PLATFORM_ARM_TCC8930_JB42 = n
-+CONFIG_PLATFORM_ARM_RK2818 = n
-+CONFIG_PLATFORM_ARM_RK3066 = n
-+CONFIG_PLATFORM_ARM_RK3188 = n
-+CONFIG_PLATFORM_ARM_URBETTER = n
-+CONFIG_PLATFORM_ARM_TI_PANDA = n
-+CONFIG_PLATFORM_MIPS_JZ4760 = n
-+CONFIG_PLATFORM_DMP_PHILIPS = n
-+CONFIG_PLATFORM_MSTAR_TITANIA12 = n
-+CONFIG_PLATFORM_MSTAR = n
-+CONFIG_PLATFORM_SZEBOOK = n
-+CONFIG_PLATFORM_ARM_SUNxI = n
-+CONFIG_PLATFORM_ARM_SUN6I = n
-+CONFIG_PLATFORM_ARM_SUN7I = n
-+CONFIG_PLATFORM_ARM_SUN8I_W3P1 = n
-+CONFIG_PLATFORM_ARM_SUN8I_W5P1 = n
-+CONFIG_PLATFORM_ACTIONS_ATM702X = n
-+CONFIG_PLATFORM_ACTIONS_ATV5201 = n
-+CONFIG_PLATFORM_ACTIONS_ATM705X = n
-+CONFIG_PLATFORM_ARM_SUN50IW1P1 = n
-+CONFIG_PLATFORM_ARM_RTD299X = n
-+CONFIG_PLATFORM_ARM_LGE = n
-+CONFIG_PLATFORM_ARM_SPREADTRUM_6820 = n
-+CONFIG_PLATFORM_ARM_SPREADTRUM_8810 = n
-+CONFIG_PLATFORM_ARM_WMT = n
-+CONFIG_PLATFORM_TI_DM365 = n
-+CONFIG_PLATFORM_MOZART = n
-+CONFIG_PLATFORM_RTK119X = n
-+CONFIG_PLATFORM_RTK119X_AM = n
-+CONFIG_PLATFORM_RTK129X = n
-+CONFIG_PLATFORM_RTK390X = n
-+CONFIG_PLATFORM_NOVATEK_NT72668 = n
-+CONFIG_PLATFORM_HISILICON = n
-+CONFIG_PLATFORM_HISILICON_HI3798 = n
-+CONFIG_PLATFORM_NV_TK1 = n
-+CONFIG_PLATFORM_NV_TK1_UBUNTU = n
-+CONFIG_PLATFORM_RTL8197D = n
-+CONFIG_PLATFORM_AML_S905 = n
-+CONFIG_PLATFORM_ZTE_ZX296716 = n
-+CONFIG_PLATFORM_ARM_ODROIDC2 = n
-+CONFIG_PLATFORM_PPC = n
-+########### CUSTOMER ################################
-+CONFIG_CUSTOMER_HUAWEI_GENERAL = n
-+
-+CONFIG_DRVEXT_MODULE = n
-+
-+ifeq ($(CONFIG_RTL8812AU), )
-+ifneq (,$(findstring /usr/lib/dkms,$(PATH)))
-+ export TopDIR ?= $(shell pwd)
-+else
-+export TopDIR ?= $(srctree)/$(src)
-+endif
-+endif
-+
-+########### COMMON #################################
-+ifeq ($(CONFIG_USB_HCI), y)
-+HCI_NAME = usb
-+endif
-+
-+ifeq ($(CONFIG_RTL8812A)_$(CONFIG_RTL8821A)_$(CONFIG_RTL8814A), y_y_y)
-+
-+EXTRA_CFLAGS += -DDRV_NAME=\"rtl88XXau\"
-+ifeq ($(CONFIG_USB_HCI), y)
-+USER_MODULE_NAME = 88XXau
-+endif
-+else
-+EXTRA_CFLAGS += -DDRV_NAME=\"rtl8812au\"
-+endif
-+
-+_OS_INTFS_FILES := os_dep/osdep_service.o \
-+ os_dep/linux/os_intfs.o \
-+ os_dep/linux/$(HCI_NAME)_intf.o \
-+ os_dep/linux/$(HCI_NAME)_ops_linux.o \
-+ os_dep/linux/ioctl_linux.o \
-+ os_dep/linux/xmit_linux.o \
-+ os_dep/linux/mlme_linux.o \
-+ os_dep/linux/recv_linux.o \
-+ os_dep/linux/ioctl_cfg80211.o \
-+ os_dep/linux/wifi_regd.o \
-+ os_dep/linux/rtw_android.o \
-+ os_dep/linux/rtw_proc.o \
-+ os_dep/linux/rtw_rhashtable.o
-+
-+ifeq ($(CONFIG_MP_INCLUDED), y)
-+_OS_INTFS_FILES += os_dep/linux/ioctl_mp.o
-+endif
-+
-+_HAL_INTFS_FILES := hal/hal_intf.o \
-+ hal/hal_com.o \
-+ hal/hal_com_phycfg.o \
-+ hal/hal_phy.o \
-+ hal/hal_dm.o \
-+ hal/hal_dm_acs.o \
-+ hal/hal_btcoex_wifionly.o \
-+ hal/hal_btcoex.o \
-+ hal/hal_mp.o \
-+ hal/hal_mcc.o \
-+ hal/hal_hci/hal_$(HCI_NAME).o \
-+ hal/led/hal_led.o \
-+ hal/led/hal_$(HCI_NAME)_led.o
-+
-+
-+EXTRA_CFLAGS += -I$(src)/platform
-+_PLATFORM_FILES := platform/platform_ops.o
-+
-+EXTRA_CFLAGS += -I$(src)/hal/btc
-+
-+########### HAL_RTL8188E #################################
-+ifeq ($(CONFIG_RTL8188E), y)
-+
-+RTL871X = rtl8188e
-+ifeq ($(CONFIG_SDIO_HCI), y)
-+MODULE_NAME = 8189es
-+endif
-+
-+ifeq ($(CONFIG_GSPI_HCI), y)
-+MODULE_NAME = 8189es
-+endif
-+
-+ifeq ($(CONFIG_USB_HCI), y)
-+MODULE_NAME = 8188eu
-+endif
-+
-+ifeq ($(CONFIG_PCI_HCI), y)
-+MODULE_NAME = 8188ee
-+endif
-+EXTRA_CFLAGS += -DCONFIG_RTL8188E
-+
-+_HAL_INTFS_FILES += hal/HalPwrSeqCmd.o \
-+ hal/$(RTL871X)/Hal8188EPwrSeq.o\
-+ hal/$(RTL871X)/$(RTL871X)_xmit.o\
-+ hal/$(RTL871X)/$(RTL871X)_sreset.o
-+
-+_HAL_INTFS_FILES += hal/$(RTL871X)/$(RTL871X)_hal_init.o \
-+ hal/$(RTL871X)/$(RTL871X)_phycfg.o \
-+ hal/$(RTL871X)/$(RTL871X)_rf6052.o \
-+ hal/$(RTL871X)/$(RTL871X)_dm.o \
-+ hal/$(RTL871X)/$(RTL871X)_rxdesc.o \
-+ hal/$(RTL871X)/$(RTL871X)_cmd.o \
-+ hal/$(RTL871X)/hal8188e_s_fw.o \
-+ hal/$(RTL871X)/hal8188e_t_fw.o \
-+ hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_halinit.o \
-+ hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_NAME)_led.o \
-+ hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_NAME)_xmit.o \
-+ hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_NAME)_recv.o
-+
-+ifeq ($(CONFIG_SDIO_HCI), y)
-+_HAL_INTFS_FILES += hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_ops.o
-+else
-+ifeq ($(CONFIG_GSPI_HCI), y)
-+_HAL_INTFS_FILES += hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_ops.o
-+else
-+_HAL_INTFS_FILES += hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_ops_linux.o
-+endif
-+endif
-+
-+ifeq ($(CONFIG_USB_HCI), y)
-+_HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8188E_USB.o
-+endif
-+ifeq ($(CONFIG_PCI_HCI), y)
-+_HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8188E_PCIE.o
-+endif
-+ifeq ($(CONFIG_SDIO_HCI), y)
-+_HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8188E_SDIO.o
-+endif
-+endif
-+
-+########### HAL_RTL8812A_RTL8821A #################################
-+
-+ifneq ($(CONFIG_RTL8812A)_$(CONFIG_RTL8821A), n_n)
-+
-+RTL871X = rtl8812a
-+ifeq ($(CONFIG_USB_HCI), y)
-+MODULE_NAME = 8812au
-+endif
-+ifeq ($(CONFIG_PCI_HCI), y)
-+MODULE_NAME = 8812ae
-+endif
-+ifeq ($(CONFIG_SDIO_HCI), y)
-+MODULE_NAME = 8812as
-+endif
-+
-+_HAL_INTFS_FILES += hal/HalPwrSeqCmd.o \
-+ hal/$(RTL871X)/Hal8812PwrSeq.o \
-+ hal/$(RTL871X)/Hal8821APwrSeq.o\
-+ hal/$(RTL871X)/$(RTL871X)_xmit.o\
-+ hal/$(RTL871X)/$(RTL871X)_sreset.o
-+
-+_HAL_INTFS_FILES += hal/$(RTL871X)/$(RTL871X)_hal_init.o \
-+ hal/$(RTL871X)/$(RTL871X)_phycfg.o \
-+ hal/$(RTL871X)/$(RTL871X)_rf6052.o \
-+ hal/$(RTL871X)/$(RTL871X)_dm.o \
-+ hal/$(RTL871X)/$(RTL871X)_rxdesc.o \
-+ hal/$(RTL871X)/$(RTL871X)_cmd.o \
-+ hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_halinit.o \
-+ hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_NAME)_led.o \
-+ hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_NAME)_xmit.o \
-+ hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_NAME)_recv.o
-+
-+ifeq ($(CONFIG_SDIO_HCI), y)
-+_HAL_INTFS_FILES += hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_ops.o
-+else
-+ifeq ($(CONFIG_GSPI_HCI), y)
-+_HAL_INTFS_FILES += hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_ops.o
-+else
-+_HAL_INTFS_FILES += hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_ops_linux.o
-+endif
-+endif
-+
-+ifeq ($(CONFIG_RTL8812A), y)
-+ifeq ($(CONFIG_USB_HCI), y)
-+_HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8812A_USB.o
-+endif
-+ifeq ($(CONFIG_PCI_HCI), y)
-+_HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8812A_PCIE.o
-+endif
-+endif
-+ifeq ($(CONFIG_RTL8821A), y)
-+ifeq ($(CONFIG_USB_HCI), y)
-+_HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8821A_USB.o
-+endif
-+ifeq ($(CONFIG_PCI_HCI), y)
-+_HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8821A_PCIE.o
-+endif
-+ifeq ($(CONFIG_SDIO_HCI), y)
-+_HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8821A_SDIO.o
-+endif
-+endif
-+
-+ifeq ($(CONFIG_RTL8812A), y)
-+EXTRA_CFLAGS += -DCONFIG_RTL8812A
-+_HAL_INTFS_FILES += hal/rtl8812a/hal8812a_fw.o
-+endif
-+
-+ifeq ($(CONFIG_RTL8821A), y)
-+
-+ifeq ($(CONFIG_RTL8812A), n)
-+
-+RTL871X = rtl8821a
-+ifeq ($(CONFIG_USB_HCI), y)
-+ifeq ($(CONFIG_BT_COEXIST), y)
-+MODULE_NAME := 8821au
-+else
-+MODULE_NAME := 8811au
-+endif
-+endif
-+ifeq ($(CONFIG_PCI_HCI), y)
-+MODULE_NAME := 8821ae
-+endif
-+ifeq ($(CONFIG_SDIO_HCI), y)
-+MODULE_NAME := 8821as
-+endif
-+
-+endif
-+
-+EXTRA_CFLAGS += -DCONFIG_RTL8821A
-+
-+_HAL_INTFS_FILES += hal/rtl8812a/hal8821a_fw.o
-+
-+endif
-+
-+ifeq ($(CONFIG_BT_COEXIST), y)
-+ifeq ($(CONFIG_RTL8812A), y)
-+_BTC_FILES += hal/btc/halbtc8812a1ant.o \
-+ hal/btc/halbtc8812a2ant.o
-+endif
-+ifeq ($(CONFIG_RTL8821A), y)
-+_BTC_FILES += hal/btc/halbtc8821a1ant.o \
-+ hal/btc/halbtc8821a2ant.o
-+endif
-+endif
-+
-+endif
-+
-+########### HAL_RTL8723B #################################
-+ifeq ($(CONFIG_RTL8723B), y)
-+
-+RTL871X = rtl8723b
-+ifeq ($(CONFIG_USB_HCI), y)
-+MODULE_NAME = 8723bu
-+endif
-+ifeq ($(CONFIG_PCI_HCI), y)
-+MODULE_NAME = 8723be
-+endif
-+ifeq ($(CONFIG_SDIO_HCI), y)
-+MODULE_NAME = 8723bs
-+endif
-+
-+EXTRA_CFLAGS += -DCONFIG_RTL8723B
-+
-+_HAL_INTFS_FILES += hal/HalPwrSeqCmd.o \
-+ hal/$(RTL871X)/Hal8723BPwrSeq.o\
-+ hal/$(RTL871X)/$(RTL871X)_sreset.o
-+
-+_HAL_INTFS_FILES += hal/$(RTL871X)/$(RTL871X)_hal_init.o \
-+ hal/$(RTL871X)/$(RTL871X)_phycfg.o \
-+ hal/$(RTL871X)/$(RTL871X)_rf6052.o \
-+ hal/$(RTL871X)/$(RTL871X)_dm.o \
-+ hal/$(RTL871X)/$(RTL871X)_rxdesc.o \
-+ hal/$(RTL871X)/$(RTL871X)_cmd.o \
-+ hal/$(RTL871X)/hal8723b_fw.o
-+
-+_HAL_INTFS_FILES += \
-+ hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_halinit.o \
-+ hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_NAME)_led.o \
-+ hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_NAME)_xmit.o \
-+ hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_NAME)_recv.o
-+
-+ifeq ($(CONFIG_PCI_HCI), y)
-+_HAL_INTFS_FILES += hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_ops_linux.o
-+else
-+_HAL_INTFS_FILES += hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_ops.o
-+endif
-+
-+ifeq ($(CONFIG_USB_HCI), y)
-+_HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8723B_USB.o
-+endif
-+ifeq ($(CONFIG_PCI_HCI), y)
-+_HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8723B_PCIE.o
-+endif
-+ifeq ($(CONFIG_SDIO_HCI), y)
-+_HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8723B_SDIO.o
-+endif
-+
-+_BTC_FILES += hal/btc/halbtc8723bwifionly.o
-+ifeq ($(CONFIG_BT_COEXIST), y)
-+_BTC_FILES += hal/btc/halbtc8723b1ant.o \
-+ hal/btc/halbtc8723b2ant.o
-+endif
-+
-+endif
-+
-+########### HAL_RTL8814A #################################
-+ifeq ($(CONFIG_RTL8814A), y)
-+## ADD NEW VHT MP HW TX MODE ##
-+#EXTRA_CFLAGS += -DCONFIG_MP_VHT_HW_TX_MODE
-+CONFIG_MP_VHT_HW_TX_MODE = n
-+##########################################
-+RTL871X = rtl8814a
-+ifeq ($(CONFIG_USB_HCI), y)
-+MODULE_NAME = 8814au
-+endif
-+
-+EXTRA_CFLAGS += -DCONFIG_RTL8814A
-+
-+_HAL_INTFS_FILES += hal/HalPwrSeqCmd.o \
-+ hal/$(RTL871X)/Hal8814PwrSeq.o \
-+ hal/$(RTL871X)/$(RTL871X)_xmit.o\
-+ hal/$(RTL871X)/$(RTL871X)_sreset.o
-+
-+_HAL_INTFS_FILES += hal/$(RTL871X)/$(RTL871X)_hal_init.o \
-+ hal/$(RTL871X)/$(RTL871X)_phycfg.o \
-+ hal/$(RTL871X)/$(RTL871X)_rf6052.o \
-+ hal/$(RTL871X)/$(RTL871X)_dm.o \
-+ hal/$(RTL871X)/$(RTL871X)_rxdesc.o \
-+ hal/$(RTL871X)/$(RTL871X)_cmd.o \
-+ hal/$(RTL871X)/hal8814a_fw.o
-+
-+
-+_HAL_INTFS_FILES += \
-+ hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_halinit.o \
-+ hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_NAME)_led.o \
-+ hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_NAME)_xmit.o \
-+ hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_NAME)_recv.o
-+
-+ifeq ($(CONFIG_SDIO_HCI), y)
-+_HAL_INTFS_FILES += hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_ops.o
-+else
-+ifeq ($(CONFIG_GSPI_HCI), y)
-+_HAL_INTFS_FILES += hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_ops.o
-+else
-+_HAL_INTFS_FILES += hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_ops_linux.o
-+endif
-+endif
-+
-+ifeq ($(CONFIG_USB_HCI), y)
-+_HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8814A_USB.o
-+endif
-+ifeq ($(CONFIG_PCI_HCI), y)
-+_HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8814A_PCIE.o
-+endif
-+
-+endif
-+
-+########### HAL_RTL8723C #################################
-+ifeq ($(CONFIG_RTL8723C), y)
-+
-+RTL871X = rtl8703b
-+ifeq ($(CONFIG_USB_HCI), y)
-+MODULE_NAME = 8723cu
-+MODULE_SUB_NAME = 8703bu
-+endif
-+ifeq ($(CONFIG_PCI_HCI), y)
-+MODULE_NAME = 8723ce
-+MODULE_SUB_NAME = 8703be
-+endif
-+ifeq ($(CONFIG_SDIO_HCI), y)
-+MODULE_NAME = 8723cs
-+MODULE_SUB_NAME = 8703bs
-+endif
-+
-+EXTRA_CFLAGS += -DCONFIG_RTL8703B
-+
-+_HAL_INTFS_FILES += hal/HalPwrSeqCmd.o \
-+ hal/$(RTL871X)/Hal8703BPwrSeq.o\
-+ hal/$(RTL871X)/$(RTL871X)_sreset.o
-+
-+_HAL_INTFS_FILES += hal/$(RTL871X)/$(RTL871X)_hal_init.o \
-+ hal/$(RTL871X)/$(RTL871X)_phycfg.o \
-+ hal/$(RTL871X)/$(RTL871X)_rf6052.o \
-+ hal/$(RTL871X)/$(RTL871X)_dm.o \
-+ hal/$(RTL871X)/$(RTL871X)_rxdesc.o \
-+ hal/$(RTL871X)/$(RTL871X)_cmd.o \
-+ hal/$(RTL871X)/hal8703b_fw.o
-+
-+_HAL_INTFS_FILES += \
-+ hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_halinit.o \
-+ hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_SUB_NAME)_led.o \
-+ hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_SUB_NAME)_xmit.o \
-+ hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_SUB_NAME)_recv.o
-+
-+ifeq ($(CONFIG_PCI_HCI), y)
-+_HAL_INTFS_FILES += hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_ops_linux.o
-+else
-+_HAL_INTFS_FILES += hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_ops.o
-+endif
-+
-+ifeq ($(CONFIG_USB_HCI), y)
-+_HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8703B_USB.o
-+endif
-+ifeq ($(CONFIG_PCI_HCI), y)
-+_HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8703B_PCIE.o
-+endif
-+
-+ifeq ($(CONFIG_BT_COEXIST), y)
-+_BTC_FILES += hal/btc/halbtc8703b1ant.o
-+endif
-+
-+endif
-+
-+########### HAL_RTL8723D #################################
-+ifeq ($(CONFIG_RTL8723D), y)
-+
-+RTL871X = rtl8723d
-+ifeq ($(CONFIG_USB_HCI), y)
-+MODULE_NAME = 8723du
-+MODULE_SUB_NAME = 8723du
-+endif
-+ifeq ($(CONFIG_PCI_HCI), y)
-+MODULE_NAME = 8723de
-+MODULE_SUB_NAME = 8723de
-+endif
-+ifeq ($(CONFIG_SDIO_HCI), y)
-+MODULE_NAME = 8723ds
-+MODULE_SUB_NAME = 8723ds
-+endif
-+
-+EXTRA_CFLAGS += -DCONFIG_RTL8723D
-+
-+_HAL_INTFS_FILES += hal/HalPwrSeqCmd.o \
-+ hal/$(RTL871X)/Hal8723DPwrSeq.o\
-+ hal/$(RTL871X)/$(RTL871X)_sreset.o
-+
-+_HAL_INTFS_FILES += hal/$(RTL871X)/$(RTL871X)_hal_init.o \
-+ hal/$(RTL871X)/$(RTL871X)_phycfg.o \
-+ hal/$(RTL871X)/$(RTL871X)_rf6052.o \
-+ hal/$(RTL871X)/$(RTL871X)_dm.o \
-+ hal/$(RTL871X)/$(RTL871X)_rxdesc.o \
-+ hal/$(RTL871X)/$(RTL871X)_cmd.o \
-+ hal/$(RTL871X)/hal8723d_fw.o \
-+ hal/$(RTL871X)/$(RTL871X)_lps_poff.o
-+
-+
-+_HAL_INTFS_FILES += \
-+ hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_halinit.o \
-+ hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_SUB_NAME)_led.o \
-+ hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_SUB_NAME)_xmit.o \
-+ hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_SUB_NAME)_recv.o
-+
-+ifeq ($(CONFIG_PCI_HCI), y)
-+_HAL_INTFS_FILES += hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_ops_linux.o
-+else
-+_HAL_INTFS_FILES += hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_ops.o
-+endif
-+
-+ifeq ($(CONFIG_USB_HCI), y)
-+_HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8723D_USB.o
-+endif
-+ifeq ($(CONFIG_PCI_HCI), y)
-+_HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8723D_PCIE.o
-+endif
-+
-+ifeq ($(CONFIG_BT_COEXIST), y)
-+_BTC_FILES += hal/btc/halbtc8723d1ant.o \
-+ hal/btc/halbtc8723d2ant.o
-+endif
-+
-+endif
-+
-+########### HAL_RTL8188F #################################
-+ifeq ($(CONFIG_RTL8188F), y)
-+
-+RTL871X = rtl8188f
-+ifeq ($(CONFIG_USB_HCI), y)
-+MODULE_NAME = 8188fu
-+endif
-+ifeq ($(CONFIG_PCI_HCI), y)
-+MODULE_NAME = 8188fe
-+endif
-+ifeq ($(CONFIG_SDIO_HCI), y)
-+MODULE_NAME = 8189fs
-+endif
-+
-+EXTRA_CFLAGS += -DCONFIG_RTL8188F
-+
-+_HAL_INTFS_FILES += hal/HalPwrSeqCmd.o \
-+ hal/$(RTL871X)/Hal8188FPwrSeq.o\
-+ hal/$(RTL871X)/$(RTL871X)_sreset.o
-+
-+_HAL_INTFS_FILES += hal/$(RTL871X)/$(RTL871X)_hal_init.o \
-+ hal/$(RTL871X)/$(RTL871X)_phycfg.o \
-+ hal/$(RTL871X)/$(RTL871X)_rf6052.o \
-+ hal/$(RTL871X)/$(RTL871X)_dm.o \
-+ hal/$(RTL871X)/$(RTL871X)_rxdesc.o \
-+ hal/$(RTL871X)/$(RTL871X)_cmd.o \
-+ hal/$(RTL871X)/hal8188f_fw.o
-+
-+_HAL_INTFS_FILES += \
-+ hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_halinit.o \
-+ hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_NAME)_led.o \
-+ hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_NAME)_xmit.o \
-+ hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_NAME)_recv.o
-+
-+ifeq ($(CONFIG_PCI_HCI), y)
-+_HAL_INTFS_FILES += hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_ops_linux.o
-+else
-+_HAL_INTFS_FILES += hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_ops.o
-+endif
-+
-+ifeq ($(CONFIG_USB_HCI), y)
-+_HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8188F_USB.o
-+endif
-+
-+ifeq ($(CONFIG_SDIO_HCI), y)
-+_HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8188F_SDIO.o
-+endif
-+
-+endif
-+
-+########### HAL_RTL8188GTV #################################
-+ifeq ($(CONFIG_RTL8188GTV), y)
-+
-+RTL871X = rtl8188gtv
-+ifeq ($(CONFIG_USB_HCI), y)
-+MODULE_NAME = 8188gtvu
-+endif
-+ifeq ($(CONFIG_SDIO_HCI), y)
-+MODULE_NAME = 8189gtvs
-+endif
-+
-+EXTRA_CFLAGS += -DCONFIG_RTL8188GTV
-+
-+_HAL_INTFS_FILES += hal/HalPwrSeqCmd.o \
-+ hal/$(RTL871X)/Hal8188GTVPwrSeq.o\
-+ hal/$(RTL871X)/$(RTL871X)_sreset.o
-+
-+_HAL_INTFS_FILES += hal/$(RTL871X)/$(RTL871X)_hal_init.o \
-+ hal/$(RTL871X)/$(RTL871X)_phycfg.o \
-+ hal/$(RTL871X)/$(RTL871X)_rf6052.o \
-+ hal/$(RTL871X)/$(RTL871X)_dm.o \
-+ hal/$(RTL871X)/$(RTL871X)_rxdesc.o \
-+ hal/$(RTL871X)/$(RTL871X)_cmd.o \
-+ hal/$(RTL871X)/hal8188gtv_fw.o
-+
-+_HAL_INTFS_FILES += \
-+ hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_halinit.o \
-+ hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_NAME)_led.o \
-+ hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_NAME)_xmit.o \
-+ hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_NAME)_recv.o
-+
-+ifeq ($(CONFIG_PCI_HCI), y)
-+_HAL_INTFS_FILES += hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_ops_linux.o
-+else
-+_HAL_INTFS_FILES += hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_ops.o
-+endif
-+
-+ifeq ($(CONFIG_USB_HCI), y)
-+_HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8188GTV_USB.o
-+endif
-+
-+ifeq ($(CONFIG_SDIO_HCI), y)
-+_HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8188GTV_SDIO.o
-+endif
-+
-+endif
-+
-+########### HAL_RTL8822B #################################
-+ifeq ($(CONFIG_RTL8822B), y)
-+RTL871X := rtl8822b
-+ifeq ($(CONFIG_USB_HCI), y)
-+ifeq ($(CONFIG_BT_COEXIST), n)
-+MODULE_NAME = 8812bu
-+else
-+MODULE_NAME = 88x2bu
-+endif
-+endif
-+ifeq ($(CONFIG_PCI_HCI), y)
-+MODULE_NAME = 88x2be
-+endif
-+ifeq ($(CONFIG_SDIO_HCI), y)
-+MODULE_NAME = 88x2bs
-+endif
-+
-+endif
-+########### HAL_RTL8821C #################################
-+ifeq ($(CONFIG_RTL8821C), y)
-+RTL871X := rtl8821c
-+ifeq ($(CONFIG_USB_HCI), y)
-+MODULE_NAME = 8821cu
-+endif
-+ifeq ($(CONFIG_PCI_HCI), y)
-+MODULE_NAME = 8821ce
-+endif
-+ifeq ($(CONFIG_SDIO_HCI), y)
-+MODULE_NAME = 8821cs
-+endif
-+
-+endif
-+
-+########### HAL_RTL8710B #################################
-+ifeq ($(CONFIG_RTL8710B), y)
-+
-+RTL871X = rtl8710b
-+ifeq ($(CONFIG_USB_HCI), y)
-+MODULE_NAME = 8710bu
-+MODULE_SUB_NAME = 8710bu
-+endif
-+
-+EXTRA_CFLAGS += -DCONFIG_RTL8710B
-+
-+_HAL_INTFS_FILES += hal/HalPwrSeqCmd.o \
-+ hal/$(RTL871X)/Hal8710BPwrSeq.o\
-+ hal/$(RTL871X)/$(RTL871X)_sreset.o
-+
-+_HAL_INTFS_FILES += hal/$(RTL871X)/$(RTL871X)_hal_init.o \
-+ hal/$(RTL871X)/$(RTL871X)_phycfg.o \
-+ hal/$(RTL871X)/$(RTL871X)_rf6052.o \
-+ hal/$(RTL871X)/$(RTL871X)_dm.o \
-+ hal/$(RTL871X)/$(RTL871X)_rxdesc.o \
-+ hal/$(RTL871X)/$(RTL871X)_cmd.o \
-+ hal/$(RTL871X)/hal8710b_fw.o \
-+ hal/$(RTL871X)/$(RTL871X)_lps_poff.o
-+
-+
-+_HAL_INTFS_FILES += \
-+ hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_halinit.o \
-+ hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_SUB_NAME)_led.o \
-+ hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_SUB_NAME)_xmit.o \
-+ hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_SUB_NAME)_recv.o
-+
-+_HAL_INTFS_FILES += hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_ops.o
-+
-+ifeq ($(CONFIG_USB_HCI), y)
-+_HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8710B_USB.o
-+endif
-+
-+endif
-+
-+########### HAL_RTL8192F #################################
-+ifeq ($(CONFIG_RTL8192F), y)
-+
-+RTL871X = rtl8192f
-+ifeq ($(CONFIG_USB_HCI), y)
-+MODULE_NAME = 8192fu
-+MODULE_SUB_NAME = 8192fu
-+endif
-+ifeq ($(CONFIG_PCI_HCI), y)
-+MODULE_NAME = 8192fe
-+MODULE_SUB_NAME = 8192fe
-+endif
-+ifeq ($(CONFIG_SDIO_HCI), y)
-+MODULE_NAME = 8192fs
-+MODULE_SUB_NAME = 8192fs
-+endif
-+
-+EXTRA_CFLAGS += -DCONFIG_RTL8192F
-+
-+_HAL_INTFS_FILES += hal/HalPwrSeqCmd.o \
-+ hal/$(RTL871X)/Hal8192FPwrSeq.o\
-+ hal/$(RTL871X)/$(RTL871X)_sreset.o
-+
-+_HAL_INTFS_FILES += hal/$(RTL871X)/$(RTL871X)_hal_init.o \
-+ hal/$(RTL871X)/$(RTL871X)_phycfg.o \
-+ hal/$(RTL871X)/$(RTL871X)_rf6052.o \
-+ hal/$(RTL871X)/$(RTL871X)_dm.o \
-+ hal/$(RTL871X)/$(RTL871X)_rxdesc.o \
-+ hal/$(RTL871X)/$(RTL871X)_cmd.o \
-+ hal/$(RTL871X)/hal8192f_fw.o \
-+ hal/$(RTL871X)/$(RTL871X)_lps_poff.o
-+
-+
-+_HAL_INTFS_FILES += \
-+ hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_halinit.o \
-+ hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_SUB_NAME)_led.o \
-+ hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_SUB_NAME)_xmit.o \
-+ hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_SUB_NAME)_recv.o
-+
-+ifeq ($(CONFIG_PCI_HCI), y)
-+_HAL_INTFS_FILES += hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_ops_linux.o
-+else
-+_HAL_INTFS_FILES += hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_ops.o
-+endif
-+
-+ifeq ($(CONFIG_SDIO_HCI), y)
-+_HAL_INTFS_FILES += hal/efuse/$(RTL871X)/HalEfuseMask8192F_SDIO.o
-+endif
-+
-+ifeq ($(CONFIG_USB_HCI), y)
-+_HAL_INTFS_FILES += hal/efuse/$(RTL871X)/HalEfuseMask8192F_USB.o
-+endif
-+
-+ifeq ($(CONFIG_PCI_HCI), y)
-+_HAL_INTFS_FILES += hal/efuse/$(RTL871X)/HalEfuseMask8192F_PCIE.o
-+endif
-+
-+endif
-+########### AUTO_CFG #################################
-+
-+ifeq ($(CONFIG_AUTOCFG_CP), y)
-+
-+ifeq ($(CONFIG_MULTIDRV), y)
-+$(shell cp $(TopDIR)/autoconf_multidrv_$(HCI_NAME)_linux.h $(TopDIR)/include/autoconf.h)
-+else
-+ifeq ($(CONFIG_RTL8188E)$(CONFIG_SDIO_HCI),yy)
-+$(shell cp $(TopDIR)/autoconf_rtl8189e_$(HCI_NAME)_linux.h $(TopDIR)/include/autoconf.h)
-+else ifeq ($(CONFIG_RTL8188F)$(CONFIG_SDIO_HCI),yy)
-+$(shell cp $(TopDIR)/autoconf_rtl8189f_$(HCI_NAME)_linux.h $(TopDIR)/include/autoconf.h)
-+else ifeq ($(CONFIG_RTL8723C),y)
-+$(shell cp $(TopDIR)/autoconf_rtl8723c_$(HCI_NAME)_linux.h $(TopDIR)/include/autoconf.h)
-+else
-+$(shell cp $(TopDIR)/autoconf_$(RTL871X)_$(HCI_NAME)_linux.h $(TopDIR)/include/autoconf.h)
-+endif
-+endif
-+
-+endif
-+
-+########### END OF PATH #################################
-+
-+ifeq ($(CONFIG_USB_HCI), y)
-+ifeq ($(CONFIG_USB_AUTOSUSPEND), y)
-+EXTRA_CFLAGS += -DCONFIG_USB_AUTOSUSPEND
-+endif
-+endif
-+
-+ifeq ($(CONFIG_MP_INCLUDED), y)
-+#MODULE_NAME := $(MODULE_NAME)_mp
-+EXTRA_CFLAGS += -DCONFIG_MP_INCLUDED
-+endif
-+
-+ifeq ($(CONFIG_POWER_SAVING), y)
-+EXTRA_CFLAGS += -DCONFIG_POWER_SAVING
-+endif
-+
-+ifeq ($(CONFIG_HW_PWRP_DETECTION), y)
-+EXTRA_CFLAGS += -DCONFIG_HW_PWRP_DETECTION
-+endif
-+
-+ifeq ($(CONFIG_BT_COEXIST), y)
-+EXTRA_CFLAGS += -DCONFIG_BT_COEXIST
-+endif
-+
-+ifeq ($(CONFIG_INTEL_WIDI), y)
-+EXTRA_CFLAGS += -DCONFIG_INTEL_WIDI
-+endif
-+
-+ifeq ($(CONFIG_WAPI_SUPPORT), y)
-+EXTRA_CFLAGS += -DCONFIG_WAPI_SUPPORT
-+endif
-+
-+
-+ifeq ($(CONFIG_EFUSE_CONFIG_FILE), y)
-+EXTRA_CFLAGS += -DCONFIG_EFUSE_CONFIG_FILE
-+
-+#EFUSE_MAP_PATH
-+USER_EFUSE_MAP_PATH ?=
-+ifneq ($(USER_EFUSE_MAP_PATH),)
-+EXTRA_CFLAGS += -DEFUSE_MAP_PATH=\"$(USER_EFUSE_MAP_PATH)\"
-+else ifeq ($(MODULE_NAME), 8189es)
-+EXTRA_CFLAGS += -DEFUSE_MAP_PATH=\"/system/etc/wifi/wifi_efuse_8189e.map\"
-+else ifeq ($(MODULE_NAME), 8723bs)
-+EXTRA_CFLAGS += -DEFUSE_MAP_PATH=\"/system/etc/wifi/wifi_efuse_8723bs.map\"
-+else
-+EXTRA_CFLAGS += -DEFUSE_MAP_PATH=\"/system/etc/wifi/wifi_efuse_$(MODULE_NAME).map\"
-+endif
-+
-+#WIFIMAC_PATH
-+USER_WIFIMAC_PATH ?=
-+ifneq ($(USER_WIFIMAC_PATH),)
-+EXTRA_CFLAGS += -DWIFIMAC_PATH=\"$(USER_WIFIMAC_PATH)\"
-+else
-+EXTRA_CFLAGS += -DWIFIMAC_PATH=\"/data/wifimac.txt\"
-+endif
-+
-+endif
-+
-+ifeq ($(CONFIG_EXT_CLK), y)
-+EXTRA_CFLAGS += -DCONFIG_EXT_CLK
-+endif
-+
-+ifeq ($(CONFIG_TRAFFIC_PROTECT), y)
-+EXTRA_CFLAGS += -DCONFIG_TRAFFIC_PROTECT
-+endif
-+
-+ifeq ($(CONFIG_LOAD_PHY_PARA_FROM_FILE), y)
-+EXTRA_CFLAGS += -DCONFIG_LOAD_PHY_PARA_FROM_FILE
-+#EXTRA_CFLAGS += -DREALTEK_CONFIG_PATH_WITH_IC_NAME_FOLDER
-+EXTRA_CFLAGS += -DREALTEK_CONFIG_PATH=\"/lib/firmware/\"
-+endif
-+
-+ifeq ($(CONFIG_TXPWR_BY_RATE), n)
-+EXTRA_CFLAGS += -DCONFIG_TXPWR_BY_RATE=0
-+else ifeq ($(CONFIG_TXPWR_BY_RATE), y)
-+EXTRA_CFLAGS += -DCONFIG_TXPWR_BY_RATE=1
-+endif
-+ifeq ($(CONFIG_TXPWR_BY_RATE_EN), n)
-+EXTRA_CFLAGS += -DCONFIG_TXPWR_BY_RATE_EN=0
-+else ifeq ($(CONFIG_TXPWR_BY_RATE_EN), y)
-+EXTRA_CFLAGS += -DCONFIG_TXPWR_BY_RATE_EN=1
-+else ifeq ($(CONFIG_TXPWR_BY_RATE_EN), auto)
-+EXTRA_CFLAGS += -DCONFIG_TXPWR_BY_RATE_EN=2
-+endif
-+
-+ifeq ($(CONFIG_TXPWR_LIMIT), n)
-+EXTRA_CFLAGS += -DCONFIG_TXPWR_LIMIT=0
-+else ifeq ($(CONFIG_TXPWR_LIMIT), y)
-+EXTRA_CFLAGS += -DCONFIG_TXPWR_LIMIT=1
-+endif
-+ifeq ($(CONFIG_TXPWR_LIMIT_EN), n)
-+EXTRA_CFLAGS += -DCONFIG_TXPWR_LIMIT_EN=0
-+else ifeq ($(CONFIG_TXPWR_LIMIT_EN), y)
-+EXTRA_CFLAGS += -DCONFIG_TXPWR_LIMIT_EN=1
-+else ifeq ($(CONFIG_TXPWR_LIMIT_EN), auto)
-+EXTRA_CFLAGS += -DCONFIG_TXPWR_LIMIT_EN=2
-+endif
-+
-+ifneq ($(CONFIG_RTW_CHPLAN), 0xFF)
-+EXTRA_CFLAGS += -DCONFIG_RTW_CHPLAN=$(CONFIG_RTW_CHPLAN)
-+endif
-+
-+ifeq ($(CONFIG_CALIBRATE_TX_POWER_BY_REGULATORY), y)
-+EXTRA_CFLAGS += -DCONFIG_CALIBRATE_TX_POWER_BY_REGULATORY
-+endif
-+
-+ifeq ($(CONFIG_CALIBRATE_TX_POWER_TO_MAX), y)
-+EXTRA_CFLAGS += -DCONFIG_CALIBRATE_TX_POWER_TO_MAX
-+endif
-+
-+ifeq ($(CONFIG_RTW_ADAPTIVITY_EN), disable)
-+EXTRA_CFLAGS += -DCONFIG_RTW_ADAPTIVITY_EN=0
-+else ifeq ($(CONFIG_RTW_ADAPTIVITY_EN), enable)
-+EXTRA_CFLAGS += -DCONFIG_RTW_ADAPTIVITY_EN=1
-+endif
-+
-+ifeq ($(CONFIG_RTW_ADAPTIVITY_MODE), normal)
-+EXTRA_CFLAGS += -DCONFIG_RTW_ADAPTIVITY_MODE=0
-+else ifeq ($(CONFIG_RTW_ADAPTIVITY_MODE), carrier_sense)
-+EXTRA_CFLAGS += -DCONFIG_RTW_ADAPTIVITY_MODE=1
-+endif
-+
-+ifeq ($(CONFIG_SIGNAL_SCALE_MAPPING), y)
-+EXTRA_CFLAGS += -DCONFIG_SIGNAL_SCALE_MAPPING
-+endif
-+
-+ifeq ($(CONFIG_80211W), y)
-+EXTRA_CFLAGS += -DCONFIG_IEEE80211W
-+endif
-+
-+ifeq ($(CONFIG_WOWLAN), y)
-+EXTRA_CFLAGS += -DCONFIG_WOWLAN -DRTW_WAKEUP_EVENT=$(CONFIG_WAKEUP_TYPE)
-+EXTRA_CFLAGS += -DRTW_SUSPEND_TYPE=$(CONFIG_SUSPEND_TYPE)
-+ifeq ($(CONFIG_WOW_STA_MIX), y)
-+EXTRA_CFLAGS += -DRTW_WOW_STA_MIX
-+endif
-+ifeq ($(CONFIG_SDIO_HCI), y)
-+EXTRA_CFLAGS += -DCONFIG_RTW_SDIO_PM_KEEP_POWER
-+endif
-+endif
-+
-+ifeq ($(CONFIG_AP_WOWLAN), y)
-+EXTRA_CFLAGS += -DCONFIG_AP_WOWLAN
-+ifeq ($(CONFIG_SDIO_HCI), y)
-+EXTRA_CFLAGS += -DCONFIG_RTW_SDIO_PM_KEEP_POWER
-+endif
-+endif
-+
-+ifeq ($(CONFIG_PNO_SUPPORT), y)
-+EXTRA_CFLAGS += -DCONFIG_PNO_SUPPORT
-+ifeq ($(CONFIG_PNO_SET_DEBUG), y)
-+EXTRA_CFLAGS += -DCONFIG_PNO_SET_DEBUG
-+endif
-+endif
-+
-+ifeq ($(CONFIG_GPIO_WAKEUP), y)
-+EXTRA_CFLAGS += -DCONFIG_GPIO_WAKEUP
-+ifeq ($(CONFIG_ONE_PIN_GPIO), y)
-+EXTRA_CFLAGS += -DCONFIG_RTW_ONE_PIN_GPIO
-+endif
-+ifeq ($(CONFIG_HIGH_ACTIVE_DEV2HST), y)
-+EXTRA_CFLAGS += -DHIGH_ACTIVE_DEV2HST=1
-+else
-+EXTRA_CFLAGS += -DHIGH_ACTIVE_DEV2HST=0
-+endif
-+endif
-+
-+ifeq ($(CONFIG_HIGH_ACTIVE_HST2DEV), y)
-+EXTRA_CFLAGS += -DHIGH_ACTIVE_HST2DEV=1
-+else
-+EXTRA_CFLAGS += -DHIGH_ACTIVE_HST2DEV=0
-+endif
-+
-+ifneq ($(CONFIG_WAKEUP_GPIO_IDX), default)
-+EXTRA_CFLAGS += -DWAKEUP_GPIO_IDX=$(CONFIG_WAKEUP_GPIO_IDX)
-+endif
-+
-+ifeq ($(CONFIG_RTW_SDIO_PM_KEEP_POWER), y)
-+ifeq ($(CONFIG_SDIO_HCI), y)
-+EXTRA_CFLAGS += -DCONFIG_RTW_SDIO_PM_KEEP_POWER
-+endif
-+endif
-+
-+ifeq ($(CONFIG_REDUCE_TX_CPU_LOADING), y)
-+EXTRA_CFLAGS += -DCONFIG_REDUCE_TX_CPU_LOADING
-+endif
-+
-+ifeq ($(CONFIG_BR_EXT), y)
-+BR_NAME = br0
-+EXTRA_CFLAGS += -DCONFIG_BR_EXT
-+EXTRA_CFLAGS += '-DCONFIG_BR_EXT_BRNAME="'$(BR_NAME)'"'
-+endif
-+
-+
-+ifeq ($(CONFIG_TDLS), y)
-+EXTRA_CFLAGS += -DCONFIG_TDLS
-+endif
-+
-+ifeq ($(CONFIG_WIFI_MONITOR), y)
-+EXTRA_CFLAGS += -DCONFIG_WIFI_MONITOR
-+endif
-+
-+ifeq ($(CONFIG_MCC_MODE), y)
-+EXTRA_CFLAGS += -DCONFIG_MCC_MODE
-+endif
-+
-+ifeq ($(CONFIG_RTW_NAPI), y)
-+EXTRA_CFLAGS += -DCONFIG_RTW_NAPI
-+endif
-+
-+ifeq ($(CONFIG_RTW_GRO), y)
-+EXTRA_CFLAGS += -DCONFIG_RTW_GRO
-+endif
-+
-+ifeq ($(CONFIG_RTW_REPEATER_SON), y)
-+EXTRA_CFLAGS += -DCONFIG_RTW_REPEATER_SON
-+endif
-+
-+ifeq ($(CONFIG_RTW_IPCAM_APPLICATION), y)
-+EXTRA_CFLAGS += -DCONFIG_RTW_IPCAM_APPLICATION
-+ifeq ($(CONFIG_WIFI_MONITOR), n)
-+EXTRA_CFLAGS += -DCONFIG_WIFI_MONITOR
-+endif
-+endif
-+
-+ifeq ($(CONFIG_RTW_NETIF_SG), y)
-+EXTRA_CFLAGS += -DCONFIG_RTW_NETIF_SG
-+endif
-+
-+ifeq ($(CONFIG_TX_CSUM_OFFLOAD), y)
-+EXTRA_CFLAGS += -DCONFIG_TX_CSUM_OFFLOAD
-+endif
-+
-+ifeq ($(CONFIG_ICMP_VOQ), y)
-+EXTRA_CFLAGS += -DCONFIG_ICMP_VOQ
-+endif
-+
-+ifeq ($(CONFIG_IP_R_MONITOR), y)
-+EXTRA_CFLAGS += -DCONFIG_IP_R_MONITOR
-+endif
-+
-+ifeq ($(CONFIG_RTW_WIFI_HAL), y)
-+#EXTRA_CFLAGS += -DCONFIG_RTW_WIFI_HAL_DEBUG
-+EXTRA_CFLAGS += -DCONFIG_RTW_WIFI_HAL
-+EXTRA_CFLAGS += -DCONFIG_RTW_CFGVEDNOR_LLSTATS
-+EXTRA_CFLAGS += -DCONFIG_RTW_CFGVENDOR_RANDOM_MAC_OUI
-+EXTRA_CFLAGS += -DCONFIG_RTW_CFGVEDNOR_RSSIMONITOR
-+EXTRA_CFLAGS += -DCONFIG_RTW_CFGVENDOR_WIFI_LOGGER
-+endif
-+
-+ifeq ($(CONFIG_MP_VHT_HW_TX_MODE), y)
-+EXTRA_CFLAGS += -DCONFIG_MP_VHT_HW_TX_MODE
-+ifeq ($(CONFIG_PLATFORM_I386_PC), y)
-+## For I386 X86 ToolChain use Hardware FLOATING
-+EXTRA_CFLAGS += -mhard-float
-+EXTRA_CFLAGS += -DMARK_KERNEL_PFU
-+else
-+## For ARM ToolChain use Hardware FLOATING
-+# Raspbian kernel is with soft-float.
-+# 'softfp' allows FP instructions, but no FP on function call interfaces
-+EXTRA_CFLAGS += -mfloat-abi=softfp
-+endif
-+endif
-+
-+ifeq ($(CONFIG_APPEND_VENDOR_IE_ENABLE), y)
-+EXTRA_CFLAGS += -DCONFIG_APPEND_VENDOR_IE_ENABLE
-+endif
-+
-+ifeq ($(CONFIG_RTW_DEBUG), y)
-+EXTRA_CFLAGS += -DCONFIG_RTW_DEBUG
-+EXTRA_CFLAGS += -DRTW_LOG_LEVEL=$(CONFIG_RTW_LOG_LEVEL)
-+endif
-+
-+EXTRA_CFLAGS += -DDM_ODM_SUPPORT_TYPE=0x04
-+
-+ifeq ($(CONFIG_PLATFORM_I386_PC), y)
-+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
-+EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
-+SUBARCH := $(shell uname -m | sed -e "s/i.86/i386/; s/ppc/powerpc/; s/armv.l/arm/; s/aarch64/arm64/;")
-+ARCH ?= $(SUBARCH)
-+CROSS_COMPILE ?=
-+KVER := $(shell uname -r)
-+KSRC := /lib/modules/$(KVER)/build
-+MODDESTDIR := /lib/modules/$(KVER)/kernel/drivers/net/wireless/
-+INSTALL_PREFIX :=
-+STAGINGMODDIR := /lib/modules/$(KVER)/kernel/drivers/staging
-+endif
-+
-+ifeq ($(CONFIG_PLATFORM_ARM_RPI), y)
-+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
-+EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
-+ARCH ?= arm
-+CROSS_COMPILE ?=
-+KVER ?= $(shell uname -r)
-+KSRC := /lib/modules/$(KVER)/build
-+MODDESTDIR := /lib/modules/$(KVER)/kernel/drivers/net/wireless/
-+INSTALL_PREFIX :=
-+endif
-+
-+ifeq ($(CONFIG_PLATFORM_ARM64_RPI), y)
-+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
-+EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
-+ARCH ?= arm64
-+CROSS_COMPILE ?=
-+KVER ?= $(shell uname -r)
-+KSRC := /lib/modules/$(KVER)/build
-+MODDESTDIR := /lib/modules/$(KVER)/kernel/drivers/net/wireless/
-+INSTALL_PREFIX :=
-+endif
-+
-+ifeq ($(CONFIG_PLATFORM_ARM_NV_NANO), y)
-+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
-+EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
-+ARCH := arm64
-+KVER := $(shell uname -r)
-+KSRC := /lib/modules/$(KVER)/build
-+MODDESTDIR := /lib/modules/$(KVER)/kernel/drivers/net/wireless/
-+INSTALL_PREFIX :=
-+STAGINGMODDIR := /lib/modules/$(KVER)/kernel/drivers/staging
-+endif
-+
-+ifeq ($(CONFIG_PLATFORM_ARM_ODROIDC2), y)
-+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
-+EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
-+ARCH ?= arm64
-+CROSS_COMPILE ?=
-+KVER ?= $(shell uname -r)
-+KSRC := /lib/modules/$(KVER)/build
-+MODDESTDIR := /lib/modules/$(KVER)/kernel/drivers/net/wireless/
-+INSTALL_PREFIX :=
-+endif
-+
-+ifeq ($(CONFIG_PLATFORM_PPC), y)
-+EXTRA_CFLAGS += -DCONFIG_BIG_ENDIAN
-+SUBARCH := $(shell uname -m | sed -e s/ppc/powerpc/)
-+ARCH ?= $(SUBARCH)
-+CROSS_COMPILE ?=
-+KVER ?= $(shell uname -r)
-+KSRC := /lib/modules/$(KVER)/build
-+MODDESTDIR := /lib/modules/$(KVER)/kernel/drivers/net/wireless/
-+INSTALL_PREFIX :=
-+endif
-+
-+ifeq ($(CONFIG_PLATFORM_NV_TK1), y)
-+EXTRA_CFLAGS += -DCONFIG_PLATFORM_NV_TK1
-+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
-+# default setting for Android 4.1, 4.2
-+EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
-+EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
-+EXTRA_CFLAGS += -DCONFIG_P2P_IPS -DCONFIG_PLATFORM_ANDROID
-+# Enable this for Android 5.0
-+EXTRA_CFLAGS += -DCONFIG_RADIO_WORK
-+EXTRA_CFLAGS += -DRTW_VENDOR_EXT_SUPPORT
-+EXTRA_CFLAGS += -DRTW_ENABLE_WIFI_CONTROL_FUNC
-+ARCH ?= arm
-+
-+CROSS_COMPILE := /mnt/newdisk/android_sdk/nvidia_tk1/android_L/prebuilts/gcc/linux-x86/arm/arm-eabi-4.8/bin/arm-eabi-
-+KSRC :=/mnt/newdisk/android_sdk/nvidia_tk1/android_L/out/target/product/shieldtablet/obj/KERNEL/
-+MODULE_NAME = wlan
-+endif
-+
-+ifeq ($(CONFIG_PLATFORM_NV_TK1_UBUNTU), y)
-+EXTRA_CFLAGS += -DCONFIG_PLATFORM_NV_TK1
-+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
-+EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
-+
-+ARCH ?= arm
-+
-+CROSS_COMPILE ?=
-+KVER := $(shell uname -r)
-+KSRC := /lib/modules/$(KVER)/build
-+MODDESTDIR := /lib/modules/$(KVER)/kernel/drivers/net/wireless/
-+INSTALL_PREFIX :=
-+endif
-+
-+ifeq ($(CONFIG_PLATFORM_ACTIONS_ATM702X), y)
-+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_PLATFORM_ANDROID -DCONFIG_PLATFORM_ACTIONS_ATM702X
-+#ARCH := arm
-+ARCH := $(R_ARCH)
-+#CROSS_COMPILE := arm-none-linux-gnueabi-
-+CROSS_COMPILE := $(R_CROSS_COMPILE)
-+KVER:= 3.4.0
-+#KSRC := ../../../../build/out/kernel
-+KSRC := $(KERNEL_BUILD_PATH)
-+MODULE_NAME :=wlan
-+endif
-+
-+ifeq ($(CONFIG_PLATFORM_ACTIONS_ATM705X), y)
-+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
-+#EXTRA_CFLAGS += -DRTW_ENABLE_WIFI_CONTROL_FUNC
-+# default setting for Android 4.1, 4.2, 4.3, 4.4
-+EXTRA_CFLAGS += -DCONFIG_PLATFORM_ACTIONS_ATM705X
-+EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
-+EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
-+
-+# Enable this for Android 5.0
-+EXTRA_CFLAGS += -DCONFIG_RADIO_WORK
-+
-+ifeq ($(CONFIG_SDIO_HCI), y)
-+EXTRA_CFLAGS += -DCONFIG_PLATFORM_OPS
-+_PLATFORM_FILES += platform/platform_arm_act_sdio.o
-+endif
-+
-+ARCH := arm
-+CROSS_COMPILE := /opt/arm-2011.09/bin/arm-none-linux-gnueabi-
-+KSRC := /home/android_sdk/Action-semi/705a_android_L/android/kernel
-+endif
-+
-+ifeq ($(CONFIG_PLATFORM_ARM_SUN50IW1P1), y)
-+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
-+EXTRA_CFLAGS += -DCONFIG_PLATFORM_ARM_SUN50IW1P1
-+EXTRA_CFLAGS += -DCONFIG_TRAFFIC_PROTECT
-+# default setting for Android 4.1, 4.2
-+EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
-+EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
-+EXTRA_CFLAGS += -DCONFIG_RESUME_IN_WORKQUEUE
-+EXTRA_CFLAGS += -DCONFIG_PLATFORM_OPS
-+
-+# Enable this for Android 5.0
-+EXTRA_CFLAGS += -DCONFIG_RADIO_WORK
-+
-+ifeq ($(CONFIG_USB_HCI), y)
-+EXTRA_CFLAGS += -DCONFIG_USE_USB_BUFFER_ALLOC_TX
-+_PLATFORM_FILES += platform/platform_ARM_SUNxI_usb.o
-+endif
-+ifeq ($(CONFIG_SDIO_HCI), y)
-+_PLATFORM_FILES += platform/platform_ARM_SUN50IW1P1_sdio.o
-+endif
-+
-+ARCH := arm64
-+# ===Cross compile setting for Android 5.1(64) SDK ===
-+CROSS_COMPILE := /home/android_sdk/Allwinner/a64/android-51/lichee/out/sun50iw1p1/android/common/buildroot/external-toolchain/bin/aarch64-linux-gnu-
-+KSRC :=/home/android_sdk/Allwinner/a64/android-51/lichee/linux-3.10/
-+endif
-+
-+ifeq ($(CONFIG_PLATFORM_TI_AM3517), y)
-+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_PLATFORM_ANDROID -DCONFIG_PLATFORM_SHUTTLE
-+CROSS_COMPILE := arm-eabi-
-+KSRC := $(shell pwd)/../../../Android/kernel
-+ARCH := arm
-+endif
-+
-+ifeq ($(CONFIG_PLATFORM_MSTAR_TITANIA12), y)
-+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_PLATFORM_MSTAR -DCONFIG_PLATFORM_MSTAR_TITANIA12
-+ARCH:=mips
-+CROSS_COMPILE:= /usr/src/Mstar_kernel/mips-4.3/bin/mips-linux-gnu-
-+KVER:= 2.6.28.9
-+KSRC:= /usr/src/Mstar_kernel/2.6.28.9/
-+endif
-+
-+ifeq ($(CONFIG_PLATFORM_MSTAR), y)
-+EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
-+EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
-+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
-+EXTRA_CFLAGS += -DCONFIG_PLATFORM_MSTAR
-+EXTRA_CFLAGS += -DCONFIG_PLATFORM_MSTAR_HIGH
-+ifeq ($(CONFIG_USB_HCI), y)
-+EXTRA_CFLAGS += -DCONFIG_USE_USB_BUFFER_ALLOC_TX -DCONFIG_FIX_NR_BULKIN_BUFFER
-+endif
-+ARCH:=arm
-+CROSS_COMPILE:= /usr/src/bin/arm-none-linux-gnueabi-
-+KVER:= 3.1.10
-+KSRC:= /usr/src/Mstar_kernel/3.1.10/
-+endif
-+
-+ifeq ($(CONFIG_PLATFORM_ANDROID_ARM64), y)
-+# For this to work, change the "modules:" section is also needed, in order to build with CLANG.
-+# "$(MAKE) ARCH=$(ARCH) SUBARCH=$(ARCH) REAL_CC=${CC_DIR}/clang CLANG_TRIPLE=aarch64-linux-gnu- CROSS_COMPILE=$(CROSS_COMPILE) -C $(KSRC) M=$(shell pwd) O="$(KBUILD_OUTPUT)" modules"
-+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -fno-pic
-+EXTRA_CFLAGS += -DRTW_ENABLE_WIFI_CONTROL_FUNC -DCONFIG_RADIO_WORK
-+#Enable this to have two interfaces:
-+#EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
-+EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
-+EXTRA_CFLAGS += -DCONFIG_P2P_IPS
-+endif
-+
-+ifeq ($(CONFIG_PLATFORM_ANDROID_X86), y)
-+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
-+SUBARCH := $(shell uname -m | sed -e s/i.86/i386/)
-+ARCH := $(SUBARCH)
-+CROSS_COMPILE := /media/DATA-2/android-x86/ics-x86_20120130/prebuilt/linux-x86/toolchain/i686-unknown-linux-gnu-4.2.1/bin/i686-unknown-linux-gnu-
-+KSRC := /media/DATA-2/android-x86/ics-x86_20120130/out/target/product/generic_x86/obj/kernel
-+MODULE_NAME :=wlan
-+endif
-+
-+ifeq ($(CONFIG_PLATFORM_ANDROID_INTEL_X86), y)
-+EXTRA_CFLAGS += -DCONFIG_PLATFORM_ANDROID_INTEL_X86
-+EXTRA_CFLAGS += -DCONFIG_PLATFORM_INTEL_BYT
-+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_PLATFORM_ANDROID
-+EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
-+EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
-+EXTRA_CFLAGS += -DCONFIG_SKIP_SIGNAL_SCALE_MAPPING
-+ifeq ($(CONFIG_SDIO_HCI), y)
-+EXTRA_CFLAGS += -DCONFIG_RESUME_IN_WORKQUEUE
-+endif
-+endif
-+
-+ifeq ($(CONFIG_PLATFORM_JB_X86), y)
-+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
-+EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
-+EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
-+SUBARCH := $(shell uname -m | sed -e s/i.86/i386/)
-+ARCH := $(SUBARCH)
-+CROSS_COMPILE := /home/android_sdk/android-x86_JB/prebuilts/gcc/linux-x86/x86/i686-linux-android-4.7/bin/i686-linux-android-
-+KSRC := /home/android_sdk/android-x86_JB/out/target/product/x86/obj/kernel/
-+MODULE_NAME :=wlan
-+endif
-+
-+ifeq ($(CONFIG_PLATFORM_ARM_PXA2XX), y)
-+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
-+ARCH := arm
-+CROSS_COMPILE := arm-none-linux-gnueabi-
-+KVER := 2.6.34.1
-+KSRC ?= /usr/src/linux-2.6.34.1
-+endif
-+
-+ifeq ($(CONFIG_PLATFORM_ARM_S3C2K4), y)
-+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
-+ARCH := arm
-+CROSS_COMPILE := arm-linux-
-+KVER := 2.6.24.7_$(ARCH)
-+KSRC := /usr/src/kernels/linux-$(KVER)
-+endif
-+
-+ifeq ($(CONFIG_PLATFORM_ARM_S3C6K4), y)
-+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
-+ARCH := arm
-+CROSS_COMPILE := arm-none-linux-gnueabi-
-+KVER := 2.6.34.1
-+KSRC ?= /usr/src/linux-2.6.34.1
-+endif
-+
-+ifeq ($(CONFIG_PLATFORM_RTD2880B), y)
-+EXTRA_CFLAGS += -DCONFIG_BIG_ENDIAN -DCONFIG_PLATFORM_RTD2880B
-+ARCH:=
-+CROSS_COMPILE:=
-+KVER:=
-+KSRC:=
-+endif
-+
-+ifeq ($(CONFIG_PLATFORM_MIPS_RMI), y)
-+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
-+ARCH:=mips
-+CROSS_COMPILE:=mipsisa32r2-uclibc-
-+KVER:=
-+KSRC:= /root/work/kernel_realtek
-+endif
-+
-+ifeq ($(CONFIG_PLATFORM_MIPS_PLM), y)
-+EXTRA_CFLAGS += -DCONFIG_BIG_ENDIAN
-+ARCH:=mips
-+CROSS_COMPILE:=mipsisa32r2-uclibc-
-+KVER:=
-+KSRC:= /root/work/kernel_realtek
-+endif
-+
-+ifeq ($(CONFIG_PLATFORM_MSTAR389), y)
-+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_PLATFORM_MSTAR389
-+ARCH:=mips
-+CROSS_COMPILE:= mips-linux-gnu-
-+KVER:= 2.6.28.10
-+KSRC:= /home/mstar/mstar_linux/2.6.28.9/
-+endif
-+
-+ifeq ($(CONFIG_PLATFORM_MIPS_AR9132), y)
-+EXTRA_CFLAGS += -DCONFIG_BIG_ENDIAN
-+ARCH := mips
-+CROSS_COMPILE := mips-openwrt-linux-
-+KSRC := /home/alex/test_openwrt/tmp/linux-2.6.30.9
-+endif
-+
-+# This is how I built for openwrt Neo2 platform. --Ben
-+ifeq ($(CONFIG_PLATFORM_OPENWRT_NEO2), y)
-+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
-+ARCH := arm64
-+CROSS_COMPILE := aarch64-openwrt-linux-
-+#export PATH=$PATH:/home/greearb/git/openwrt-neo2-dev/staging_dir/toolchain-aarch64_cortex-a53_gcc-7.3.0_musl/bin/
-+#export STAGING_DIR=/home/greearb/git/openwrt-neo2-dev/staging_dir
-+KSRC := /home/greearb/git/openwrt-neo2-dev/build_dir/target-aarch64_cortex-a53_musl/linux-sunxi_cortexa53/linux-4.14.78
-+endif
-+
-+ifeq ($(CONFIG_PLATFORM_DMP_PHILIPS), y)
-+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DRTK_DMP_PLATFORM
-+ARCH := mips
-+#CROSS_COMPILE:=/usr/local/msdk-4.3.6-mips-EL-2.6.12.6-0.9.30.3/bin/mipsel-linux-
-+CROSS_COMPILE:=/usr/local/toolchain_mipsel/bin/mipsel-linux-
-+KSRC ?=/usr/local/Jupiter/linux-2.6.12
-+endif
-+
-+ifeq ($(CONFIG_PLATFORM_RTK_DMP), y)
-+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DRTK_DMP_PLATFORM -DCONFIG_WIRELESS_EXT
-+EXTRA_CFLAGS += -DCONFIG_PLATFORM_OPS
-+ifeq ($(CONFIG_USB_HCI), y)
-+_PLATFORM_FILES += platform/platform_RTK_DMP_usb.o
-+endif
-+ARCH:=mips
-+CROSS_COMPILE:=mipsel-linux-
-+KVER:=
-+KSRC ?= /usr/src/DMP_Kernel/jupiter/linux-2.6.12
-+endif
-+
-+ifeq ($(CONFIG_PLATFORM_MT53XX), y)
-+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_PLATFORM_MT53XX
-+ARCH:= arm
-+CROSS_COMPILE:= arm11_mtk_le-
-+KVER:= 2.6.27
-+KSRC?= /proj/mtk00802/BD_Compare/BDP/Dev/BDP_V301/BDP_Linux/linux-2.6.27
-+endif
-+
-+ifeq ($(CONFIG_PLATFORM_ARM_MX51_241H), y)
-+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_WISTRON_PLATFORM
-+ARCH := arm
-+CROSS_COMPILE := /opt/freescale/usr/local/gcc-4.1.2-glibc-2.5-nptl-3/arm-none-linux-gnueabi/bin/arm-none-linux-gnueabi-
-+KVER := 2.6.31
-+KSRC ?= /lib/modules/2.6.31-770-g0e46b52/source
-+endif
-+
-+ifeq ($(CONFIG_PLATFORM_FS_MX61), y)
-+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
-+EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
-+ARCH := arm
-+CROSS_COMPILE ?=
-+KVER ?= $(shell uname -r)
-+KSRC := /lib/modules/$(KVER)/build
-+MODDESTDIR := /lib/modules/$(KVER)/kernel/drivers/net/wireless/
-+INSTALL_PREFIX :=
-+endif
-+
-+ifeq ($(CONFIG_PLATFORM_ACTIONS_ATJ227X), y)
-+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_PLATFORM_ACTIONS_ATJ227X
-+ARCH := mips
-+CROSS_COMPILE := /home/cnsd4/project/actions/tools-2.6.27/bin/mipsel-linux-gnu-
-+KVER := 2.6.27
-+KSRC := /home/cnsd4/project/actions/linux-2.6.27.28
-+endif
-+
-+ifeq ($(CONFIG_PLATFORM_TI_DM365), y)
-+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_PLATFORM_TI_DM365
-+EXTRA_CFLAGS += -DCONFIG_USE_USB_BUFFER_ALLOC_RX
-+EXTRA_CFLAGS += -DCONFIG_SINGLE_XMIT_BUF -DCONFIG_SINGLE_RECV_BUF
-+ARCH := arm
-+#CROSS_COMPILE := /home/cnsd4/Appro/mv_pro_5.0/montavista/pro/devkit/arm/v5t_le/bin/arm_v5t_le-
-+#KSRC := /home/cnsd4/Appro/mv_pro_5.0/montavista/pro/devkit/lsp/ti-davinci/linux-dm365
-+CROSS_COMPILE := /opt/montavista/pro5.0/devkit/arm/v5t_le/bin/arm-linux-
-+KSRC:= /home/vivotek/lsp/DM365/kernel_platform/kernel/linux-2.6.18
-+KERNELOUTPUT := ${PRODUCTDIR}/tmp
-+KVER := 2.6.18
-+endif
-+
-+ifeq ($(CONFIG_PLATFORM_MOZART), y)
-+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_PLATFORM_MOZART
-+ARCH := arm
-+CROSS_COMPILE := /home/vivotek/lsp/mozart3v2/Mozart3e_Toolchain/build_arm_nofpu/usr/bin/arm-linux-
-+KVER := $(shell uname -r)
-+KSRC:= /opt/Vivotek/lsp/mozart3v2/kernel_platform/kernel/mozart_kernel-1.17
-+KERNELOUTPUT := /home/pink/sample/ODM/IP8136W-VINT/tmp/kernel
-+endif
-+
-+ifeq ($(CONFIG_PLATFORM_TEGRA3_CARDHU), y)
-+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
-+# default setting for Android 4.1, 4.2
-+EXTRA_CFLAGS += -DRTW_ENABLE_WIFI_CONTROL_FUNC
-+EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
-+EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
-+ARCH := arm
-+CROSS_COMPILE := /home/android_sdk/nvidia/tegra-16r3-partner-android-4.1_20120723/prebuilt/linux-x86/toolchain/arm-eabi-4.4.3/bin/arm-eabi-
-+KSRC := /home/android_sdk/nvidia/tegra-16r3-partner-android-4.1_20120723/out/target/product/cardhu/obj/KERNEL
-+MODULE_NAME := wlan
-+endif
-+
-+ifeq ($(CONFIG_PLATFORM_TEGRA4_DALMORE), y)
-+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
-+# default setting for Android 4.1, 4.2
-+EXTRA_CFLAGS += -DRTW_ENABLE_WIFI_CONTROL_FUNC
-+EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
-+EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
-+ARCH := arm
-+CROSS_COMPILE := /home/android_sdk/nvidia/tegra-17r9-partner-android-4.2-dalmore_20130131/prebuilts/gcc/linux-x86/arm/arm-eabi-4.6/bin/arm-eabi-
-+KSRC := /home/android_sdk/nvidia/tegra-17r9-partner-android-4.2-dalmore_20130131/out/target/product/dalmore/obj/KERNEL
-+MODULE_NAME := wlan
-+endif
-+
-+ifeq ($(CONFIG_PLATFORM_ARM_TCC8900), y)
-+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
-+ARCH := arm
-+CROSS_COMPILE := /home/android_sdk/Telechips/SDK_2304_20110613/prebuilt/linux-x86/toolchain/arm-eabi-4.4.3/bin/arm-eabi-
-+KSRC := /home/android_sdk/Telechips/SDK_2304_20110613/kernel
-+MODULE_NAME := wlan
-+endif
-+
-+ifeq ($(CONFIG_PLATFORM_ARM_TCC8920), y)
-+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
-+ARCH := arm
-+CROSS_COMPILE := /home/android_sdk/Telechips/v12.06_r1-tcc-android-4.0.4/prebuilt/linux-x86/toolchain/arm-eabi-4.4.3/bin/arm-eabi-
-+KSRC := /home/android_sdk/Telechips/v12.06_r1-tcc-android-4.0.4/kernel
-+MODULE_NAME := wlan
-+endif
-+
-+ifeq ($(CONFIG_PLATFORM_ARM_TCC8920_JB42), y)
-+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
-+# default setting for Android 4.1, 4.2
-+EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
-+EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
-+ARCH := arm
-+CROSS_COMPILE := /home/android_sdk/Telechips/v13.03_r1-tcc-android-4.2.2_ds_patched/prebuilts/gcc/linux-x86/arm/arm-eabi-4.6/bin/arm-eabi-
-+KSRC := /home/android_sdk/Telechips/v13.03_r1-tcc-android-4.2.2_ds_patched/kernel
-+MODULE_NAME := wlan
-+endif
-+
-+ifeq ($(CONFIG_PLATFORM_ARM_RK2818), y)
-+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_PLATFORM_ANDROID -DCONFIG_PLATFORM_ROCKCHIPS
-+ARCH := arm
-+CROSS_COMPILE := /usr/src/release_fae_version/toolchain/arm-eabi-4.4.0/bin/arm-eabi-
-+KSRC := /usr/src/release_fae_version/kernel25_A7_281x
-+MODULE_NAME := wlan
-+endif
-+
-+ifeq ($(CONFIG_PLATFORM_ARM_RK3188), y)
-+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_PLATFORM_ANDROID -DCONFIG_PLATFORM_ROCKCHIPS
-+# default setting for Android 4.1, 4.2, 4.3, 4.4
-+EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
-+EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
-+# default setting for Power control
-+EXTRA_CFLAGS += -DRTW_ENABLE_WIFI_CONTROL_FUNC
-+EXTRA_CFLAGS += -DRTW_SUPPORT_PLATFORM_SHUTDOWN
-+# default setting for Special function
-+ARCH := arm
-+CROSS_COMPILE := /home/android_sdk/Rockchip/Rk3188/prebuilts/gcc/linux-x86/arm/arm-eabi-4.6/bin/arm-eabi-
-+KSRC := /home/android_sdk/Rockchip/Rk3188/kernel
-+MODULE_NAME := wlan
-+endif
-+
-+ifeq ($(CONFIG_PLATFORM_ARM_RK3066), y)
-+EXTRA_CFLAGS += -DCONFIG_PLATFORM_ARM_RK3066
-+EXTRA_CFLAGS += -DRTW_ENABLE_WIFI_CONTROL_FUNC
-+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
-+EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
-+EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211
-+ifeq ($(CONFIG_SDIO_HCI), y)
-+EXTRA_CFLAGS += -DRTW_SUPPORT_PLATFORM_SHUTDOWN
-+endif
-+EXTRA_CFLAGS += -fno-pic
-+ARCH := arm
-+CROSS_COMPILE := /home/android_sdk/Rockchip/rk3066_20130607/prebuilts/gcc/linux-x86/arm/arm-linux-androideabi-4.6/bin/arm-linux-androideabi-
-+#CROSS_COMPILE := /home/android_sdk/Rockchip/Rk3066sdk/prebuilts/gcc/linux-x86/arm/arm-linux-androideabi-4.6/bin/arm-linux-androideabi-
-+KSRC := /home/android_sdk/Rockchip/Rk3066sdk/kernel
-+MODULE_NAME :=wlan
-+endif
-+
-+ifeq ($(CONFIG_PLATFORM_ARM_URBETTER), y)
-+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN #-DCONFIG_MINIMAL_MEMORY_USAGE
-+ARCH := arm
-+CROSS_COMPILE := /media/DATA-1/urbetter/arm-2009q3/bin/arm-none-linux-gnueabi-
-+KSRC := /media/DATA-1/urbetter/ics-urbetter/kernel
-+MODULE_NAME := wlan
-+endif
-+
-+ifeq ($(CONFIG_PLATFORM_ARM_TI_PANDA), y)
-+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN #-DCONFIG_MINIMAL_MEMORY_USAGE
-+ARCH := arm
-+#CROSS_COMPILE := /media/DATA-1/aosp/ics-aosp_20111227/prebuilt/linux-x86/toolchain/arm-eabi-4.4.3/bin/arm-eabi-
-+#KSRC := /media/DATA-1/aosp/android-omap-panda-3.0_20120104
-+CROSS_COMPILE := /media/DATA-1/android-4.0/prebuilt/linux-x86/toolchain/arm-eabi-4.4.3/bin/arm-eabi-
-+KSRC := /media/DATA-1/android-4.0/panda_kernel/omap
-+MODULE_NAME := wlan
-+endif
-+
-+ifeq ($(CONFIG_PLATFORM_MIPS_JZ4760), y)
-+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_MINIMAL_MEMORY_USAGE
-+ARCH ?= mips
-+CROSS_COMPILE ?= /mnt/sdb5/Ingenic/Umido/mips-4.3/bin/mips-linux-gnu-
-+KSRC ?= /mnt/sdb5/Ingenic/Umido/kernel
-+endif
-+
-+ifeq ($(CONFIG_PLATFORM_SZEBOOK), y)
-+EXTRA_CFLAGS += -DCONFIG_BIG_ENDIAN
-+ARCH:=arm
-+CROSS_COMPILE:=/opt/crosstool2/bin/armeb-unknown-linux-gnueabi-
-+KVER:= 2.6.31.6
-+KSRC:= ../code/linux-2.6.31.6-2020/
-+endif
-+
-+ifeq ($(CONFIG_PLATFORM_ARM_SUNxI), y)
-+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
-+EXTRA_CFLAGS += -DCONFIG_PLATFORM_ARM_SUNxI
-+# default setting for Android 4.1, 4.2
-+EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
-+EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
-+
-+EXTRA_CFLAGS += -DCONFIG_PLATFORM_OPS
-+ifeq ($(CONFIG_USB_HCI), y)
-+EXTRA_CFLAGS += -DCONFIG_USE_USB_BUFFER_ALLOC_TX
-+_PLATFORM_FILES += platform/platform_ARM_SUNxI_usb.o
-+endif
-+ifeq ($(CONFIG_SDIO_HCI), y)
-+# default setting for A10-EVB mmc0
-+#EXTRA_CFLAGS += -DCONFIG_WITS_EVB_V13
-+_PLATFORM_FILES += platform/platform_ARM_SUNxI_sdio.o
-+endif
-+
-+ARCH := arm
-+#CROSS_COMPILE := arm-none-linux-gnueabi-
-+CROSS_COMPILE=/home/android_sdk/Allwinner/a10/android-jb42/lichee-jb42/buildroot/output/external-toolchain/bin/arm-none-linux-gnueabi-
-+KVER := 3.0.8
-+#KSRC:= ../lichee/linux-3.0/
-+KSRC=/home/android_sdk/Allwinner/a10/android-jb42/lichee-jb42/linux-3.0
-+endif
-+
-+ifeq ($(CONFIG_PLATFORM_ARM_SUN6I), y)
-+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
-+EXTRA_CFLAGS += -DCONFIG_PLATFORM_ARM_SUN6I
-+EXTRA_CFLAGS += -DCONFIG_TRAFFIC_PROTECT
-+# default setting for Android 4.1, 4.2, 4.3, 4.4
-+EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
-+EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
-+EXTRA_CFLAGS += -DCONFIG_QOS_OPTIMIZATION
-+
-+EXTRA_CFLAGS += -DCONFIG_PLATFORM_OPS
-+ifeq ($(CONFIG_USB_HCI), y)
-+EXTRA_CFLAGS += -DCONFIG_USE_USB_BUFFER_ALLOC_TX
-+_PLATFORM_FILES += platform/platform_ARM_SUNxI_usb.o
-+endif
-+ifeq ($(CONFIG_SDIO_HCI), y)
-+# default setting for A31-EVB mmc0
-+EXTRA_CFLAGS += -DCONFIG_A31_EVB
-+_PLATFORM_FILES += platform/platform_ARM_SUNnI_sdio.o
-+endif
-+
-+ARCH := arm
-+#Android-JB42
-+#CROSS_COMPILE := /home/android_sdk/Allwinner/a31/android-jb42/lichee/buildroot/output/external-toolchain/bin/arm-linux-gnueabi-
-+#KSRC :=/home/android_sdk/Allwinner/a31/android-jb42/lichee/linux-3.3
-+#ifeq ($(CONFIG_USB_HCI), y)
-+#MODULE_NAME := 8188eu_sw
-+#endif
-+# ==== Cross compile setting for kitkat-a3x_v4.5 =====
-+CROSS_COMPILE := /home/android_sdk/Allwinner/a31/kitkat-a3x_v4.5/lichee/buildroot/output/external-toolchain/bin/arm-linux-gnueabi-
-+KSRC :=/home/android_sdk/Allwinner/a31/kitkat-a3x_v4.5/lichee/linux-3.3
-+endif
-+
-+ifeq ($(CONFIG_PLATFORM_ARM_SUN7I), y)
-+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
-+EXTRA_CFLAGS += -DCONFIG_PLATFORM_ARM_SUN7I
-+EXTRA_CFLAGS += -DCONFIG_TRAFFIC_PROTECT
-+# default setting for Android 4.1, 4.2, 4.3, 4.4
-+EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
-+EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
-+EXTRA_CFLAGS += -DCONFIG_QOS_OPTIMIZATION
-+
-+EXTRA_CFLAGS += -DCONFIG_PLATFORM_OPS
-+ifeq ($(CONFIG_USB_HCI), y)
-+EXTRA_CFLAGS += -DCONFIG_USE_USB_BUFFER_ALLOC_TX
-+_PLATFORM_FILES += platform/platform_ARM_SUNxI_usb.o
-+endif
-+ifeq ($(CONFIG_SDIO_HCI), y)
-+_PLATFORM_FILES += platform/platform_ARM_SUNnI_sdio.o
-+endif
-+
-+ARCH := arm
-+# ===Cross compile setting for Android 4.2 SDK ===
-+#CROSS_COMPILE := /home/android_sdk/Allwinner/a20_evb/lichee/out/android/common/buildroot/external-toolchain/bin/arm-linux-gnueabi-
-+#KSRC := /home/android_sdk/Allwinner/a20_evb/lichee/linux-3.3
-+# ==== Cross compile setting for Android 4.3 SDK =====
-+#CROSS_COMPILE := /home/android_sdk/Allwinner/a20/android-jb43/lichee/out/android/common/buildroot/external-toolchain/bin/arm-linux-gnueabi-
-+#KSRC := /home/android_sdk/Allwinner/a20/android-jb43/lichee/linux-3.4
-+# ==== Cross compile setting for kitkat-a20_v4.4 =====
-+CROSS_COMPILE := /home/android_sdk/Allwinner/a20/kitkat-a20_v4.4/lichee/out/android/common/buildroot/external-toolchain/bin/arm-linux-gnueabi-
-+KSRC := /home/android_sdk/Allwinner/a20/kitkat-a20_v4.4/lichee/linux-3.4
-+endif
-+
-+ifeq ($(CONFIG_PLATFORM_ARM_SUN8I_W3P1), y)
-+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
-+EXTRA_CFLAGS += -DCONFIG_PLATFORM_ARM_SUN8I
-+EXTRA_CFLAGS += -DCONFIG_PLATFORM_ARM_SUN8I_W3P1
-+EXTRA_CFLAGS += -DCONFIG_TRAFFIC_PROTECT
-+# default setting for Android 4.1, 4.2
-+EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
-+EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
-+
-+EXTRA_CFLAGS += -DCONFIG_PLATFORM_OPS
-+ifeq ($(CONFIG_USB_HCI), y)
-+EXTRA_CFLAGS += -DCONFIG_USE_USB_BUFFER_ALLOC_TX
-+_PLATFORM_FILES += platform/platform_ARM_SUNxI_usb.o
-+endif
-+ifeq ($(CONFIG_SDIO_HCI), y)
-+_PLATFORM_FILES += platform/platform_ARM_SUNnI_sdio.o
-+endif
-+
-+ARCH := arm
-+# ===Cross compile setting for Android 4.2 SDK ===
-+#CROSS_COMPILE := /home/android_sdk/Allwinner/a23/android-jb42/lichee/out/android/common/buildroot/external-toolchain/bin/arm-linux-gnueabi-
-+#KSRC :=/home/android_sdk/Allwinner/a23/android-jb42/lichee/linux-3.4
-+# ===Cross compile setting for Android 4.4 SDK ===
-+CROSS_COMPILE := /home/android_sdk/Allwinner/a23/android-kk44/lichee/out/android/common/buildroot/external-toolchain/bin/arm-linux-gnueabi-
-+KSRC :=/home/android_sdk/Allwinner/a23/android-kk44/lichee/linux-3.4
-+endif
-+
-+ifeq ($(CONFIG_PLATFORM_ARM_SUN8I_W5P1), y)
-+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
-+EXTRA_CFLAGS += -DCONFIG_PLATFORM_ARM_SUN8I
-+EXTRA_CFLAGS += -DCONFIG_PLATFORM_ARM_SUN8I_W5P1
-+EXTRA_CFLAGS += -DCONFIG_TRAFFIC_PROTECT
-+# default setting for Android 4.1, 4.2
-+EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
-+EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
-+
-+# Enable this for Android 5.0
-+EXTRA_CFLAGS += -DCONFIG_RADIO_WORK
-+
-+EXTRA_CFLAGS += -DCONFIG_PLATFORM_OPS
-+ifeq ($(CONFIG_USB_HCI), y)
-+EXTRA_CFLAGS += -DCONFIG_USE_USB_BUFFER_ALLOC_TX
-+_PLATFORM_FILES += platform/platform_ARM_SUNxI_usb.o
-+endif
-+ifeq ($(CONFIG_SDIO_HCI), y)
-+_PLATFORM_FILES += platform/platform_ARM_SUNnI_sdio.o
-+endif
-+
-+ARCH := arm
-+# ===Cross compile setting for Android L SDK ===
-+CROSS_COMPILE := /home/android_sdk/Allwinner/a33/android-L/lichee/out/sun8iw5p1/android/common/buildroot/external-toolchain/bin/arm-linux-gnueabi-
-+KSRC :=/home/android_sdk/Allwinner/a33/android-L/lichee/linux-3.4
-+endif
-+
-+ifeq ($(CONFIG_PLATFORM_ACTIONS_ATV5201), y)
-+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_PLATFORM_ACTIONS_ATV5201
-+EXTRA_CFLAGS += -DCONFIG_SDIO_DISABLE_RXFIFO_POLLING_LOOP
-+ARCH := mips
-+CROSS_COMPILE := mipsel-linux-gnu-
-+KVER := $(KERNEL_VER)
-+KSRC:= $(CFGDIR)/../../kernel/linux-$(KERNEL_VER)
-+endif
-+
-+ifeq ($(CONFIG_PLATFORM_ARM_RTD299X), y)
-+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
-+EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
-+EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
-+ifeq ($(CONFIG_ANDROID), y)
-+# Enable this for Android 5.0
-+EXTRA_CFLAGS += -DCONFIG_RADIO_WORK
-+endif
-+#ARCH, CROSS_COMPILE, KSRC,and MODDESTDIR are provided by external makefile
-+INSTALL_PREFIX :=
-+endif
-+
-+ifeq ($(CONFIG_PLATFORM_ARM_RTD299X_LG), y)
-+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
-+EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
-+EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
-+EXTRA_CFLAGS += -DRTW_P2P_GROUP_INTERFACE=1
-+EXTRA_CFLAGS += -DCONFIG_IFACE_NUMBER=3
-+#EXTRA_CFLAGS += -DCONFIG_FIX_HWPORT
-+EXTRA_CFLAGS += -DLGE_PRIVATE
-+EXTRA_CFLAGS += -DPURE_SUPPLICANT
-+EXTRA_CFLAGS += -DCONFIG_CUSTOMIZED_COUNTRY_CHPLAN_MAP -DCONFIG_RTW_IOCTL_SET_COUNTRY
-+EXTRA_CFLAGS += -DDBG_RX_DFRAME_RAW_DATA
-+EXTRA_CFLAGS += -DRTW_REDUCE_SCAN_SWITCH_CH_TIME
-+ARCH ?= arm
-+KVER ?=
-+
-+ifneq ($(PLATFORM), WEBOS)
-+$(info PLATFORM is empty)
-+CROSS_COMPILE ?= /mnt/newdisk/LGE/arm-lg115x-linux-gnueabi-4.8-2016.03-x86_64/bin/arm-lg115x-linux-gnueabi-
-+KSRC ?= /mnt/newdisk/LGE/linux-rockhopper_k3lp_drd4tv_423
-+endif
-+
-+CROSS_COMPILE ?=
-+KSRC ?= $(LINUX_SRC)
-+INSTALL_PREFIX ?=
-+endif
-+
-+ifeq ($(CONFIG_PLATFORM_HISILICON), y)
-+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_PLATFORM_HISILICON
-+ifeq ($(SUPPORT_CONCURRENT),y)
-+EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
-+endif
-+EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
-+ARCH := arm
-+ifeq ($(CROSS_COMPILE),)
-+ CROSS_COMPILE = arm-hisiv200-linux-
-+endif
-+MODULE_NAME := rtl8192eu
-+ifeq ($(KSRC),)
-+ KSRC := ../../../../../../kernel/linux-3.4.y
-+endif
-+endif
-+
-+ifeq ($(CONFIG_PLATFORM_HISILICON_HI3798), y)
-+EXTRA_CFLAGS += -DCONFIG_PLATFORM_HISILICON
-+EXTRA_CFLAGS += -DCONFIG_PLATFORM_HISILICON_HI3798
-+#EXTRA_CFLAGS += -DCONFIG_PLATFORM_HISILICON_HI3798_MV200_HDMI_DONGLE
-+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
-+# default setting for Android
-+EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
-+EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211
-+EXTRA_CFLAGS += -DRTW_USE_CFG80211_STA_EVENT
-+# default setting for Android 5.x and later
-+#EXTRA_CFLAGS += -DCONFIG_RADIO_WORK
-+
-+# If system could power on and recognize Wi-Fi SDIO automatically,
-+# platfrom operations are not necessary.
-+#ifeq ($(CONFIG_SDIO_HCI), y)
-+#EXTRA_CFLAGS += -DCONFIG_PLATFORM_OPS
-+#_PLATFORM_FILES += platform/platform_hisilicon_hi3798_sdio.o
-+#EXTRA_CFLAGS += -DCONFIG_HISI_SDIO_ID=1
-+#endif
-+
-+ARCH ?= arm
-+CROSS_COMPILE ?= /HiSTBAndroidV600R003C00SPC021_git_0512/device/hisilicon/bigfish/sdk/tools/linux/toolchains/arm-histbv310-linux/bin/arm-histbv310-linux-
-+ifndef KSRC
-+KSRC := /HiSTBAndroidV600R003C00SPC021_git_0512/device/hisilicon/bigfish/sdk/source/kernel/linux-3.18.y
-+KSRC += O=/HiSTBAndroidV600R003C00SPC021_git_0512/out/target/product/Hi3798MV200/obj/KERNEL_OBJ
-+endif
-+
-+ifeq ($(CONFIG_RTL8822B), y)
-+ifeq ($(CONFIG_SDIO_HCI), y)
-+CONFIG_RTL8822BS ?= m
-+USER_MODULE_NAME := rtl8822bs
-+endif
-+endif
-+
-+endif
-+
-+# Platform setting
-+ifeq ($(CONFIG_PLATFORM_ARM_SPREADTRUM_6820), y)
-+ifeq ($(CONFIG_ANDROID_2X), y)
-+EXTRA_CFLAGS += -DANDROID_2X
-+endif
-+EXTRA_CFLAGS += -DCONFIG_PLATFORM_SPRD
-+EXTRA_CFLAGS += -DPLATFORM_SPREADTRUM_6820
-+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
-+ifeq ($(RTL871X), rtl8188e)
-+EXTRA_CFLAGS += -DSOFTAP_PS_DURATION=50
-+endif
-+ifeq ($(CONFIG_SDIO_HCI), y)
-+EXTRA_CFLAGS += -DCONFIG_PLATFORM_OPS
-+_PLATFORM_FILES += platform/platform_sprd_sdio.o
-+endif
-+endif
-+
-+ifeq ($(CONFIG_PLATFORM_ARM_SPREADTRUM_8810), y)
-+ifeq ($(CONFIG_ANDROID_2X), y)
-+EXTRA_CFLAGS += -DANDROID_2X
-+endif
-+EXTRA_CFLAGS += -DCONFIG_PLATFORM_SPRD
-+EXTRA_CFLAGS += -DPLATFORM_SPREADTRUM_8810
-+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
-+ifeq ($(RTL871X), rtl8188e)
-+EXTRA_CFLAGS += -DSOFTAP_PS_DURATION=50
-+endif
-+ifeq ($(CONFIG_SDIO_HCI), y)
-+EXTRA_CFLAGS += -DCONFIG_PLATFORM_OPS
-+_PLATFORM_FILES += platform/platform_sprd_sdio.o
-+endif
-+endif
-+
-+ifeq ($(CONFIG_PLATFORM_ARM_WMT), y)
-+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
-+EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
-+EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
-+EXTRA_CFLAGS += -DCONFIG_PLATFORM_OPS
-+ifeq ($(CONFIG_SDIO_HCI), y)
-+_PLATFORM_FILES += platform/platform_ARM_WMT_sdio.o
-+endif
-+ARCH := arm
-+CROSS_COMPILE := /home/android_sdk/WonderMedia/wm8880-android4.4/toolchain/arm_201103_gcc4.5.2/mybin/arm_1103_le-
-+KSRC := /home/android_sdk/WonderMedia/wm8880-android4.4/kernel4.4/
-+MODULE_NAME :=8189es_kk
-+endif
-+
-+ifeq ($(CONFIG_PLATFORM_RTK119X), y)
-+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
-+#EXTRA_CFLAGS += -DCONFIG_PLATFORM_ARM_SUN7I
-+EXTRA_CFLAGS += -DCONFIG_TRAFFIC_PROTECT
-+# default setting for Android 4.1, 4.2
-+EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
-+EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
-+#EXTRA_CFLAGS += -DCONFIG_QOS_OPTIMIZATION
-+EXTRA_CFLAGS += -DCONFIG_QOS_OPTIMIZATION
-+
-+#EXTRA_CFLAGS += -DCONFIG_#PLATFORM_OPS
-+ifeq ($(CONFIG_USB_HCI), y)
-+EXTRA_CFLAGS += -DCONFIG_USE_USB_BUFFER_ALLOC_TX
-+#_PLATFORM_FILES += platform/platform_ARM_SUNxI_usb.o
-+endif
-+ifeq ($(CONFIG_SDIO_HCI), y)
-+_PLATFORM_FILES += platform/platform_ARM_SUNnI_sdio.o
-+endif
-+
-+ARCH := arm
-+
-+# ==== Cross compile setting for Android 4.4 SDK =====
-+#CROSS_COMPILE := arm-linux-gnueabihf-
-+KVER := 3.10.24
-+#KSRC :=/home/android_sdk/Allwinner/a20/android-kitkat44/lichee/linux-3.4
-+CROSS_COMPILE := /home/realtek/software_phoenix/phoenix/toolchain/usr/local/arm-2013.11/bin/arm-linux-gnueabihf-
-+KSRC := /home/realtek/software_phoenix/linux-kernel
-+MODULE_NAME := 8192eu
-+
-+endif
-+
-+ifeq ($(CONFIG_PLATFORM_RTK119X_AM), y)
-+EXTRA_CFLAGS += -DCONFIG_PLATFORM_RTK119X_AM
-+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
-+EXTRA_CFLAGS += -DCONFIG_TRAFFIC_PROTECT
-+EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE -DCONFIG_FULL_CH_IN_P2P_HANDSHAKE
-+EXTRA_CFLAGS += -DCONFIG_IFACE_NUMBER=3
-+EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
-+
-+ifeq ($(CONFIG_USB_HCI), y)
-+EXTRA_CFLAGS += -DCONFIG_USE_USB_BUFFER_ALLOC_TX
-+endif
-+
-+ARCH := arm
-+
-+#CROSS_COMPILE := arm-linux-gnueabihf-
-+KVER := 3.10.24
-+#KSRC :=
-+CROSS_COMPILE :=
-+endif
-+
-+ifeq ($(CONFIG_PLATFORM_RTK129X), y)
-+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
-+EXTRA_CFLAGS += -DRTK_129X_PLATFORM
-+EXTRA_CFLAGS += -DCONFIG_TRAFFIC_PROTECT
-+# default setting for Android 4.1, 4.2
-+EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
-+EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
-+#EXTRA_CFLAGS += -DCONFIG_P2P_IPS -DCONFIG_QOS_OPTIMIZATION
-+EXTRA_CFLAGS += -DCONFIG_QOS_OPTIMIZATION
-+# Enable this for Android 5.0
-+EXTRA_CFLAGS += -DCONFIG_RADIO_WORK
-+ifeq ($(CONFIG_RTL8821C)$(CONFIG_SDIO_HCI),yy)
-+EXTRA_CFLAGS += -DCONFIG_WAKEUP_GPIO_INPUT_MODE
-+EXTRA_CFLAGS += -DCONFIG_BT_WAKE_HST_OPEN_DRAIN
-+endif
-+EXTRA_CFLAGS += -Wno-error=date-time
-+# default setting for Android 7.0
-+ifeq ($(RTK_ANDROID_VERSION), nougat)
-+EXTRA_CFLAGS += -DRTW_P2P_GROUP_INTERFACE=1
-+endif
-+#EXTRA_CFLAGS += -DCONFIG_#PLATFORM_OPS
-+ifeq ($(CONFIG_USB_HCI), y)
-+EXTRA_CFLAGS += -DCONFIG_USE_USB_BUFFER_ALLOC_TX
-+endif
-+
-+ARCH := arm64
-+
-+# ==== Cross compile setting for Android 4.4 SDK =====
-+#CROSS_COMPILE := arm-linux-gnueabihf-
-+#KVER := 4.1.10
-+#CROSS_COMPILE := $(CROSS)
-+#KSRC := $(LINUX_KERNEL_PATH)
-+CROSS_COMPILE := /home/android_sdk/DHC/trunk-6.0.0_r1-QA160627/phoenix/toolchain/asdk64-4.9.4-a53-EL-3.10-g2.19-a64nt-160307/bin/asdk64-linux-
-+KSRC := /home/android_sdk/DHC/trunk-6.0.0_r1-QA160627/linux-kernel
-+endif
-+
-+ifeq ($(CONFIG_PLATFORM_RTK390X), y)
-+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
-+EXTRA_CFLAGS += -DCONFIG_PLATFORM_RTK390X
-+EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
-+EXTRA_CFLAGS += -DCONFIG_RTW_NETIF_SG
-+ifeq ($(CONFIG_USB_HCI), y)
-+EXTRA_CFLAGS += -DCONFIG_USE_USB_BUFFER_ALLOC_TX
-+endif
-+
-+ARCH:=rlx
-+
-+CROSS_COMPILE:=mips-linux-
-+KSRC:= /home/realtek/share/Develop/IPCAM_SDK/RealSil/rts3901_sdk_v1.2_vanilla/linux-3.10
-+
-+endif
-+
-+ifeq ($(CONFIG_PLATFORM_NOVATEK_NT72668), y)
-+EXTRA_CFLAGS += -DCONFIG_PLATFORM_NOVATEK_NT72668
-+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
-+EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
-+EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
-+EXTRA_CFLAGS += -DCONFIG_USE_USB_BUFFER_ALLOC_RX
-+EXTRA_CFLAGS += -DCONFIG_USE_USB_BUFFER_ALLOC_TX
-+ARCH ?= arm
-+CROSS_COMPILE := arm-linux-gnueabihf-
-+KVER := 3.8.0
-+KSRC := /Custom/Novatek/TCL/linux-3.8_header
-+#KSRC := $(KERNELDIR)
-+endif
-+
-+ifeq ($(CONFIG_PLATFORM_ARM_TCC8930_JB42), y)
-+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
-+# default setting for Android 4.1, 4.2
-+EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
-+EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
-+ARCH := arm
-+CROSS_COMPILE := /home/android_sdk/Telechips/v13.05_r1-tcc-android-4.2.2_tcc893x-evm_build/prebuilts/gcc/linux-x86/arm/arm-eabi-4.6/bin/arm-eabi-
-+KSRC := /home/android_sdk/Telechips/v13.05_r1-tcc-android-4.2.2_tcc893x-evm_build/kernel
-+MODULE_NAME := wlan
-+endif
-+
-+ifeq ($(CONFIG_PLATFORM_RTL8197D), y)
-+EXTRA_CFLAGS += -DCONFIG_BIG_ENDIAN -DCONFIG_PLATFORM_RTL8197D
-+export DIR_LINUX=$(shell pwd)/../SDK/rlxlinux-sdk321-v50/linux-2.6.30
-+ARCH ?= rlx
-+CROSS_COMPILE:= $(DIR_LINUX)/../toolchain/rsdk-1.5.5-5281-EB-2.6.30-0.9.30.3-110714/bin/rsdk-linux-
-+KSRC := $(DIR_LINUX)
-+endif
-+
-+ifeq ($(CONFIG_PLATFORM_AML_S905), y)
-+EXTRA_CFLAGS += -DCONFIG_PLATFORM_AML_S905
-+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -fno-pic
-+# default setting for Android
-+EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
-+EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211
-+EXTRA_CFLAGS += -DRTW_USE_CFG80211_STA_EVENT
-+# default setting for Android 5.x and later
-+EXTRA_CFLAGS += -DCONFIG_RADIO_WORK
-+
-+ifeq ($(CONFIG_SDIO_HCI), y)
-+EXTRA_CFLAGS += -DCONFIG_PLATFORM_OPS
-+_PLATFORM_FILES += platform/platform_aml_s905_sdio.o
-+endif
-+
-+ARCH ?= arm64
-+CROSS_COMPILE ?= /4.4_S905L_8822bs_compile/gcc-linaro-aarch64-linux-gnu-4.9-2014.09_linux/bin/aarch64-linux-gnu-
-+ifndef KSRC
-+KSRC := /4.4_S905L_8822bs_compile/common
-+# To locate output files in a separate directory.
-+KSRC += O=/4.4_S905L_8822bs_compile/KERNEL_OBJ
-+endif
-+
-+ifeq ($(CONFIG_RTL8822B), y)
-+ifeq ($(CONFIG_SDIO_HCI), y)
-+CONFIG_RTL8822BS ?= m
-+USER_MODULE_NAME := 8822bs
-+endif
-+endif
-+
-+endif
-+
-+ifeq ($(CONFIG_PLATFORM_ZTE_ZX296716), y)
-+EXTRA_CFLAGS += -Wno-error=date-time
-+EXTRA_CFLAGS += -DCONFIG_PLATFORM_ZTE_ZX296716
-+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
-+# default setting for Android
-+EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
-+EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211
-+EXTRA_CFLAGS += -DRTW_USE_CFG80211_STA_EVENT
-+# default setting for Android 5.x and later
-+#EXTRA_CFLAGS += -DCONFIG_RADIO_WORK
-+
-+ifeq ($(CONFIG_SDIO_HCI), y)
-+# mark this temporarily
-+#EXTRA_CFLAGS += -DCONFIG_PLATFORM_OPS
-+#_PLATFORM_FILES += platform/platform_zte_zx296716_sdio.o
-+endif
-+
-+ARCH ?= arm64
-+CROSS_COMPILE ?=
-+KSRC ?=
-+
-+ifeq ($(CONFIG_RTL8822B), y)
-+ifeq ($(CONFIG_SDIO_HCI), y)
-+CONFIG_RTL8822BS ?= m
-+USER_MODULE_NAME := 8822bs
-+endif
-+endif
-+
-+endif
-+
-+########### CUSTOMER ################################
-+ifeq ($(CONFIG_CUSTOMER_HUAWEI_GENERAL), y)
-+CONFIG_CUSTOMER_HUAWEI = y
-+endif
-+
-+ifeq ($(CONFIG_CUSTOMER_HUAWEI), y)
-+EXTRA_CFLAGS += -DCONFIG_HUAWEI_PROC
-+endif
-+
-+ifeq ($(CONFIG_MULTIDRV), y)
-+
-+ifeq ($(CONFIG_SDIO_HCI), y)
-+MODULE_NAME := rtw_sdio
-+endif
-+
-+ifeq ($(CONFIG_USB_HCI), y)
-+MODULE_NAME := rtw_usb
-+endif
-+
-+ifeq ($(CONFIG_PCI_HCI), y)
-+MODULE_NAME := rtw_pci
-+endif
-+
-+endif
-+
-+USER_MODULE_NAME ?=
-+ifneq ($(USER_MODULE_NAME),)
-+MODULE_NAME := $(USER_MODULE_NAME)
-+endif
-+
-+ifneq ($(KERNELRELEASE),)
-+
-+########### this part for *.mk ############################
-+include $(src)/hal/phydm/phydm.mk
-+
-+########### HAL_RTL8822B #################################
-+ifeq ($(CONFIG_RTL8822B), y)
-+include $(src)/rtl8822b.mk
-+endif
-+
-+########### HAL_RTL8821C #################################
-+ifeq ($(CONFIG_RTL8821C), y)
-+include $(src)/rtl8821c.mk
-+endif
-+
-+rtk_core := core/rtw_cmd.o \
-+ core/rtw_security.o \
-+ core/rtw_debug.o \
-+ core/rtw_io.o \
-+ core/rtw_ioctl_query.o \
-+ core/rtw_ioctl_set.o \
-+ core/rtw_ieee80211.o \
-+ core/rtw_mlme.o \
-+ core/rtw_mlme_ext.o \
-+ core/rtw_mi.o \
-+ core/rtw_wlan_util.o \
-+ core/rtw_vht.o \
-+ core/rtw_pwrctrl.o \
-+ core/rtw_rf.o \
-+ core/rtw_chplan.o \
-+ core/rtw_recv.o \
-+ core/rtw_sta_mgt.o \
-+ core/rtw_ap.o \
-+ core/mesh/rtw_mesh.o \
-+ core/mesh/rtw_mesh_pathtbl.o \
-+ core/mesh/rtw_mesh_hwmp.o \
-+ core/rtw_xmit.o \
-+ core/rtw_p2p.o \
-+ core/rtw_rson.o \
-+ core/rtw_tdls.o \
-+ core/rtw_br_ext.o \
-+ core/rtw_iol.o \
-+ core/rtw_sreset.o \
-+ core/rtw_btcoex_wifionly.o \
-+ core/rtw_btcoex.o \
-+ core/rtw_beamforming.o \
-+ core/rtw_odm.o \
-+ core/rtw_rm.o \
-+ core/rtw_rm_fsm.o \
-+ core/efuse/rtw_efuse.o
-+
-+ifeq ($(CONFIG_SDIO_HCI), y)
-+rtk_core += core/rtw_sdio.o
-+endif
-+
-+$(MODULE_NAME)-y += $(rtk_core)
-+
-+$(MODULE_NAME)-$(CONFIG_INTEL_WIDI) += core/rtw_intel_widi.o
-+
-+$(MODULE_NAME)-$(CONFIG_WAPI_SUPPORT) += core/rtw_wapi.o \
-+ core/rtw_wapi_sms4.o
-+
-+$(MODULE_NAME)-y += $(_OS_INTFS_FILES)
-+$(MODULE_NAME)-y += $(_HAL_INTFS_FILES)
-+$(MODULE_NAME)-y += $(_PHYDM_FILES)
-+$(MODULE_NAME)-y += $(_BTC_FILES)
-+$(MODULE_NAME)-y += $(_PLATFORM_FILES)
-+
-+$(MODULE_NAME)-$(CONFIG_MP_INCLUDED) += core/rtw_mp.o
-+
-+obj-$(CONFIG_88XXAU) := $(MODULE_NAME).o
-+
-+else
-+
-+export CONFIG_88XXAU = m
-+
-+all: modules
-+
-+modules:
-+ $(MAKE) ARCH=$(ARCH) CROSS_COMPILE=$(CROSS_COMPILE) -C $(KSRC) M=$(shell pwd) modules
-+ @echo "---------------------------------------------------------------------------"
-+ @echo "Visit https://github.com/aircrack-ng/rtl8812au for support/reporting issues"
-+ @echo "or check for newer versions (branches) of these drivers. "
-+ @echo "---------------------------------------------------------------------------"
-+strip:
-+ $(CROSS_COMPILE)strip $(MODULE_NAME).ko --strip-unneeded
-+
-+install:
-+ install -p -m 644 $(MODULE_NAME).ko $(MODDESTDIR)
-+ /sbin/depmod -a ${KVER}
-+
-+uninstall:
-+ rm -f $(MODDESTDIR)/$(MODULE_NAME).ko
-+ /sbin/depmod -a ${KVER}
-+
-+backup_rtlwifi:
-+ @echo "Making backup rtlwifi drivers"
-+ifneq (,$(wildcard $(STAGINGMODDIR)/rtl*))
-+ @tar cPf $(wildcard $(STAGINGMODDIR))/backup_rtlwifi_driver.tar $(wildcard $(STAGINGMODDIR)/rtl*)
-+ @rm -rf $(wildcard $(STAGINGMODDIR)/rtl*)
-+endif
-+ifneq (,$(wildcard $(MODDESTDIR)realtek))
-+ @tar cPf $(MODDESTDIR)backup_rtlwifi_driver.tar $(MODDESTDIR)realtek
-+ @rm -fr $(MODDESTDIR)realtek
-+endif
-+ifneq (,$(wildcard $(MODDESTDIR)rtl*))
-+ @tar cPf $(MODDESTDIR)../backup_rtlwifi_driver.tar $(wildcard $(MODDESTDIR)rtl*)
-+ @rm -fr $(wildcard $(MODDESTDIR)rtl*)
-+endif
-+ @/sbin/depmod -a ${KVER}
-+ @echo "Please reboot your system"
-+
-+restore_rtlwifi:
-+ @echo "Restoring backups"
-+ifneq (,$(wildcard $(STAGINGMODDIR)/backup_rtlwifi_driver.tar))
-+ @tar xPf $(STAGINGMODDIR)/backup_rtlwifi_driver.tar
-+ @rm $(STAGINGMODDIR)/backup_rtlwifi_driver.tar
-+endif
-+ifneq (,$(wildcard $(MODDESTDIR)backup_rtlwifi_driver.tar))
-+ @tar xPf $(MODDESTDIR)backup_rtlwifi_driver.tar
-+ @rm $(MODDESTDIR)backup_rtlwifi_driver.tar
-+endif
-+ifneq (,$(wildcard $(MODDESTDIR)../backup_rtlwifi_driver.tar))
-+ @tar xPf $(MODDESTDIR)../backup_rtlwifi_driver.tar
-+ @rm $(MODDESTDIR)../backup_rtlwifi_driver.tar
-+endif
-+ @/sbin/depmod -a ${KVER}
-+ @echo "Please reboot your system"
-+
-+config_r:
-+ @echo "make config"
-+ /bin/bash script/Configure script/config.in
-+
-+.PHONY: modules clean
-+
-+clean:
-+ #$(MAKE) -C $(KSRC) M=$(shell pwd) clean
-+ cd hal ; rm -fr */*/*/*.mod.c */*/*/*.mod */*/*/*.o */*/*/.*.cmd */*/*/*.ko
-+ cd hal ; rm -fr */*/*.mod.c */*/*.mod */*/*.o */*/.*.cmd */*/*.ko
-+ cd hal ; rm -fr */*.mod.c */*.mod */*.o */.*.cmd */*.ko
-+ cd hal ; rm -fr *.mod.c *.mod *.o .*.cmd *.ko
-+ cd core ; rm -fr */*.mod.c */*.mod */*.o */.*.cmd */*.ko
-+ cd core ; rm -fr *.mod.c *.mod *.o .*.cmd *.ko
-+ cd os_dep/linux ; rm -fr *.mod.c *.mod *.o .*.cmd *.ko *.o.d
-+ cd os_dep ; rm -fr *.mod.c *.mod *.o .*.cmd *.ko
-+ cd platform ; rm -fr *.mod.c *.mod *.o .*.cmd *.ko
-+ rm -fr Module.symvers ; rm -fr Module.markers ; rm -fr modules.order
-+ rm -fr *.mod.c *.mod *.o .*.cmd *.ko *~
-+ rm -fr .tmp_versions
-+endif
-diff --git linux-5.8/3rdparty/rtl8812au/README.md linux-5.8/3rdparty/rtl8812au/README.md
-new file mode 100644
-index 000000000..1739873c3
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/README.md
-@@ -0,0 +1,207 @@
-+## RTL8812AU/21AU and RTL8814AU drivers
-+Only for use with Linux & Android
-+
-+[](#)
-+[](#)
-+[](#)
-+[](https://github.com/aircrack-ng/rtl8812au/issues)
-+[](https://github.com/aircrack-ng/rtl8812au/network)
-+[](https://github.com/aircrack-ng/rtl8812au/stargazers)
-+[](https://travis-ci.org/aircrack-ng/rtl8812au)
-+[](https://github.com/aircrack-ng/rtl8812au/blob/master/LICENSE)
-+
-+[](https://www.kali.org)
-+[](https://www.archlinux.org)
-+[](https://www.armbian.com)
-+[](https://img.shields.io/badge/ArchLinux-supported-blue.svg)
-+[](https://github.com/aircrack-ng/aircrack-ng)
-+[](https://github.com/kimocoder/wifite2)
-+
-+
-+### Important!
-+```
-+* Use "ip" and "iw" instead of "ifconfig" and "iwconfig"
-+ It's described further down, READ THE README!
-+
-+* v5.3.4 is the stable branch, not this, but this does have
-+ better range then branches below + more fixes from Realtek
-+```
-+
-+### IPERF3 benchmark
-+[Device] Alfa Networks AWUS036ACH
-+[Chipset] 88XXau (rtl8812au)
-+[Branch] v5.6.4.1
-+[Distance] 10m free sight
-+```
-+[ ID] Interval Transfer Bitrate Retr Cwnd
-+[ 5] 0.00-1.00 sec 11.6 MBytes 97.4 Mbits/sec 0 96.2 KBytes
-+[ 5] 1.00-2.00 sec 11.2 MBytes 93.8 Mbits/sec 0 100 KBytes
-+[ 5] 2.00-3.00 sec 11.2 MBytes 93.8 Mbits/sec 0 100 KBytes
-+[ 5] 3.00-4.00 sec 11.2 MBytes 93.8 Mbits/sec 0 100 KBytes
-+[ 5] 4.00-5.00 sec 11.2 MBytes 93.8 Mbits/sec 0 100 KBytes
-+[ 5] 5.00-6.00 sec 11.4 MBytes 95.9 Mbits/sec 0 105 KBytes
-+[ 5] 6.00-7.00 sec 11.2 MBytes 93.8 Mbits/sec 0 105 KBytes
-+[ 5] 7.00-8.00 sec 11.3 MBytes 94.9 Mbits/sec 0 157 KBytes
-+[ 5] 8.00-9.00 sec 11.2 MBytes 93.8 Mbits/sec 0 157 KBytes
-+[ 5] 9.00-10.00 sec 11.2 MBytes 94.3 Mbits/sec 0 157 KBytes
-+[ 5] 10.00-11.00 sec 11.2 MBytes 93.8 Mbits/sec 0 157 KBytes
-+[ 5] 11.00-12.00 sec 11.2 MBytes 93.8 Mbits/sec 0 157 KBytes
-+[ 5] 12.00-13.00 sec 11.2 MBytes 94.4 Mbits/sec 0 157 KBytes
-+[ 5] 13.00-14.00 sec 11.2 MBytes 93.8 Mbits/sec 0 157 KBytes
-+[ 5] 14.00-15.00 sec 11.2 MBytes 94.4 Mbits/sec 0 157 KBytes
-+[ 5] 15.00-16.00 sec 10.9 MBytes 91.7 Mbits/sec 0 157 KBytes
-+[ 5] 16.00-17.00 sec 11.2 MBytes 94.4 Mbits/sec 0 157 KBytes
-+[ 5] 17.00-18.00 sec 11.2 MBytes 94.4 Mbits/sec 0 157 KBytes
-+[ 5] 18.00-19.00 sec 11.2 MBytes 94.4 Mbits/sec 0 157 KBytes
-+[ 5] 19.00-20.00 sec 11.2 MBytes 93.8 Mbits/sec 0 157 KBytes
-+[ 5] 20.00-21.00 sec 11.2 MBytes 93.8 Mbits/sec 0 157 KBytes
-+[ 5] 21.00-22.00 sec 11.2 MBytes 93.8 Mbits/sec 0 157 KBytes
-+[ 5] 22.00-23.00 sec 11.2 MBytes 93.8 Mbits/sec 0 157 KBytes
-+- - - - - - - - - - - - - - - - - - - - - - - - -
-+[ ID] Interval Transfer Bitrate Retr
-+[ 5] 0.00-23.15 sec 260 MBytes 94.2 Mbits/sec 0 sender
-+[ 5] 0.00-23.15 sec 0.00 Bytes 0.00 bits/sec receiver
-+```
-+
-+### DKMS
-+This driver can be installed using [DKMS]. This is a system which will automatically recompile and install a kernel module when a new kernel gets installed or updated. To make use of DKMS, install the `dkms` package, which on Debian (based) systems is done like this:
-+```
-+$ sudo apt-get install dkms
-+```
-+
-+### Installation of Driver
-+In order to install the driver open a terminal in the directory with the source code and execute the following command:
-+```
-+$ sudo ./dkms-install.sh
-+```
-+
-+### Removal of Driver
-+In order to remove the driver from your system open a terminal in the directory with the source code and execute the following command:
-+```
-+$ sudo ./dkms-remove.sh
-+```
-+
-+### Make
-+For building & installing the driver with 'make' use
-+```
-+$ make && make install
-+```
-+
-+### Notes
-+Download
-+```
-+$ git clone -b v5.6.4.2 https://github.com/aircrack-ng/rtl8812au.git
-+cd rtl*
-+```
-+Package / Build dependencies (Kali)
-+```
-+$ sudo apt-get update
-+$ sudo apt-get install build-essential libelf-dev linux-headers-`uname -r`
-+```
-+#### For Raspberry (RPI)
-+
-+```
-+$ sudo apt-get install raspberrypi-kernel-headers
-+```
-+
-+Then run this step to change platform in Makefile, For RPI 1/2/3/ & 0/Zero:
-+```
-+$ sed -i 's/CONFIG_PLATFORM_I386_PC = y/CONFIG_PLATFORM_I386_PC = n/g' Makefile
-+$ sed -i 's/CONFIG_PLATFORM_ARM_RPI = n/CONFIG_PLATFORM_ARM_RPI = y/g' Makefile
-+```
-+
-+But for RPI 3B+ & 4B you will need to run those below which builds the ARM64 arch driver:
-+```
-+$ sed -i 's/CONFIG_PLATFORM_I386_PC = y/CONFIG_PLATFORM_I386_PC = n/g' Makefile
-+$ sed -i 's/CONFIG_PLATFORM_ARM64_RPI = n/CONFIG_PLATFORM_ARM64_RPI = y/g' Makefile
-+```
-+
-+In addition, if you receive an error message about `unrecognized command line option ‘-mgeneral-regs-only’` (i.e., Raspbian Buster), you will need to run the following commands:
-+```
-+$ sed -i 's/^dkms build/ARCH=arm dkms build/' dkms-install.sh
-+$ sed -i 's/^MAKE="/MAKE="ARCH=arm\ /' dkms.conf
-+```
-+
-+For setting monitor mode
-+ 1. Fix problematic interference in monitor mode.
-+ ```
-+ $ airmon-ng check kill
-+ ```
-+ You may also uncheck the box "Automatically connect to this network when it is avaiable" in nm-connection-editor. This only works if you have a saved wifi connection.
-+
-+ 2. Set interface down
-+ ```
-+ $ sudo ip link set wlan0 down
-+ ```
-+ 3. Set monitor mode
-+ ```
-+ $ sudo iw dev wlan0 set type monitor
-+ ```
-+ 4. Set interface up
-+ ```
-+ $ sudo ip link set wlan0 up
-+ ```
-+For setting TX power
-+```
-+$ sudo iw wlan0 set txpower fixed 3000
-+```
-+
-+### LED control
-+
-+#### statically by module parameter in /etc/modprobe.d/8812au.conf or wherever, for example:
-+
-+```sh
-+options 88XXau rtw_led_ctrl=0
-+```
-+value can be 0 or 1
-+
-+#### or dynamically by writing to /proc/net/rtl8812au/$(your interface name)/led_ctrl, for example:
-+
-+```sh
-+$ echo "0" > /proc/net/rtl8812au/$(your interface name)/led_ctrl
-+```
-+value can be 0 or 1
-+
-+#### check current value:
-+
-+```sh
-+$ cat /proc/net/rtl8812au/$(your interface name)/led_ctrl
-+```
-+
-+### USB Mode Switch
-+
-+0: doesn't switch, 1: switch from usb2.0 to usb 3.0 2: switch from usb3.0 to usb 2.0
-+```sh
-+$ rmmod 88XXau
-+$ modprobe 88XXau rtw_switch_usb_mode:int (0: no switch 1: switch from usb2 to usb3 2: switch from usb3 to usb2)
-+```
-+
-+### NetworkManager
-+
-+Newer versions of NetworkManager switches to random MAC address. Some users would prefer to use a fixed address.
-+Simply add these lines below
-+```
-+[device]
-+wifi.scan-rand-mac-address=no
-+```
-+at the end of file /etc/NetworkManager/NetworkManager.conf and restart NetworkManager with the command:
-+```
-+$ sudo service NetworkManager restart
-+```
-+
-+### Credits / Contributors
-+
-+```
-+Alfa Networks - https://www.alfa.com.tw/
-+Realtek. - https://www.realtek.com
-+aircrack-ng - https://www.aircrack-ng.org
-+
-+astsam - https://github.com/astsam
-+evilphish - https://github.com/evilphish
-+fariouche - https://github.com/fariouche
-+CGarces - https://github.com/CGarces
-+ZerBea - https://github.com/ZerBea
-+lwfinger - https://github.com/lwfinger
-+Ulli-Kroll. - https://github.com/Ulli-Kroll
-+
-+```
-diff --git linux-5.8/3rdparty/rtl8812au/ReleaseNotes.pdf linux-5.8/3rdparty/rtl8812au/ReleaseNotes.pdf
-new file mode 100644
-index 000000000..6ead272e3
-Binary files /dev/null and linux-5.8/3rdparty/rtl8812au/ReleaseNotes.pdf differ
-diff --git linux-5.8/3rdparty/rtl8812au/core/efuse/rtw_efuse.c linux-5.8/3rdparty/rtl8812au/core/efuse/rtw_efuse.c
-new file mode 100644
-index 000000000..44d8ac468
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/core/efuse/rtw_efuse.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/core/efuse/rtw_efuse.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/core/efuse/rtw_efuse.c
+--- linux-5.11.4/3rdparty/rtl8812au/core/efuse/rtw_efuse.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/core/efuse/rtw_efuse.c 2021-03-07 18:16:17.015954210 +0200
@@ -0,0 +1,3278 @@
+/******************************************************************************
+ *
@@ -6184,11 +3280,9 @@ index 000000000..44d8ac468
+#endif /* CONFIG_EFUSE_CONFIG_FILE */
+
+#endif /* PLATFORM_LINUX */
-diff --git linux-5.8/3rdparty/rtl8812au/core/mesh/rtw_mesh.c linux-5.8/3rdparty/rtl8812au/core/mesh/rtw_mesh.c
-new file mode 100644
-index 000000000..95d0f15ce
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/core/mesh/rtw_mesh.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/core/mesh/rtw_mesh.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/core/mesh/rtw_mesh.c
+--- linux-5.11.4/3rdparty/rtl8812au/core/mesh/rtw_mesh.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/core/mesh/rtw_mesh.c 2021-03-07 18:16:17.016954257 +0200
@@ -0,0 +1,4080 @@
+/******************************************************************************
+ *
@@ -10270,11 +7364,9 @@ index 000000000..95d0f15ce
+}
+#endif /* CONFIG_RTW_MESH */
+
-diff --git linux-5.8/3rdparty/rtl8812au/core/mesh/rtw_mesh.h linux-5.8/3rdparty/rtl8812au/core/mesh/rtw_mesh.h
-new file mode 100644
-index 000000000..73694f84d
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/core/mesh/rtw_mesh.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/core/mesh/rtw_mesh.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/core/mesh/rtw_mesh.h
+--- linux-5.11.4/3rdparty/rtl8812au/core/mesh/rtw_mesh.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/core/mesh/rtw_mesh.h 2021-03-07 18:16:17.016954257 +0200
@@ -0,0 +1,534 @@
+/******************************************************************************
+ *
@@ -10810,11 +7902,9 @@ index 000000000..73694f84d
+#include "rtw_mesh_hwmp.h"
+#endif /* __RTW_MESH_H_ */
+
-diff --git linux-5.8/3rdparty/rtl8812au/core/mesh/rtw_mesh_hwmp.c linux-5.8/3rdparty/rtl8812au/core/mesh/rtw_mesh_hwmp.c
-new file mode 100644
-index 000000000..f64aa3de9
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/core/mesh/rtw_mesh_hwmp.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/core/mesh/rtw_mesh_hwmp.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/core/mesh/rtw_mesh_hwmp.c
+--- linux-5.11.4/3rdparty/rtl8812au/core/mesh/rtw_mesh_hwmp.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/core/mesh/rtw_mesh_hwmp.c 2021-03-07 18:16:17.016954257 +0200
@@ -0,0 +1,1665 @@
+/******************************************************************************
+ *
@@ -12481,11 +9571,9 @@ index 000000000..f64aa3de9
+
+#endif /* CONFIG_RTW_MESH */
+
-diff --git linux-5.8/3rdparty/rtl8812au/core/mesh/rtw_mesh_hwmp.h linux-5.8/3rdparty/rtl8812au/core/mesh/rtw_mesh_hwmp.h
-new file mode 100644
-index 000000000..943341781
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/core/mesh/rtw_mesh_hwmp.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/core/mesh/rtw_mesh_hwmp.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/core/mesh/rtw_mesh_hwmp.h
+--- linux-5.11.4/3rdparty/rtl8812au/core/mesh/rtw_mesh_hwmp.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/core/mesh/rtw_mesh_hwmp.h 2021-03-07 18:16:17.016954257 +0200
@@ -0,0 +1,60 @@
+/******************************************************************************
+ *
@@ -12547,11 +9635,9 @@ index 000000000..943341781
+#endif /* __RTW_MESH_HWMP_H_ */
+
+
-diff --git linux-5.8/3rdparty/rtl8812au/core/mesh/rtw_mesh_pathtbl.c linux-5.8/3rdparty/rtl8812au/core/mesh/rtw_mesh_pathtbl.c
-new file mode 100644
-index 000000000..d8791603d
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/core/mesh/rtw_mesh_pathtbl.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/core/mesh/rtw_mesh_pathtbl.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/core/mesh/rtw_mesh_pathtbl.c
+--- linux-5.11.4/3rdparty/rtl8812au/core/mesh/rtw_mesh_pathtbl.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/core/mesh/rtw_mesh_pathtbl.c 2021-03-07 18:16:17.016954257 +0200
@@ -0,0 +1,1237 @@
+/******************************************************************************
+ *
@@ -13790,11 +10876,9 @@ index 000000000..d8791603d
+}
+#endif /* CONFIG_RTW_MESH */
+
-diff --git linux-5.8/3rdparty/rtl8812au/core/mesh/rtw_mesh_pathtbl.h linux-5.8/3rdparty/rtl8812au/core/mesh/rtw_mesh_pathtbl.h
-new file mode 100644
-index 000000000..650b239f5
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/core/mesh/rtw_mesh_pathtbl.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/core/mesh/rtw_mesh_pathtbl.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/core/mesh/rtw_mesh_pathtbl.h
+--- linux-5.11.4/3rdparty/rtl8812au/core/mesh/rtw_mesh_pathtbl.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/core/mesh/rtw_mesh_pathtbl.h 2021-03-07 18:16:17.016954257 +0200
@@ -0,0 +1,208 @@
+/******************************************************************************
+ *
@@ -14004,11 +11088,9 @@ index 000000000..650b239f5
+
+#endif /* __RTW_MESH_PATHTBL_H_ */
+
-diff --git linux-5.8/3rdparty/rtl8812au/core/rtw_ap.c linux-5.8/3rdparty/rtl8812au/core/rtw_ap.c
-new file mode 100644
-index 000000000..bc78e9c19
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/core/rtw_ap.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/core/rtw_ap.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/core/rtw_ap.c
+--- linux-5.11.4/3rdparty/rtl8812au/core/rtw_ap.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/core/rtw_ap.c 2021-03-07 18:16:17.017954304 +0200
@@ -0,0 +1,5476 @@
+/******************************************************************************
+ *
@@ -19486,11 +16568,9 @@ index 000000000..bc78e9c19
+}
+#endif /* CONFIG_AP_MODE */
+
-diff --git linux-5.8/3rdparty/rtl8812au/core/rtw_beamforming.c linux-5.8/3rdparty/rtl8812au/core/rtw_beamforming.c
-new file mode 100644
-index 000000000..7e5fd7b94
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/core/rtw_beamforming.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/core/rtw_beamforming.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/core/rtw_beamforming.c
+--- linux-5.11.4/3rdparty/rtl8812au/core/rtw_beamforming.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/core/rtw_beamforming.c 2021-03-07 18:16:17.017954304 +0200
@@ -0,0 +1,3155 @@
+/******************************************************************************
+ *
@@ -22647,11 +19727,9 @@ index 000000000..7e5fd7b94
+#endif /* !RTW_BEAMFORMING_VERSION_2 */
+
+#endif /* CONFIG_BEAMFORMING */
-diff --git linux-5.8/3rdparty/rtl8812au/core/rtw_br_ext.c linux-5.8/3rdparty/rtl8812au/core/rtw_br_ext.c
-new file mode 100644
-index 000000000..9a0effd8b
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/core/rtw_br_ext.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/core/rtw_br_ext.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/core/rtw_br_ext.c
+--- linux-5.11.4/3rdparty/rtl8812au/core/rtw_br_ext.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/core/rtw_br_ext.c 2021-03-07 18:16:17.017954304 +0200
@@ -0,0 +1,1581 @@
+/******************************************************************************
+ *
@@ -24234,11 +21312,1831 @@ index 000000000..9a0effd8b
+}
+
+#endif /* CONFIG_BR_EXT */
-diff --git linux-5.8/3rdparty/rtl8812au/core/rtw_bt_mp.c linux-5.8/3rdparty/rtl8812au/core/rtw_bt_mp.c
-new file mode 100644
-index 000000000..9b4fc2432
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/core/rtw_bt_mp.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/core/rtw_btcoex.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/core/rtw_btcoex.c
+--- linux-5.11.4/3rdparty/rtl8812au/core/rtw_btcoex.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/core/rtw_btcoex.c 2021-03-07 18:16:17.017954304 +0200
+@@ -0,0 +1,1767 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2013 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#include
++#include
++#ifdef CONFIG_BT_COEXIST
++#include
++
++void rtw_btcoex_Initialize(PADAPTER padapter)
++{
++ hal_btcoex_Initialize(padapter);
++}
++
++void rtw_btcoex_PowerOnSetting(PADAPTER padapter)
++{
++ hal_btcoex_PowerOnSetting(padapter);
++}
++
++void rtw_btcoex_AntInfoSetting(PADAPTER padapter)
++{
++ hal_btcoex_AntInfoSetting(padapter);
++}
++
++void rtw_btcoex_PowerOffSetting(PADAPTER padapter)
++{
++ hal_btcoex_PowerOffSetting(padapter);
++}
++
++void rtw_btcoex_PreLoadFirmware(PADAPTER padapter)
++{
++ hal_btcoex_PreLoadFirmware(padapter);
++}
++
++void rtw_btcoex_HAL_Initialize(PADAPTER padapter, u8 bWifiOnly)
++{
++ hal_btcoex_InitHwConfig(padapter, bWifiOnly);
++}
++
++void rtw_btcoex_IpsNotify(PADAPTER padapter, u8 type)
++{
++ PHAL_DATA_TYPE pHalData;
++
++ pHalData = GET_HAL_DATA(padapter);
++ if (_FALSE == pHalData->EEPROMBluetoothCoexist)
++ return;
++
++ hal_btcoex_IpsNotify(padapter, type);
++}
++
++void rtw_btcoex_LpsNotify(PADAPTER padapter, u8 type)
++{
++ PHAL_DATA_TYPE pHalData;
++
++ pHalData = GET_HAL_DATA(padapter);
++ if (_FALSE == pHalData->EEPROMBluetoothCoexist)
++ return;
++
++ hal_btcoex_LpsNotify(padapter, type);
++}
++
++void rtw_btcoex_ScanNotify(PADAPTER padapter, u8 type)
++{
++ PHAL_DATA_TYPE pHalData;
++#ifdef CONFIG_BT_COEXIST_SOCKET_TRX
++ struct bt_coex_info *pcoex_info = &padapter->coex_info;
++ PBT_MGNT pBtMgnt = &pcoex_info->BtMgnt;
++#endif /* CONFIG_BT_COEXIST_SOCKET_TRX */
++
++ pHalData = GET_HAL_DATA(padapter);
++ if (_FALSE == pHalData->EEPROMBluetoothCoexist)
++ return;
++
++ if (_FALSE == type) {
++ #ifdef CONFIG_CONCURRENT_MODE
++ if (rtw_mi_buddy_check_fwstate(padapter, WIFI_SITE_MONITOR))
++ return;
++ #endif
++
++ if (DEV_MGMT_TX_NUM(adapter_to_dvobj(padapter))
++ || DEV_ROCH_NUM(adapter_to_dvobj(padapter)))
++ return;
++ }
++
++#ifdef CONFIG_BT_COEXIST_SOCKET_TRX
++ if (pBtMgnt->ExtConfig.bEnableWifiScanNotify)
++ rtw_btcoex_SendScanNotify(padapter, type);
++#endif /* CONFIG_BT_COEXIST_SOCKET_TRX */
++
++ hal_btcoex_ScanNotify(padapter, type);
++}
++
++void rtw_btcoex_ConnectNotify(PADAPTER padapter, u8 action)
++{
++ PHAL_DATA_TYPE pHalData;
++
++ pHalData = GET_HAL_DATA(padapter);
++ if (_FALSE == pHalData->EEPROMBluetoothCoexist)
++ return;
++
++#ifdef DBG_CONFIG_ERROR_RESET
++ if (_TRUE == rtw_hal_sreset_inprogress(padapter)) {
++ RTW_INFO(FUNC_ADPT_FMT ": [BTCoex] under reset, skip notify!\n",
++ FUNC_ADPT_ARG(padapter));
++ return;
++ }
++#endif /* DBG_CONFIG_ERROR_RESET */
++
++#ifdef CONFIG_CONCURRENT_MODE
++ if (_FALSE == action) {
++ if (rtw_mi_buddy_check_fwstate(padapter, WIFI_UNDER_LINKING))
++ return;
++ }
++#endif
++
++ hal_btcoex_ConnectNotify(padapter, action);
++}
++
++void rtw_btcoex_MediaStatusNotify(PADAPTER padapter, u8 mediaStatus)
++{
++ PHAL_DATA_TYPE pHalData;
++
++ pHalData = GET_HAL_DATA(padapter);
++ if (_FALSE == pHalData->EEPROMBluetoothCoexist)
++ return;
++
++#ifdef DBG_CONFIG_ERROR_RESET
++ if (_TRUE == rtw_hal_sreset_inprogress(padapter)) {
++ RTW_INFO(FUNC_ADPT_FMT ": [BTCoex] under reset, skip notify!\n",
++ FUNC_ADPT_ARG(padapter));
++ return;
++ }
++#endif /* DBG_CONFIG_ERROR_RESET */
++
++#ifdef CONFIG_CONCURRENT_MODE
++ if (RT_MEDIA_DISCONNECT == mediaStatus) {
++ if (rtw_mi_buddy_check_fwstate(padapter, WIFI_ASOC_STATE))
++ return;
++ }
++#endif /* CONFIG_CONCURRENT_MODE */
++
++ if ((RT_MEDIA_CONNECT == mediaStatus)
++ && (check_fwstate(&padapter->mlmepriv, WIFI_AP_STATE) == _TRUE))
++ rtw_hal_set_hwreg(padapter, HW_VAR_DL_RSVD_PAGE, NULL);
++
++ hal_btcoex_MediaStatusNotify(padapter, mediaStatus);
++}
++
++void rtw_btcoex_SpecialPacketNotify(PADAPTER padapter, u8 pktType)
++{
++ PHAL_DATA_TYPE pHalData;
++
++ pHalData = GET_HAL_DATA(padapter);
++ if (_FALSE == pHalData->EEPROMBluetoothCoexist)
++ return;
++
++ hal_btcoex_SpecialPacketNotify(padapter, pktType);
++}
++
++void rtw_btcoex_IQKNotify(PADAPTER padapter, u8 state)
++{
++ PHAL_DATA_TYPE pHalData;
++
++ pHalData = GET_HAL_DATA(padapter);
++ if (_FALSE == pHalData->EEPROMBluetoothCoexist)
++ return;
++
++ hal_btcoex_IQKNotify(padapter, state);
++}
++
++void rtw_btcoex_BtInfoNotify(PADAPTER padapter, u8 length, u8 *tmpBuf)
++{
++ PHAL_DATA_TYPE pHalData;
++
++ pHalData = GET_HAL_DATA(padapter);
++ if (_FALSE == pHalData->EEPROMBluetoothCoexist)
++ return;
++
++ hal_btcoex_BtInfoNotify(padapter, length, tmpBuf);
++}
++
++void rtw_btcoex_BtMpRptNotify(PADAPTER padapter, u8 length, u8 *tmpBuf)
++{
++ PHAL_DATA_TYPE pHalData;
++
++ pHalData = GET_HAL_DATA(padapter);
++ if (_FALSE == pHalData->EEPROMBluetoothCoexist)
++ return;
++
++ if (padapter->registrypriv.mp_mode == 1)
++ return;
++
++ hal_btcoex_BtMpRptNotify(padapter, length, tmpBuf);
++}
++
++void rtw_btcoex_SuspendNotify(PADAPTER padapter, u8 state)
++{
++ PHAL_DATA_TYPE pHalData;
++
++ pHalData = GET_HAL_DATA(padapter);
++ if (_FALSE == pHalData->EEPROMBluetoothCoexist)
++ return;
++
++ hal_btcoex_SuspendNotify(padapter, state);
++}
++
++void rtw_btcoex_HaltNotify(PADAPTER padapter)
++{
++ PHAL_DATA_TYPE pHalData;
++ u8 do_halt = 1;
++
++ pHalData = GET_HAL_DATA(padapter);
++ if (_FALSE == pHalData->EEPROMBluetoothCoexist)
++ do_halt = 0;
++
++ if (_FALSE == padapter->bup) {
++ RTW_INFO(FUNC_ADPT_FMT ": bup=%d Skip!\n",
++ FUNC_ADPT_ARG(padapter), padapter->bup);
++ do_halt = 0;
++ }
++
++ if (rtw_is_surprise_removed(padapter)) {
++ RTW_INFO(FUNC_ADPT_FMT ": bSurpriseRemoved=%s Skip!\n",
++ FUNC_ADPT_ARG(padapter), rtw_is_surprise_removed(padapter) ? "True" : "False");
++ do_halt = 0;
++ }
++
++ hal_btcoex_HaltNotify(padapter, do_halt);
++}
++
++void rtw_btcoex_switchband_notify(u8 under_scan, u8 band_type)
++{
++ hal_btcoex_switchband_notify(under_scan, band_type);
++}
++
++void rtw_btcoex_WlFwDbgInfoNotify(PADAPTER padapter, u8* tmpBuf, u8 length)
++{
++ hal_btcoex_WlFwDbgInfoNotify(padapter, tmpBuf, length);
++}
++
++void rtw_btcoex_rx_rate_change_notify(PADAPTER padapter, u8 is_data_frame, u8 rate_id)
++{
++ hal_btcoex_rx_rate_change_notify(padapter, is_data_frame, rate_id);
++}
++
++void rtw_btcoex_SwitchBtTRxMask(PADAPTER padapter)
++{
++ hal_btcoex_SwitchBtTRxMask(padapter);
++}
++
++void rtw_btcoex_Switch(PADAPTER padapter, u8 enable)
++{
++ hal_btcoex_SetBTCoexist(padapter, enable);
++}
++
++u8 rtw_btcoex_IsBtDisabled(PADAPTER padapter)
++{
++ return hal_btcoex_IsBtDisabled(padapter);
++}
++
++void rtw_btcoex_Handler(PADAPTER padapter)
++{
++ PHAL_DATA_TYPE pHalData;
++
++ pHalData = GET_HAL_DATA(padapter);
++
++ if (_FALSE == pHalData->EEPROMBluetoothCoexist)
++ return;
++
++ hal_btcoex_Hanlder(padapter);
++}
++
++s32 rtw_btcoex_IsBTCoexRejectAMPDU(PADAPTER padapter)
++{
++ s32 coexctrl;
++
++ coexctrl = hal_btcoex_IsBTCoexRejectAMPDU(padapter);
++
++ return coexctrl;
++}
++
++s32 rtw_btcoex_IsBTCoexCtrlAMPDUSize(PADAPTER padapter)
++{
++ s32 coexctrl;
++
++ coexctrl = hal_btcoex_IsBTCoexCtrlAMPDUSize(padapter);
++
++ return coexctrl;
++}
++
++u32 rtw_btcoex_GetAMPDUSize(PADAPTER padapter)
++{
++ u32 size;
++
++ size = hal_btcoex_GetAMPDUSize(padapter);
++
++ return size;
++}
++
++void rtw_btcoex_SetManualControl(PADAPTER padapter, u8 manual)
++{
++ if (_TRUE == manual)
++ hal_btcoex_SetManualControl(padapter, _TRUE);
++ else
++ hal_btcoex_SetManualControl(padapter, _FALSE);
++}
++
++u8 rtw_btcoex_1Ant(PADAPTER padapter)
++{
++ return hal_btcoex_1Ant(padapter);
++}
++
++u8 rtw_btcoex_IsBtControlLps(PADAPTER padapter)
++{
++ return hal_btcoex_IsBtControlLps(padapter);
++}
++
++u8 rtw_btcoex_IsLpsOn(PADAPTER padapter)
++{
++ return hal_btcoex_IsLpsOn(padapter);
++}
++
++u8 rtw_btcoex_RpwmVal(PADAPTER padapter)
++{
++ return hal_btcoex_RpwmVal(padapter);
++}
++
++u8 rtw_btcoex_LpsVal(PADAPTER padapter)
++{
++ return hal_btcoex_LpsVal(padapter);
++}
++
++u32 rtw_btcoex_GetRaMask(PADAPTER padapter)
++{
++ return hal_btcoex_GetRaMask(padapter);
++}
++
++void rtw_btcoex_RecordPwrMode(PADAPTER padapter, u8 *pCmdBuf, u8 cmdLen)
++{
++ hal_btcoex_RecordPwrMode(padapter, pCmdBuf, cmdLen);
++}
++
++void rtw_btcoex_DisplayBtCoexInfo(PADAPTER padapter, u8 *pbuf, u32 bufsize)
++{
++ hal_btcoex_DisplayBtCoexInfo(padapter, pbuf, bufsize);
++}
++
++void rtw_btcoex_SetDBG(PADAPTER padapter, u32 *pDbgModule)
++{
++ hal_btcoex_SetDBG(padapter, pDbgModule);
++}
++
++u32 rtw_btcoex_GetDBG(PADAPTER padapter, u8 *pStrBuf, u32 bufSize)
++{
++ return hal_btcoex_GetDBG(padapter, pStrBuf, bufSize);
++}
++
++u8 rtw_btcoex_IncreaseScanDeviceNum(PADAPTER padapter)
++{
++ return hal_btcoex_IncreaseScanDeviceNum(padapter);
++}
++
++u8 rtw_btcoex_IsBtLinkExist(PADAPTER padapter)
++{
++ return hal_btcoex_IsBtLinkExist(padapter);
++}
++
++void rtw_btcoex_SetBtPatchVersion(PADAPTER padapter, u16 btHciVer, u16 btPatchVer)
++{
++ hal_btcoex_SetBtPatchVersion(padapter, btHciVer, btPatchVer);
++}
++
++void rtw_btcoex_SetHciVersion(PADAPTER padapter, u16 hciVersion)
++{
++ hal_btcoex_SetHciVersion(padapter, hciVersion);
++}
++
++void rtw_btcoex_StackUpdateProfileInfo(void)
++{
++ hal_btcoex_StackUpdateProfileInfo();
++}
++
++void rtw_btcoex_pta_off_on_notify(PADAPTER padapter, u8 bBTON)
++{
++ hal_btcoex_pta_off_on_notify(padapter, bBTON);
++}
++
++#ifdef CONFIG_RF4CE_COEXIST
++void rtw_btcoex_SetRf4ceLinkState(PADAPTER padapter, u8 state)
++{
++ hal_btcoex_set_rf4ce_link_state(state);
++}
++
++u8 rtw_btcoex_GetRf4ceLinkState(PADAPTER padapter)
++{
++ return hal_btcoex_get_rf4ce_link_state();
++}
++#endif
++
++/* ==================================================
++ * Below Functions are called by BT-Coex
++ * ================================================== */
++void rtw_btcoex_rx_ampdu_apply(PADAPTER padapter)
++{
++ rtw_rx_ampdu_apply(padapter);
++}
++
++void rtw_btcoex_LPS_Enter(PADAPTER padapter)
++{
++ struct pwrctrl_priv *pwrpriv;
++ u8 lpsVal;
++
++
++ pwrpriv = adapter_to_pwrctl(padapter);
++
++ pwrpriv->bpower_saving = _TRUE;
++ lpsVal = rtw_btcoex_LpsVal(padapter);
++ rtw_set_ps_mode(padapter, PS_MODE_MIN, 0, lpsVal, "BTCOEX");
++}
++
++u8 rtw_btcoex_LPS_Leave(PADAPTER padapter)
++{
++ struct pwrctrl_priv *pwrpriv;
++
++
++ pwrpriv = adapter_to_pwrctl(padapter);
++
++ if (pwrpriv->pwr_mode != PS_MODE_ACTIVE) {
++ rtw_set_ps_mode(padapter, PS_MODE_ACTIVE, 0, 0, "BTCOEX");
++ pwrpriv->bpower_saving = _FALSE;
++ }
++
++ return _TRUE;
++}
++
++u16 rtw_btcoex_btreg_read(PADAPTER padapter, u8 type, u16 addr, u32 *data)
++{
++ return hal_btcoex_btreg_read(padapter, type, addr, data);
++}
++
++u16 rtw_btcoex_btreg_write(PADAPTER padapter, u8 type, u16 addr, u16 val)
++{
++ return hal_btcoex_btreg_write(padapter, type, addr, val);
++}
++
++u8 rtw_btcoex_get_bt_coexist(PADAPTER padapter)
++{
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
++
++ return pHalData->EEPROMBluetoothCoexist;
++}
++
++u8 rtw_btcoex_get_chip_type(PADAPTER padapter)
++{
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
++
++ return pHalData->EEPROMBluetoothType;
++}
++
++u8 rtw_btcoex_get_pg_ant_num(PADAPTER padapter)
++{
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
++
++ return pHalData->EEPROMBluetoothAntNum == Ant_x2 ? 2 : 1;
++}
++
++u8 rtw_btcoex_get_pg_single_ant_path(PADAPTER padapter)
++{
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
++
++ return pHalData->ant_path;
++}
++
++u8 rtw_btcoex_get_pg_rfe_type(PADAPTER padapter)
++{
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
++
++ return pHalData->rfe_type;
++}
++
++u8 rtw_btcoex_is_tfbga_package_type(PADAPTER padapter)
++{
++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
++
++#ifdef CONFIG_RTL8723B
++ if ((pHalData->PackageType == PACKAGE_TFBGA79) || (pHalData->PackageType == PACKAGE_TFBGA80)
++ || (pHalData->PackageType == PACKAGE_TFBGA90))
++ return _TRUE;
++#endif
++
++ return _FALSE;
++}
++
++u8 rtw_btcoex_get_ant_div_cfg(PADAPTER padapter)
++{
++ PHAL_DATA_TYPE pHalData;
++
++ pHalData = GET_HAL_DATA(padapter);
++
++ return (pHalData->AntDivCfg == 0) ? _FALSE : _TRUE;
++}
++
++/* ==================================================
++ * Below Functions are BT-Coex socket related function
++ * ================================================== */
++
++#ifdef CONFIG_BT_COEXIST_SOCKET_TRX
++_adapter *pbtcoexadapter; /* = NULL; */ /* do not initialise globals to 0 or NULL */
++u8 rtw_btcoex_btinfo_cmd(_adapter *adapter, u8 *buf, u16 len)
++{
++ struct cmd_obj *ph2c;
++ struct drvextra_cmd_parm *pdrvextra_cmd_parm;
++ u8 *btinfo;
++ struct cmd_priv *pcmdpriv = &adapter->cmdpriv;
++ u8 res = _SUCCESS;
++
++ ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
++ if (ph2c == NULL) {
++ res = _FAIL;
++ goto exit;
++ }
++
++ pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));
++ if (pdrvextra_cmd_parm == NULL) {
++ rtw_mfree((u8 *)ph2c, sizeof(struct cmd_obj));
++ res = _FAIL;
++ goto exit;
++ }
++
++ btinfo = rtw_zmalloc(len);
++ if (btinfo == NULL) {
++ rtw_mfree((u8 *)ph2c, sizeof(struct cmd_obj));
++ rtw_mfree((u8 *)pdrvextra_cmd_parm, sizeof(struct drvextra_cmd_parm));
++ res = _FAIL;
++ goto exit;
++ }
++
++ pdrvextra_cmd_parm->ec_id = BTINFO_WK_CID;
++ pdrvextra_cmd_parm->type = 0;
++ pdrvextra_cmd_parm->size = len;
++ pdrvextra_cmd_parm->pbuf = btinfo;
++
++ _rtw_memcpy(btinfo, buf, len);
++
++ init_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, GEN_CMD_CODE(_Set_Drv_Extra));
++
++ res = rtw_enqueue_cmd(pcmdpriv, ph2c);
++
++exit:
++ return res;
++}
++
++u8 rtw_btcoex_send_event_to_BT(_adapter *padapter, u8 status, u8 event_code, u8 opcode_low, u8 opcode_high, u8 *dbg_msg)
++{
++ u8 localBuf[6] = "";
++ u8 *pRetPar;
++ u8 len = 0, tx_event_length = 0;
++ rtw_HCI_event *pEvent;
++
++ pEvent = (rtw_HCI_event *)(&localBuf[0]);
++
++ pEvent->EventCode = event_code;
++ pEvent->Data[0] = 0x1; /* packet # */
++ pEvent->Data[1] = opcode_low;
++ pEvent->Data[2] = opcode_high;
++ len = len + 3;
++
++ /* Return parameters starts from here */
++ pRetPar = &pEvent->Data[len];
++ pRetPar[0] = status; /* status */
++
++ len++;
++ pEvent->Length = len;
++
++ /* total tx event length + EventCode length + sizeof(length) */
++ tx_event_length = pEvent->Length + 2;
++#if 0
++ rtw_btcoex_dump_tx_msg((u8 *)pEvent, tx_event_length, dbg_msg);
++#endif
++ status = rtw_btcoex_sendmsgbysocket(padapter, (u8 *)pEvent, tx_event_length, _FALSE);
++
++ return status;
++}
++
++/*
++Ref:
++Realtek Wi-Fi Driver
++Host Controller Interface for
++Bluetooth 3.0 + HS V1.4 2013/02/07
++
++Window team code & BT team code
++ */
++
++
++u8 rtw_btcoex_parse_BT_info_notify_cmd(_adapter *padapter, u8 *pcmd, u16 cmdlen)
++{
++#define BT_INFO_LENGTH 8
++
++ u8 curPollEnable = pcmd[0];
++ u8 curPollTime = pcmd[1];
++ u8 btInfoReason = pcmd[2];
++ u8 btInfoLen = pcmd[3];
++ u8 btinfo[BT_INFO_LENGTH];
++
++ u8 localBuf[6] = "";
++ u8 *pRetPar;
++ u8 len = 0, tx_event_length = 0;
++ RTW_HCI_STATUS status = HCI_STATUS_SUCCESS;
++ rtw_HCI_event *pEvent;
++
++ /* RTW_INFO("%s\n",__func__);
++ RTW_INFO("current Poll Enable: %d, currrent Poll Time: %d\n",curPollEnable,curPollTime);
++ RTW_INFO("BT Info reason: %d, BT Info length: %d\n",btInfoReason,btInfoLen);
++ RTW_INFO("%02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n"
++ ,pcmd[4],pcmd[5],pcmd[6],pcmd[7],pcmd[8],pcmd[9],pcmd[10],pcmd[11]);*/
++
++ _rtw_memset(btinfo, 0, BT_INFO_LENGTH);
++
++#if 1
++ if (BT_INFO_LENGTH != btInfoLen) {
++ status = HCI_STATUS_INVALID_HCI_CMD_PARA_VALUE;
++ RTW_INFO("Error BT Info Length: %d\n", btInfoLen);
++ /* return _FAIL; */
++ } else
++#endif
++ {
++ if (0x1 == btInfoReason || 0x2 == btInfoReason) {
++ _rtw_memcpy(btinfo, &pcmd[4], btInfoLen);
++ btinfo[0] = btInfoReason;
++ rtw_btcoex_btinfo_cmd(padapter, btinfo, btInfoLen);
++ } else
++ RTW_INFO("Other BT info reason\n");
++ }
++
++ /* send complete event to BT */
++ {
++
++ pEvent = (rtw_HCI_event *)(&localBuf[0]);
++
++ pEvent->EventCode = HCI_EVENT_COMMAND_COMPLETE;
++ pEvent->Data[0] = 0x1; /* packet # */
++ pEvent->Data[1] = HCIOPCODELOW(HCI_BT_INFO_NOTIFY, OGF_EXTENSION);
++ pEvent->Data[2] = HCIOPCODEHIGHT(HCI_BT_INFO_NOTIFY, OGF_EXTENSION);
++ len = len + 3;
++
++ /* Return parameters starts from here */
++ pRetPar = &pEvent->Data[len];
++ pRetPar[0] = status; /* status */
++
++ len++;
++ pEvent->Length = len;
++
++ /* total tx event length + EventCode length + sizeof(length) */
++ tx_event_length = pEvent->Length + 2;
++#if 0
++ rtw_btcoex_dump_tx_msg((u8 *)pEvent, tx_event_length, "BT_info_event");
++#endif
++ status = rtw_btcoex_sendmsgbysocket(padapter, (u8 *)pEvent, tx_event_length, _FALSE);
++
++ return status;
++ /* bthci_IndicateEvent(Adapter, PPacketIrpEvent, len+2); */
++ }
++}
++
++u8 rtw_btcoex_parse_BT_patch_ver_info_cmd(_adapter *padapter, u8 *pcmd, u16 cmdlen)
++{
++ RTW_HCI_STATUS status = HCI_STATUS_SUCCESS;
++ u16 btPatchVer = 0x0, btHciVer = 0x0;
++ /* u16 *pU2tmp; */
++
++ u8 localBuf[6] = "";
++ u8 *pRetPar;
++ u8 len = 0, tx_event_length = 0;
++ rtw_HCI_event *pEvent;
++
++ btHciVer = pcmd[0] | pcmd[1] << 8;
++ btPatchVer = pcmd[2] | pcmd[3] << 8;
++
++
++ RTW_INFO("%s, cmd:%02x %02x %02x %02x\n", __func__, pcmd[0] , pcmd[1] , pcmd[2] , pcmd[3]);
++ RTW_INFO("%s, HCI Ver:%d, Patch Ver:%d\n", __func__, btHciVer, btPatchVer);
++
++ rtw_btcoex_SetBtPatchVersion(padapter, btHciVer, btPatchVer);
++
++
++ /* send complete event to BT */
++ {
++ pEvent = (rtw_HCI_event *)(&localBuf[0]);
++
++
++ pEvent->EventCode = HCI_EVENT_COMMAND_COMPLETE;
++ pEvent->Data[0] = 0x1; /* packet # */
++ pEvent->Data[1] = HCIOPCODELOW(HCI_BT_PATCH_VERSION_NOTIFY, OGF_EXTENSION);
++ pEvent->Data[2] = HCIOPCODEHIGHT(HCI_BT_PATCH_VERSION_NOTIFY, OGF_EXTENSION);
++ len = len + 3;
++
++ /* Return parameters starts from here */
++ pRetPar = &pEvent->Data[len];
++ pRetPar[0] = status; /* status */
++
++ len++;
++ pEvent->Length = len;
++
++ /* total tx event length + EventCode length + sizeof(length) */
++ tx_event_length = pEvent->Length + 2;
++#if 0
++ rtw_btcoex_dump_tx_msg((u8 *)pEvent, tx_event_length, "BT_patch_event");
++#endif
++ status = rtw_btcoex_sendmsgbysocket(padapter, (u8 *)pEvent, tx_event_length, _FALSE);
++ return status;
++ /* bthci_IndicateEvent(Adapter, PPacketIrpEvent, len+2); */
++ }
++}
++
++u8 rtw_btcoex_parse_HCI_Ver_notify_cmd(_adapter *padapter, u8 *pcmd, u16 cmdlen)
++{
++ RTW_HCI_STATUS status = HCI_STATUS_SUCCESS;
++ u16 hciver = pcmd[0] | pcmd[1] << 8;
++
++ u8 localBuf[6] = "";
++ u8 *pRetPar;
++ u8 len = 0, tx_event_length = 0;
++ rtw_HCI_event *pEvent;
++
++ struct bt_coex_info *pcoex_info = &padapter->coex_info;
++ PBT_MGNT pBtMgnt = &pcoex_info->BtMgnt;
++ pBtMgnt->ExtConfig.HCIExtensionVer = hciver;
++ RTW_INFO("%s, HCI Version: %d\n", __func__, pBtMgnt->ExtConfig.HCIExtensionVer);
++ if (pBtMgnt->ExtConfig.HCIExtensionVer < 4) {
++ status = HCI_STATUS_INVALID_HCI_CMD_PARA_VALUE;
++ RTW_INFO("%s, Version = %d, HCI Version < 4\n", __func__, pBtMgnt->ExtConfig.HCIExtensionVer);
++ } else
++ rtw_btcoex_SetHciVersion(padapter, hciver);
++ /* send complete event to BT */
++ {
++ pEvent = (rtw_HCI_event *)(&localBuf[0]);
++
++
++ pEvent->EventCode = HCI_EVENT_COMMAND_COMPLETE;
++ pEvent->Data[0] = 0x1; /* packet # */
++ pEvent->Data[1] = HCIOPCODELOW(HCI_EXTENSION_VERSION_NOTIFY, OGF_EXTENSION);
++ pEvent->Data[2] = HCIOPCODEHIGHT(HCI_EXTENSION_VERSION_NOTIFY, OGF_EXTENSION);
++ len = len + 3;
++
++ /* Return parameters starts from here */
++ pRetPar = &pEvent->Data[len];
++ pRetPar[0] = status; /* status */
++
++ len++;
++ pEvent->Length = len;
++
++ /* total tx event length + EventCode length + sizeof(length) */
++ tx_event_length = pEvent->Length + 2;
++
++ status = rtw_btcoex_sendmsgbysocket(padapter, (u8 *)pEvent, tx_event_length, _FALSE);
++ return status;
++ /* bthci_IndicateEvent(Adapter, PPacketIrpEvent, len+2); */
++ }
++
++}
++
++u8 rtw_btcoex_parse_WIFI_scan_notify_cmd(_adapter *padapter, u8 *pcmd, u16 cmdlen)
++{
++ RTW_HCI_STATUS status = HCI_STATUS_SUCCESS;
++
++ u8 localBuf[6] = "";
++ u8 *pRetPar;
++ u8 len = 0, tx_event_length = 0;
++ rtw_HCI_event *pEvent;
++
++ struct bt_coex_info *pcoex_info = &padapter->coex_info;
++ PBT_MGNT pBtMgnt = &pcoex_info->BtMgnt;
++ pBtMgnt->ExtConfig.bEnableWifiScanNotify = pcmd[0];
++ RTW_INFO("%s, bEnableWifiScanNotify: %d\n", __func__, pBtMgnt->ExtConfig.bEnableWifiScanNotify);
++
++ /* send complete event to BT */
++ {
++ pEvent = (rtw_HCI_event *)(&localBuf[0]);
++
++
++ pEvent->EventCode = HCI_EVENT_COMMAND_COMPLETE;
++ pEvent->Data[0] = 0x1; /* packet # */
++ pEvent->Data[1] = HCIOPCODELOW(HCI_ENABLE_WIFI_SCAN_NOTIFY, OGF_EXTENSION);
++ pEvent->Data[2] = HCIOPCODEHIGHT(HCI_ENABLE_WIFI_SCAN_NOTIFY, OGF_EXTENSION);
++ len = len + 3;
++
++ /* Return parameters starts from here */
++ pRetPar = &pEvent->Data[len];
++ pRetPar[0] = status; /* status */
++
++ len++;
++ pEvent->Length = len;
++
++ /* total tx event length + EventCode length + sizeof(length) */
++ tx_event_length = pEvent->Length + 2;
++
++ status = rtw_btcoex_sendmsgbysocket(padapter, (u8 *)pEvent, tx_event_length, _FALSE);
++ return status;
++ /* bthci_IndicateEvent(Adapter, PPacketIrpEvent, len+2); */
++ }
++}
++
++u8 rtw_btcoex_parse_HCI_link_status_notify_cmd(_adapter *padapter, u8 *pcmd, u16 cmdlen)
++{
++ RTW_HCI_STATUS status = HCI_STATUS_SUCCESS;
++ struct bt_coex_info *pcoex_info = &padapter->coex_info;
++ PBT_MGNT pBtMgnt = &pcoex_info->BtMgnt;
++ /* PBT_DBG pBtDbg=&padapter->MgntInfo.BtInfo.BtDbg; */
++ u8 i, numOfHandle = 0, numOfAcl = 0;
++ u16 conHandle;
++ u8 btProfile, btCoreSpec, linkRole;
++ u8 *pTriple;
++
++ u8 localBuf[6] = "";
++ u8 *pRetPar;
++ u8 len = 0, tx_event_length = 0;
++ rtw_HCI_event *pEvent;
++
++ /* pBtDbg->dbgHciInfo.hciCmdCntLinkStatusNotify++; */
++ /* RT_DISP_DATA(FIOCTL, IOCTL_BT_HCICMD_EXT, "LinkStatusNotify, Hex Data :\n", */
++ /* &pHciCmd->Data[0], pHciCmd->Length); */
++
++ RTW_INFO("BTLinkStatusNotify\n");
++
++ /* Current only RTL8723 support this command. */
++ /* pBtMgnt->bSupportProfile = TRUE; */
++ pBtMgnt->bSupportProfile = _FALSE;
++
++ pBtMgnt->ExtConfig.NumberOfACL = 0;
++ pBtMgnt->ExtConfig.NumberOfSCO = 0;
++
++ numOfHandle = pcmd[0];
++ /* RT_DISP(FIOCTL, IOCTL_BT_HCICMD_EXT, ("numOfHandle = 0x%x\n", numOfHandle)); */
++ /* RT_DISP(FIOCTL, IOCTL_BT_HCICMD_EXT, ("HCIExtensionVer = %d\n", pBtMgnt->ExtConfig.HCIExtensionVer)); */
++ RTW_INFO("numOfHandle = 0x%x\n", numOfHandle);
++ RTW_INFO("HCIExtensionVer = %d\n", pBtMgnt->ExtConfig.HCIExtensionVer);
++
++ pTriple = &pcmd[1];
++ for (i = 0; i < numOfHandle; i++) {
++ if (pBtMgnt->ExtConfig.HCIExtensionVer < 1) {
++ conHandle = *((u8 *)&pTriple[0]);
++ btProfile = pTriple[2];
++ btCoreSpec = pTriple[3];
++ if (BT_PROFILE_SCO == btProfile)
++ pBtMgnt->ExtConfig.NumberOfSCO++;
++ else {
++ pBtMgnt->ExtConfig.NumberOfACL++;
++ pBtMgnt->ExtConfig.aclLink[i].ConnectHandle = conHandle;
++ pBtMgnt->ExtConfig.aclLink[i].BTProfile = btProfile;
++ pBtMgnt->ExtConfig.aclLink[i].BTCoreSpec = btCoreSpec;
++ }
++ /* RT_DISP(FIOCTL, IOCTL_BT_HCICMD_EXT, */
++ /* ("Connection_Handle=0x%x, BTProfile=%d, BTSpec=%d\n", */
++ /* conHandle, btProfile, btCoreSpec)); */
++ RTW_INFO("Connection_Handle=0x%x, BTProfile=%d, BTSpec=%d\n", conHandle, btProfile, btCoreSpec);
++ pTriple += 4;
++ } else if (pBtMgnt->ExtConfig.HCIExtensionVer >= 1) {
++ conHandle = *((pu2Byte)&pTriple[0]);
++ btProfile = pTriple[2];
++ btCoreSpec = pTriple[3];
++ linkRole = pTriple[4];
++ if (BT_PROFILE_SCO == btProfile)
++ pBtMgnt->ExtConfig.NumberOfSCO++;
++ else {
++ pBtMgnt->ExtConfig.NumberOfACL++;
++ pBtMgnt->ExtConfig.aclLink[i].ConnectHandle = conHandle;
++ pBtMgnt->ExtConfig.aclLink[i].BTProfile = btProfile;
++ pBtMgnt->ExtConfig.aclLink[i].BTCoreSpec = btCoreSpec;
++ pBtMgnt->ExtConfig.aclLink[i].linkRole = linkRole;
++ }
++ /* RT_DISP(FIOCTL, IOCTL_BT_HCICMD_EXT, */
++ RTW_INFO("Connection_Handle=0x%x, BTProfile=%d, BTSpec=%d, LinkRole=%d\n",
++ conHandle, btProfile, btCoreSpec, linkRole);
++ pTriple += 5;
++ }
++ }
++ rtw_btcoex_StackUpdateProfileInfo();
++
++ /* send complete event to BT */
++ {
++ pEvent = (rtw_HCI_event *)(&localBuf[0]);
++
++
++ pEvent->EventCode = HCI_EVENT_COMMAND_COMPLETE;
++ pEvent->Data[0] = 0x1; /* packet # */
++ pEvent->Data[1] = HCIOPCODELOW(HCI_LINK_STATUS_NOTIFY, OGF_EXTENSION);
++ pEvent->Data[2] = HCIOPCODEHIGHT(HCI_LINK_STATUS_NOTIFY, OGF_EXTENSION);
++ len = len + 3;
++
++ /* Return parameters starts from here */
++ pRetPar = &pEvent->Data[len];
++ pRetPar[0] = status; /* status */
++
++ len++;
++ pEvent->Length = len;
++
++ /* total tx event length + EventCode length + sizeof(length) */
++ tx_event_length = pEvent->Length + 2;
++
++ status = rtw_btcoex_sendmsgbysocket(padapter, (u8 *)pEvent, tx_event_length, _FALSE);
++ return status;
++ /* bthci_IndicateEvent(Adapter, PPacketIrpEvent, len+2); */
++ }
++
++
++}
++
++u8 rtw_btcoex_parse_HCI_BT_coex_notify_cmd(_adapter *padapter, u8 *pcmd, u16 cmdlen)
++{
++ u8 localBuf[6] = "";
++ u8 *pRetPar;
++ u8 len = 0, tx_event_length = 0;
++ rtw_HCI_event *pEvent;
++ RTW_HCI_STATUS status = HCI_STATUS_SUCCESS;
++
++ {
++ pEvent = (rtw_HCI_event *)(&localBuf[0]);
++
++
++ pEvent->EventCode = HCI_EVENT_COMMAND_COMPLETE;
++ pEvent->Data[0] = 0x1; /* packet # */
++ pEvent->Data[1] = HCIOPCODELOW(HCI_BT_COEX_NOTIFY, OGF_EXTENSION);
++ pEvent->Data[2] = HCIOPCODEHIGHT(HCI_BT_COEX_NOTIFY, OGF_EXTENSION);
++ len = len + 3;
++
++ /* Return parameters starts from here */
++ pRetPar = &pEvent->Data[len];
++ pRetPar[0] = status; /* status */
++
++ len++;
++ pEvent->Length = len;
++
++ /* total tx event length + EventCode length + sizeof(length) */
++ tx_event_length = pEvent->Length + 2;
++
++ status = rtw_btcoex_sendmsgbysocket(padapter, (u8 *)pEvent, tx_event_length, _FALSE);
++ return status;
++ /* bthci_IndicateEvent(Adapter, PPacketIrpEvent, len+2); */
++ }
++}
++
++u8 rtw_btcoex_parse_HCI_BT_operation_notify_cmd(_adapter *padapter, u8 *pcmd, u16 cmdlen)
++{
++ u8 localBuf[6] = "";
++ u8 *pRetPar;
++ u8 len = 0, tx_event_length = 0;
++ rtw_HCI_event *pEvent;
++ RTW_HCI_STATUS status = HCI_STATUS_SUCCESS;
++
++ RTW_INFO("%s, OP code: %d\n", __func__, pcmd[0]);
++
++ switch (pcmd[0]) {
++ case HCI_BT_OP_NONE:
++ RTW_INFO("[bt operation] : Operation None!!\n");
++ break;
++ case HCI_BT_OP_INQUIRY_START:
++ RTW_INFO("[bt operation] : Inquiry start!!\n");
++ break;
++ case HCI_BT_OP_INQUIRY_FINISH:
++ RTW_INFO("[bt operation] : Inquiry finished!!\n");
++ break;
++ case HCI_BT_OP_PAGING_START:
++ RTW_INFO("[bt operation] : Paging is started!!\n");
++ break;
++ case HCI_BT_OP_PAGING_SUCCESS:
++ RTW_INFO("[bt operation] : Paging complete successfully!!\n");
++ break;
++ case HCI_BT_OP_PAGING_UNSUCCESS:
++ RTW_INFO("[bt operation] : Paging complete unsuccessfully!!\n");
++ break;
++ case HCI_BT_OP_PAIRING_START:
++ RTW_INFO("[bt operation] : Pairing start!!\n");
++ break;
++ case HCI_BT_OP_PAIRING_FINISH:
++ RTW_INFO("[bt operation] : Pairing finished!!\n");
++ break;
++ case HCI_BT_OP_BT_DEV_ENABLE:
++ RTW_INFO("[bt operation] : BT Device is enabled!!\n");
++ break;
++ case HCI_BT_OP_BT_DEV_DISABLE:
++ RTW_INFO("[bt operation] : BT Device is disabled!!\n");
++ break;
++ default:
++ RTW_INFO("[bt operation] : Unknown, error!!\n");
++ break;
++ }
++
++ /* send complete event to BT */
++ {
++ pEvent = (rtw_HCI_event *)(&localBuf[0]);
++
++
++ pEvent->EventCode = HCI_EVENT_COMMAND_COMPLETE;
++ pEvent->Data[0] = 0x1; /* packet # */
++ pEvent->Data[1] = HCIOPCODELOW(HCI_BT_OPERATION_NOTIFY, OGF_EXTENSION);
++ pEvent->Data[2] = HCIOPCODEHIGHT(HCI_BT_OPERATION_NOTIFY, OGF_EXTENSION);
++ len = len + 3;
++
++ /* Return parameters starts from here */
++ pRetPar = &pEvent->Data[len];
++ pRetPar[0] = status; /* status */
++
++ len++;
++ pEvent->Length = len;
++
++ /* total tx event length + EventCode length + sizeof(length) */
++ tx_event_length = pEvent->Length + 2;
++
++ status = rtw_btcoex_sendmsgbysocket(padapter, (u8 *)pEvent, tx_event_length, _FALSE);
++ return status;
++ /* bthci_IndicateEvent(Adapter, PPacketIrpEvent, len+2); */
++ }
++}
++
++u8 rtw_btcoex_parse_BT_AFH_MAP_notify_cmd(_adapter *padapter, u8 *pcmd, u16 cmdlen)
++{
++ u8 localBuf[6] = "";
++ u8 *pRetPar;
++ u8 len = 0, tx_event_length = 0;
++ rtw_HCI_event *pEvent;
++ RTW_HCI_STATUS status = HCI_STATUS_SUCCESS;
++
++ {
++ pEvent = (rtw_HCI_event *)(&localBuf[0]);
++
++
++ pEvent->EventCode = HCI_EVENT_COMMAND_COMPLETE;
++ pEvent->Data[0] = 0x1; /* packet # */
++ pEvent->Data[1] = HCIOPCODELOW(HCI_BT_AFH_MAP_NOTIFY, OGF_EXTENSION);
++ pEvent->Data[2] = HCIOPCODEHIGHT(HCI_BT_AFH_MAP_NOTIFY, OGF_EXTENSION);
++ len = len + 3;
++
++ /* Return parameters starts from here */
++ pRetPar = &pEvent->Data[len];
++ pRetPar[0] = status; /* status */
++
++ len++;
++ pEvent->Length = len;
++
++ /* total tx event length + EventCode length + sizeof(length) */
++ tx_event_length = pEvent->Length + 2;
++
++ status = rtw_btcoex_sendmsgbysocket(padapter, (u8 *)pEvent, tx_event_length, _FALSE);
++ return status;
++ /* bthci_IndicateEvent(Adapter, PPacketIrpEvent, len+2); */
++ }
++}
++
++u8 rtw_btcoex_parse_BT_register_val_notify_cmd(_adapter *padapter, u8 *pcmd, u16 cmdlen)
++{
++
++ u8 localBuf[6] = "";
++ u8 *pRetPar;
++ u8 len = 0, tx_event_length = 0;
++ rtw_HCI_event *pEvent;
++ RTW_HCI_STATUS status = HCI_STATUS_SUCCESS;
++
++ {
++ pEvent = (rtw_HCI_event *)(&localBuf[0]);
++
++
++ pEvent->EventCode = HCI_EVENT_COMMAND_COMPLETE;
++ pEvent->Data[0] = 0x1; /* packet # */
++ pEvent->Data[1] = HCIOPCODELOW(HCI_BT_REGISTER_VALUE_NOTIFY, OGF_EXTENSION);
++ pEvent->Data[2] = HCIOPCODEHIGHT(HCI_BT_REGISTER_VALUE_NOTIFY, OGF_EXTENSION);
++ len = len + 3;
++
++ /* Return parameters starts from here */
++ pRetPar = &pEvent->Data[len];
++ pRetPar[0] = status; /* status */
++
++ len++;
++ pEvent->Length = len;
++
++ /* total tx event length + EventCode length + sizeof(length) */
++ tx_event_length = pEvent->Length + 2;
++
++ status = rtw_btcoex_sendmsgbysocket(padapter, (u8 *)pEvent, tx_event_length, _FALSE);
++ return status;
++ /* bthci_IndicateEvent(Adapter, PPacketIrpEvent, len+2); */
++ }
++}
++
++u8 rtw_btcoex_parse_HCI_BT_abnormal_notify_cmd(_adapter *padapter, u8 *pcmd, u16 cmdlen)
++{
++ u8 localBuf[6] = "";
++ u8 *pRetPar;
++ u8 len = 0, tx_event_length = 0;
++ rtw_HCI_event *pEvent;
++ RTW_HCI_STATUS status = HCI_STATUS_SUCCESS;
++
++ {
++ pEvent = (rtw_HCI_event *)(&localBuf[0]);
++
++
++ pEvent->EventCode = HCI_EVENT_COMMAND_COMPLETE;
++ pEvent->Data[0] = 0x1; /* packet # */
++ pEvent->Data[1] = HCIOPCODELOW(HCI_BT_ABNORMAL_NOTIFY, OGF_EXTENSION);
++ pEvent->Data[2] = HCIOPCODEHIGHT(HCI_BT_ABNORMAL_NOTIFY, OGF_EXTENSION);
++ len = len + 3;
++
++ /* Return parameters starts from here */
++ pRetPar = &pEvent->Data[len];
++ pRetPar[0] = status; /* status */
++
++ len++;
++ pEvent->Length = len;
++
++ /* total tx event length + EventCode length + sizeof(length) */
++ tx_event_length = pEvent->Length + 2;
++
++ status = rtw_btcoex_sendmsgbysocket(padapter, (u8 *)pEvent, tx_event_length, _FALSE);
++ return status;
++ /* bthci_IndicateEvent(Adapter, PPacketIrpEvent, len+2); */
++ }
++}
++
++u8 rtw_btcoex_parse_HCI_query_RF_status_cmd(_adapter *padapter, u8 *pcmd, u16 cmdlen)
++{
++ u8 localBuf[6] = "";
++ u8 *pRetPar;
++ u8 len = 0, tx_event_length = 0;
++ rtw_HCI_event *pEvent;
++ RTW_HCI_STATUS status = HCI_STATUS_SUCCESS;
++
++ {
++ pEvent = (rtw_HCI_event *)(&localBuf[0]);
++
++
++ pEvent->EventCode = HCI_EVENT_COMMAND_COMPLETE;
++ pEvent->Data[0] = 0x1; /* packet # */
++ pEvent->Data[1] = HCIOPCODELOW(HCI_QUERY_RF_STATUS, OGF_EXTENSION);
++ pEvent->Data[2] = HCIOPCODEHIGHT(HCI_QUERY_RF_STATUS, OGF_EXTENSION);
++ len = len + 3;
++
++ /* Return parameters starts from here */
++ pRetPar = &pEvent->Data[len];
++ pRetPar[0] = status; /* status */
++
++ len++;
++ pEvent->Length = len;
++
++ /* total tx event length + EventCode length + sizeof(length) */
++ tx_event_length = pEvent->Length + 2;
++
++ status = rtw_btcoex_sendmsgbysocket(padapter, (u8 *)pEvent, tx_event_length, _FALSE);
++ return status;
++ /* bthci_IndicateEvent(Adapter, PPacketIrpEvent, len+2); */
++ }
++}
++
++/*****************************************
++* HCI cmd format :
++*| 15 - 0 |
++*| OPcode (OCF|OGF<<10) |
++*| 15 - 8 |7 - 0 |
++*|Cmd para |Cmd para Length |
++*|Cmd para...... |
++******************************************/
++
++/* bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
++ * | OCF | OGF | */
++void rtw_btcoex_parse_hci_extend_cmd(_adapter *padapter, u8 *pcmd, u16 len, const u16 hci_OCF)
++{
++
++ RTW_INFO("%s: OCF: %x\n", __func__, hci_OCF);
++ switch (hci_OCF) {
++ case HCI_EXTENSION_VERSION_NOTIFY:
++ RTW_INFO("HCI_EXTENSION_VERSION_NOTIFY\n");
++ rtw_btcoex_parse_HCI_Ver_notify_cmd(padapter, pcmd, len);
++ break;
++ case HCI_LINK_STATUS_NOTIFY:
++ RTW_INFO("HCI_LINK_STATUS_NOTIFY\n");
++ rtw_btcoex_parse_HCI_link_status_notify_cmd(padapter, pcmd, len);
++ break;
++ case HCI_BT_OPERATION_NOTIFY:
++ /* only for 8723a 2ant */
++ RTW_INFO("HCI_BT_OPERATION_NOTIFY\n");
++ rtw_btcoex_parse_HCI_BT_operation_notify_cmd(padapter, pcmd, len);
++ /* */
++ break;
++ case HCI_ENABLE_WIFI_SCAN_NOTIFY:
++ RTW_INFO("HCI_ENABLE_WIFI_SCAN_NOTIFY\n");
++ rtw_btcoex_parse_WIFI_scan_notify_cmd(padapter, pcmd, len);
++ break;
++ case HCI_QUERY_RF_STATUS:
++ /* only for 8723b 2ant */
++ RTW_INFO("HCI_QUERY_RF_STATUS\n");
++ rtw_btcoex_parse_HCI_query_RF_status_cmd(padapter, pcmd, len);
++ break;
++ case HCI_BT_ABNORMAL_NOTIFY:
++ RTW_INFO("HCI_BT_ABNORMAL_NOTIFY\n");
++ rtw_btcoex_parse_HCI_BT_abnormal_notify_cmd(padapter, pcmd, len);
++ break;
++ case HCI_BT_INFO_NOTIFY:
++ RTW_INFO("HCI_BT_INFO_NOTIFY\n");
++ rtw_btcoex_parse_BT_info_notify_cmd(padapter, pcmd, len);
++ break;
++ case HCI_BT_COEX_NOTIFY:
++ RTW_INFO("HCI_BT_COEX_NOTIFY\n");
++ rtw_btcoex_parse_HCI_BT_coex_notify_cmd(padapter, pcmd, len);
++ break;
++ case HCI_BT_PATCH_VERSION_NOTIFY:
++ RTW_INFO("HCI_BT_PATCH_VERSION_NOTIFY\n");
++ rtw_btcoex_parse_BT_patch_ver_info_cmd(padapter, pcmd, len);
++ break;
++ case HCI_BT_AFH_MAP_NOTIFY:
++ RTW_INFO("HCI_BT_AFH_MAP_NOTIFY\n");
++ rtw_btcoex_parse_BT_AFH_MAP_notify_cmd(padapter, pcmd, len);
++ break;
++ case HCI_BT_REGISTER_VALUE_NOTIFY:
++ RTW_INFO("HCI_BT_REGISTER_VALUE_NOTIFY\n");
++ rtw_btcoex_parse_BT_register_val_notify_cmd(padapter, pcmd, len);
++ break;
++ default:
++ RTW_INFO("ERROR!!! Unknown OCF: %x\n", hci_OCF);
++ break;
++
++ }
++}
++
++void rtw_btcoex_parse_hci_cmd(_adapter *padapter, u8 *pcmd, u16 len)
++{
++ u16 opcode = pcmd[0] | pcmd[1] << 8;
++ u16 hci_OGF = HCI_OGF(opcode);
++ u16 hci_OCF = HCI_OCF(opcode);
++ u8 cmdlen = len - 3;
++ u8 pare_len = pcmd[2];
++
++ RTW_INFO("%s OGF: %x,OCF: %x\n", __func__, hci_OGF, hci_OCF);
++ switch (hci_OGF) {
++ case OGF_EXTENSION:
++ RTW_INFO("HCI_EXTENSION_CMD_OGF\n");
++ rtw_btcoex_parse_hci_extend_cmd(padapter, &pcmd[3], cmdlen, hci_OCF);
++ break;
++ default:
++ RTW_INFO("Other OGF: %x\n", hci_OGF);
++ break;
++ }
++}
++
++u16 rtw_btcoex_parse_recv_data(u8 *msg, u8 msg_size)
++{
++ u8 cmp_msg1[32] = attend_ack;
++ u8 cmp_msg2[32] = leave_ack;
++ u8 cmp_msg3[32] = bt_leave;
++ u8 cmp_msg4[32] = invite_req;
++ u8 cmp_msg5[32] = attend_req;
++ u8 cmp_msg6[32] = invite_rsp;
++ u8 res = OTHER;
++
++ if (_rtw_memcmp(cmp_msg1, msg, msg_size) == _TRUE) {
++ /*RTW_INFO("%s, msg:%s\n",__func__,msg);*/
++ res = RX_ATTEND_ACK;
++ } else if (_rtw_memcmp(cmp_msg2, msg, msg_size) == _TRUE) {
++ /*RTW_INFO("%s, msg:%s\n",__func__,msg);*/
++ res = RX_LEAVE_ACK;
++ } else if (_rtw_memcmp(cmp_msg3, msg, msg_size) == _TRUE) {
++ /*RTW_INFO("%s, msg:%s\n",__func__,msg);*/
++ res = RX_BT_LEAVE;
++ } else if (_rtw_memcmp(cmp_msg4, msg, msg_size) == _TRUE) {
++ /*RTW_INFO("%s, msg:%s\n",__func__,msg);*/
++ res = RX_INVITE_REQ;
++ } else if (_rtw_memcmp(cmp_msg5, msg, msg_size) == _TRUE)
++ res = RX_ATTEND_REQ;
++ else if (_rtw_memcmp(cmp_msg6, msg, msg_size) == _TRUE)
++ res = RX_INVITE_RSP;
++ else {
++ /*RTW_INFO("%s, %s\n", __func__, msg);*/
++ res = OTHER;
++ }
++
++ /*RTW_INFO("%s, res:%d\n", __func__, res);*/
++
++ return res;
++}
++
++void rtw_btcoex_recvmsgbysocket(void *data)
++{
++ u8 recv_data[255];
++ u8 tx_msg[255] = leave_ack;
++ u32 len = 0;
++ u16 recv_length = 0;
++ u16 parse_res = 0;
++#if 0
++ u8 para_len = 0, polling_enable = 0, poling_interval = 0, reason = 0, btinfo_len = 0;
++ u8 btinfo[BT_INFO_LEN] = {0};
++#endif
++
++ struct bt_coex_info *pcoex_info = NULL;
++ struct sock *sk = NULL;
++ struct sk_buff *skb = NULL;
++
++ /*RTW_INFO("%s\n",__func__);*/
++
++ if (pbtcoexadapter == NULL) {
++ RTW_INFO("%s: btcoexadapter NULL!\n", __func__);
++ return;
++ }
++
++ pcoex_info = &pbtcoexadapter->coex_info;
++ sk = pcoex_info->sk_store;
++
++ if (sk == NULL) {
++ RTW_INFO("%s: critical error when receive socket data!\n", __func__);
++ return;
++ }
++
++ len = skb_queue_len(&sk->sk_receive_queue);
++ while (len > 0) {
++ skb = skb_dequeue(&sk->sk_receive_queue);
++
++ /*important: cut the udp header from skb->data! header length is 8 byte*/
++ recv_length = skb->len - 8;
++ _rtw_memset(recv_data, 0, sizeof(recv_data));
++ _rtw_memcpy(recv_data, skb->data + 8, recv_length);
++
++ parse_res = rtw_btcoex_parse_recv_data(recv_data, recv_length);
++#if 0
++ if (RX_ATTEND_ACK == parse_res) {
++ /* attend ack */
++ pcoex_info->BT_attend = _TRUE;
++ RTW_INFO("RX_ATTEND_ACK!,sock_open:%d, BT_attend:%d\n", pcoex_info->sock_open, pcoex_info->BT_attend);
++ } else if (RX_ATTEND_REQ == parse_res) {
++ /* attend req from BT */
++ pcoex_info->BT_attend = _TRUE;
++ RTW_INFO("RX_BT_ATTEND_REQ!,sock_open:%d, BT_attend:%d\n", pcoex_info->sock_open, pcoex_info->BT_attend);
++ rtw_btcoex_sendmsgbysocket(pbtcoexadapter, attend_ack, sizeof(attend_ack), _FALSE);
++ } else if (RX_INVITE_REQ == parse_res) {
++ /* invite req from BT */
++ pcoex_info->BT_attend = _TRUE;
++ RTW_INFO("RX_INVITE_REQ!,sock_open:%d, BT_attend:%d\n", pcoex_info->sock_open, pcoex_info->BT_attend);
++ rtw_btcoex_sendmsgbysocket(pbtcoexadapter, invite_rsp, sizeof(invite_rsp), _FALSE);
++ } else if (RX_INVITE_RSP == parse_res) {
++ /* invite rsp */
++ pcoex_info->BT_attend = _TRUE;
++ RTW_INFO("RX_INVITE_RSP!,sock_open:%d, BT_attend:%d\n", pcoex_info->sock_open, pcoex_info->BT_attend);
++ } else if (RX_LEAVE_ACK == parse_res) {
++ /* mean BT know wifi will leave */
++ pcoex_info->BT_attend = _FALSE;
++ RTW_INFO("RX_LEAVE_ACK!,sock_open:%d, BT_attend:%d\n", pcoex_info->sock_open, pcoex_info->BT_attend);
++ } else if (RX_BT_LEAVE == parse_res) {
++ /* BT leave */
++ rtw_btcoex_sendmsgbysocket(pbtcoexadapter, leave_ack, sizeof(leave_ack), _FALSE); /* no ack */
++ pcoex_info->BT_attend = _FALSE;
++ RTW_INFO("RX_BT_LEAVE!sock_open:%d, BT_attend:%d\n", pcoex_info->sock_open, pcoex_info->BT_attend);
++ } else {
++ /* todo: check if recv data are really hci cmds */
++ if (_TRUE == pcoex_info->BT_attend)
++ rtw_btcoex_parse_hci_cmd(pbtcoexadapter, recv_data, recv_length);
++ }
++#endif
++ switch (parse_res) {
++ case RX_ATTEND_ACK:
++ /* attend ack */
++ pcoex_info->BT_attend = _TRUE;
++ RTW_INFO("RX_ATTEND_ACK!,sock_open:%d, BT_attend:%d\n", pcoex_info->sock_open, pcoex_info->BT_attend);
++ rtw_btcoex_pta_off_on_notify(pbtcoexadapter, pcoex_info->BT_attend);
++ break;
++
++ case RX_ATTEND_REQ:
++ pcoex_info->BT_attend = _TRUE;
++ RTW_INFO("RX_BT_ATTEND_REQ!,sock_open:%d, BT_attend:%d\n", pcoex_info->sock_open, pcoex_info->BT_attend);
++ rtw_btcoex_sendmsgbysocket(pbtcoexadapter, attend_ack, sizeof(attend_ack), _FALSE);
++ rtw_btcoex_pta_off_on_notify(pbtcoexadapter, pcoex_info->BT_attend);
++ break;
++
++ case RX_INVITE_REQ:
++ /* invite req from BT */
++ pcoex_info->BT_attend = _TRUE;
++ RTW_INFO("RX_INVITE_REQ!,sock_open:%d, BT_attend:%d\n", pcoex_info->sock_open, pcoex_info->BT_attend);
++ rtw_btcoex_sendmsgbysocket(pbtcoexadapter, invite_rsp, sizeof(invite_rsp), _FALSE);
++ rtw_btcoex_pta_off_on_notify(pbtcoexadapter, pcoex_info->BT_attend);
++ break;
++
++ case RX_INVITE_RSP:
++ /*invite rsp*/
++ pcoex_info->BT_attend = _TRUE;
++ RTW_INFO("RX_INVITE_RSP!,sock_open:%d, BT_attend:%d\n", pcoex_info->sock_open, pcoex_info->BT_attend);
++ rtw_btcoex_pta_off_on_notify(pbtcoexadapter, pcoex_info->BT_attend);
++ break;
++
++ case RX_LEAVE_ACK:
++ /* mean BT know wifi will leave */
++ pcoex_info->BT_attend = _FALSE;
++ RTW_INFO("RX_LEAVE_ACK!,sock_open:%d, BT_attend:%d\n", pcoex_info->sock_open, pcoex_info->BT_attend);
++ rtw_btcoex_pta_off_on_notify(pbtcoexadapter, pcoex_info->BT_attend);
++ break;
++
++ case RX_BT_LEAVE:
++ /* BT leave */
++ rtw_btcoex_sendmsgbysocket(pbtcoexadapter, leave_ack, sizeof(leave_ack), _FALSE); /* no ack */
++ pcoex_info->BT_attend = _FALSE;
++ RTW_INFO("RX_BT_LEAVE!sock_open:%d, BT_attend:%d\n", pcoex_info->sock_open, pcoex_info->BT_attend);
++ rtw_btcoex_pta_off_on_notify(pbtcoexadapter, pcoex_info->BT_attend);
++ break;
++
++ default:
++ if (_TRUE == pcoex_info->BT_attend)
++ rtw_btcoex_parse_hci_cmd(pbtcoexadapter, recv_data, recv_length);
++ else
++ RTW_INFO("ERROR!! BT is UP\n");
++ break;
++
++ }
++
++ len--;
++ kfree_skb(skb);
++ }
++}
++
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 15, 0))
++ void rtw_btcoex_recvmsg_init(struct sock *sk_in, s32 bytes)
++#else
++ void rtw_btcoex_recvmsg_init(struct sock *sk_in)
++#endif
++{
++ struct bt_coex_info *pcoex_info = NULL;
++
++ if (pbtcoexadapter == NULL) {
++ RTW_INFO("%s: btcoexadapter NULL\n", __func__);
++ return;
++ }
++ pcoex_info = &pbtcoexadapter->coex_info;
++ pcoex_info->sk_store = sk_in;
++ if (pcoex_info->btcoex_wq != NULL)
++ queue_delayed_work(pcoex_info->btcoex_wq, &pcoex_info->recvmsg_work, 0);
++ else
++ RTW_INFO("%s: BTCOEX workqueue NULL\n", __func__);
++}
++
++u8 rtw_btcoex_sendmsgbysocket(_adapter *padapter, u8 *msg, u8 msg_size, bool force)
++{
++ u8 error;
++ struct msghdr udpmsg;
++#ifdef set_fs
++ mm_segment_t oldfs;
++#endif
++ struct iovec iov;
++ struct bt_coex_info *pcoex_info = &padapter->coex_info;
++
++ /* RTW_INFO("%s: msg:%s, force:%s\n", __func__, msg, force == _TRUE?"TRUE":"FALSE"); */
++ if (_FALSE == force) {
++ if (_FALSE == pcoex_info->BT_attend) {
++ RTW_INFO("TX Blocked: WiFi-BT disconnected\n");
++ return _FAIL;
++ }
++ }
++
++ iov.iov_base = (void *)msg;
++ iov.iov_len = msg_size;
++ udpmsg.msg_name = &pcoex_info->bt_sockaddr;
++ udpmsg.msg_namelen = sizeof(struct sockaddr_in);
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 19, 0))
++ /* referece:sock_xmit in kernel code
++ * WRITE for sock_sendmsg, READ for sock_recvmsg
++ * third parameter for msg_iovlen
++ * last parameter for iov_len
++ */
++ iov_iter_init(&udpmsg.msg_iter, WRITE, &iov, 1, msg_size);
++#else
++ udpmsg.msg_iov = &iov;
++ udpmsg.msg_iovlen = 1;
++#endif
++ udpmsg.msg_control = NULL;
++ udpmsg.msg_controllen = 0;
++ udpmsg.msg_flags = MSG_DONTWAIT | MSG_NOSIGNAL;
++#ifdef set_fs
++ oldfs = get_fs();
++ set_fs(KERNEL_DS);
++#endif
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 1, 0))
++ error = sock_sendmsg(pcoex_info->udpsock, &udpmsg);
++#else
++ error = sock_sendmsg(pcoex_info->udpsock, &udpmsg, msg_size);
++#endif
++#ifdef set_fs
++ set_fs(oldfs);
++#endif
++ if (error < 0) {
++ RTW_INFO("Error when sendimg msg, error:%d\n", error);
++ return _FAIL;
++ } else
++ return _SUCCESS;
++}
++
++u8 rtw_btcoex_create_kernel_socket(_adapter *padapter)
++{
++ s8 kernel_socket_err;
++ u8 tx_msg[255] = attend_req;
++ struct bt_coex_info *pcoex_info = &padapter->coex_info;
++ s32 sock_reuse = 1;
++ u8 status = _FAIL;
++
++ RTW_INFO("%s CONNECT_PORT %d\n", __func__, CONNECT_PORT);
++
++ if (NULL == pcoex_info) {
++ RTW_INFO("coex_info: NULL\n");
++ status = _FAIL;
++ }
++
++ kernel_socket_err = sock_create(PF_INET, SOCK_DGRAM, 0, &pcoex_info->udpsock);
++
++ if (kernel_socket_err < 0) {
++ RTW_INFO("Error during creation of socket error:%d\n", kernel_socket_err);
++ status = _FAIL;
++ } else {
++ _rtw_memset(&(pcoex_info->wifi_sockaddr), 0, sizeof(pcoex_info->wifi_sockaddr));
++ pcoex_info->wifi_sockaddr.sin_family = AF_INET;
++ pcoex_info->wifi_sockaddr.sin_port = htons(CONNECT_PORT);
++ pcoex_info->wifi_sockaddr.sin_addr.s_addr = htonl(INADDR_LOOPBACK);
++
++ _rtw_memset(&(pcoex_info->bt_sockaddr), 0, sizeof(pcoex_info->bt_sockaddr));
++ pcoex_info->bt_sockaddr.sin_family = AF_INET;
++ pcoex_info->bt_sockaddr.sin_port = htons(CONNECT_PORT_BT);
++ pcoex_info->bt_sockaddr.sin_addr.s_addr = htonl(INADDR_LOOPBACK);
++
++ pcoex_info->sk_store = NULL;
++ kernel_socket_err = pcoex_info->udpsock->ops->bind(pcoex_info->udpsock, (struct sockaddr *)&pcoex_info->wifi_sockaddr,
++ sizeof(pcoex_info->wifi_sockaddr));
++ if (kernel_socket_err == 0) {
++ RTW_INFO("binding socket success\n");
++ pcoex_info->udpsock->sk->sk_data_ready = rtw_btcoex_recvmsg_init;
++ pcoex_info->sock_open |= KERNEL_SOCKET_OK;
++ pcoex_info->BT_attend = _FALSE;
++ RTW_INFO("WIFI sending attend_req\n");
++ rtw_btcoex_sendmsgbysocket(padapter, attend_req, sizeof(attend_req), _TRUE);
++ status = _SUCCESS;
++ } else {
++ pcoex_info->BT_attend = _FALSE;
++ sock_release(pcoex_info->udpsock); /* bind fail release socket */
++ RTW_INFO("Error binding socket: %d\n", kernel_socket_err);
++ status = _FAIL;
++ }
++
++ }
++
++ return status;
++}
++
++void rtw_btcoex_close_kernel_socket(_adapter *padapter)
++{
++ struct bt_coex_info *pcoex_info = &padapter->coex_info;
++ if (pcoex_info->sock_open & KERNEL_SOCKET_OK) {
++ RTW_INFO("release kernel socket\n");
++ sock_release(pcoex_info->udpsock);
++ pcoex_info->sock_open &= ~(KERNEL_SOCKET_OK);
++ if (_TRUE == pcoex_info->BT_attend)
++ pcoex_info->BT_attend = _FALSE;
++
++ RTW_INFO("sock_open:%d, BT_attend:%d\n", pcoex_info->sock_open, pcoex_info->BT_attend);
++ }
++}
++
++void rtw_btcoex_init_socket(_adapter *padapter)
++{
++
++ u8 is_invite = _FALSE;
++ struct bt_coex_info *pcoex_info = &padapter->coex_info;
++ RTW_INFO("%s\n", __func__);
++ if (_FALSE == pcoex_info->is_exist) {
++ _rtw_memset(pcoex_info, 0, sizeof(struct bt_coex_info));
++ pcoex_info->btcoex_wq = create_workqueue("BTCOEX");
++ INIT_DELAYED_WORK(&pcoex_info->recvmsg_work,
++ (void *)rtw_btcoex_recvmsgbysocket);
++ pbtcoexadapter = padapter;
++ /* We expect BT is off if BT don't send ack to wifi */
++ RTW_INFO("We expect BT is off if BT send ack to wifi\n");
++ rtw_btcoex_pta_off_on_notify(pbtcoexadapter, _FALSE);
++ if (rtw_btcoex_create_kernel_socket(padapter) == _SUCCESS)
++ pcoex_info->is_exist = _TRUE;
++ else {
++ pcoex_info->is_exist = _FALSE;
++ pbtcoexadapter = NULL;
++ }
++
++ RTW_INFO("%s: pbtcoexadapter:%p, coex_info->is_exist: %s\n"
++ , __func__, pbtcoexadapter, pcoex_info->is_exist == _TRUE ? "TRUE" : "FALSE");
++ }
++}
++
++void rtw_btcoex_close_socket(_adapter *padapter)
++{
++ struct bt_coex_info *pcoex_info = &padapter->coex_info;
++
++ RTW_INFO("%s--coex_info->is_exist: %s, pcoex_info->BT_attend:%s\n"
++ , __func__, pcoex_info->is_exist == _TRUE ? "TRUE" : "FALSE", pcoex_info->BT_attend == _TRUE ? "TRUE" : "FALSE");
++
++ if (_TRUE == pcoex_info->is_exist) {
++ if (_TRUE == pcoex_info->BT_attend) {
++ /*inform BT wifi leave*/
++ rtw_btcoex_sendmsgbysocket(padapter, wifi_leave, sizeof(wifi_leave), _FALSE);
++ msleep(50);
++ }
++
++ if (pcoex_info->btcoex_wq != NULL) {
++ flush_workqueue(pcoex_info->btcoex_wq);
++ destroy_workqueue(pcoex_info->btcoex_wq);
++ }
++
++ rtw_btcoex_close_kernel_socket(padapter);
++ pbtcoexadapter = NULL;
++ pcoex_info->is_exist = _FALSE;
++ }
++}
++
++void rtw_btcoex_dump_tx_msg(u8 *tx_msg, u8 len, u8 *msg_name)
++{
++ u8 i = 0;
++ RTW_INFO("======> Msg name: %s\n", msg_name);
++ for (i = 0; i < len; i++)
++ printk("%02x ", tx_msg[i]);
++ printk("\n");
++ RTW_INFO("Msg name: %s <======\n", msg_name);
++}
++
++/* Porting from Windows team */
++void rtw_btcoex_SendEventExtBtCoexControl(PADAPTER padapter, u8 bNeedDbgRsp, u8 dataLen, void *pData)
++{
++ u8 len = 0, tx_event_length = 0;
++ u8 localBuf[32] = "";
++ u8 *pRetPar;
++ u8 opCode = 0;
++ u8 *pInBuf = (pu1Byte)pData;
++ u8 *pOpCodeContent;
++ rtw_HCI_event *pEvent;
++
++ opCode = pInBuf[0];
++
++ RTW_INFO("%s, OPCode:%02x\n", __func__, opCode);
++
++ pEvent = (rtw_HCI_event *)(&localBuf[0]);
++
++ /* len += bthci_ExtensionEventHeaderRtk(&localBuf[0], */
++ /* HCI_EVENT_EXT_BT_COEX_CONTROL); */
++ pEvent->EventCode = HCI_EVENT_EXTENSION_RTK;
++ pEvent->Data[0] = HCI_EVENT_EXT_BT_COEX_CONTROL; /* extension event code */
++ len++;
++
++ /* Return parameters starts from here */
++ pRetPar = &pEvent->Data[len];
++ _rtw_memcpy(&pRetPar[0], pData, dataLen);
++
++ len += dataLen;
++
++ pEvent->Length = len;
++
++ /* total tx event length + EventCode length + sizeof(length) */
++ tx_event_length = pEvent->Length + 2;
++#if 0
++ rtw_btcoex_dump_tx_msg((u8 *)pEvent, tx_event_length, "BT COEX CONTROL", _FALSE);
++#endif
++ rtw_btcoex_sendmsgbysocket(padapter, (u8 *)pEvent, tx_event_length, _FALSE);
++
++}
++
++/* Porting from Windows team */
++void rtw_btcoex_SendEventExtBtInfoControl(PADAPTER padapter, u8 dataLen, void *pData)
++{
++ rtw_HCI_event *pEvent;
++ u8 *pRetPar;
++ u8 len = 0, tx_event_length = 0;
++ u8 localBuf[32] = "";
++
++ struct bt_coex_info *pcoex_info = &padapter->coex_info;
++ PBT_MGNT pBtMgnt = &pcoex_info->BtMgnt;
++
++ /* RTW_INFO("%s\n",__func__);*/
++ if (pBtMgnt->ExtConfig.HCIExtensionVer < 4) { /* not support */
++ RTW_INFO("ERROR: HCIExtensionVer = %d, HCIExtensionVer<4 !!!!\n", pBtMgnt->ExtConfig.HCIExtensionVer);
++ return;
++ }
++
++ pEvent = (rtw_HCI_event *)(&localBuf[0]);
++
++ /* len += bthci_ExtensionEventHeaderRtk(&localBuf[0], */
++ /* HCI_EVENT_EXT_BT_INFO_CONTROL); */
++ pEvent->EventCode = HCI_EVENT_EXTENSION_RTK;
++ pEvent->Data[0] = HCI_EVENT_EXT_BT_INFO_CONTROL; /* extension event code */
++ len++;
++
++ /* Return parameters starts from here */
++ pRetPar = &pEvent->Data[len];
++ _rtw_memcpy(&pRetPar[0], pData, dataLen);
++
++ len += dataLen;
++
++ pEvent->Length = len;
++
++ /* total tx event length + EventCode length + sizeof(length) */
++ tx_event_length = pEvent->Length + 2;
++#if 0
++ rtw_btcoex_dump_tx_msg((u8 *)pEvent, tx_event_length, "BT INFO CONTROL");
++#endif
++ rtw_btcoex_sendmsgbysocket(padapter, (u8 *)pEvent, tx_event_length, _FALSE);
++
++}
++
++void rtw_btcoex_SendScanNotify(PADAPTER padapter, u8 scanType)
++{
++ u8 len = 0, tx_event_length = 0;
++ u8 localBuf[7] = "";
++ u8 *pRetPar;
++ u8 *pu1Temp;
++ rtw_HCI_event *pEvent;
++ struct bt_coex_info *pcoex_info = &padapter->coex_info;
++ PBT_MGNT pBtMgnt = &pcoex_info->BtMgnt;
++
++ /* if(!pBtMgnt->BtOperationOn)
++ * return; */
++
++ pEvent = (rtw_HCI_event *)(&localBuf[0]);
++
++ /* len += bthci_ExtensionEventHeaderRtk(&localBuf[0],
++ * HCI_EVENT_EXT_WIFI_SCAN_NOTIFY); */
++
++ pEvent->EventCode = HCI_EVENT_EXTENSION_RTK;
++ pEvent->Data[0] = HCI_EVENT_EXT_WIFI_SCAN_NOTIFY; /* extension event code */
++ len++;
++
++ /* Return parameters starts from here */
++ /* pRetPar = &PPacketIrpEvent->Data[len]; */
++ /* pu1Temp = (u8 *)&pRetPar[0]; */
++ /* *pu1Temp = scanType; */
++ pEvent->Data[len] = scanType;
++ len += 1;
++
++ pEvent->Length = len;
++
++ /* total tx event length + EventCode length + sizeof(length) */
++ tx_event_length = pEvent->Length + 2;
++#if 0
++ rtw_btcoex_dump_tx_msg((u8 *)pEvent, tx_event_length, "WIFI SCAN OPERATION");
++#endif
++ rtw_btcoex_sendmsgbysocket(padapter, (u8 *)pEvent, tx_event_length, _FALSE);
++}
++#endif /* CONFIG_BT_COEXIST_SOCKET_TRX */
++#endif /* CONFIG_BT_COEXIST */
++
++void rtw_btcoex_set_ant_info(PADAPTER padapter)
++{
++#ifdef CONFIG_BT_COEXIST
++ PHAL_DATA_TYPE hal = GET_HAL_DATA(padapter);
++
++ if (hal->EEPROMBluetoothCoexist == _TRUE) {
++ u8 bMacPwrCtrlOn = _FALSE;
++
++ rtw_btcoex_AntInfoSetting(padapter);
++ rtw_hal_get_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);
++ if (bMacPwrCtrlOn == _TRUE)
++ rtw_btcoex_PowerOnSetting(padapter);
++ }
++ else
++#endif
++ rtw_btcoex_wifionly_AntInfoSetting(padapter);
++}
++
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/core/rtw_btcoex_wifionly.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/core/rtw_btcoex_wifionly.c
+--- linux-5.11.4/3rdparty/rtl8812au/core/rtw_btcoex_wifionly.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/core/rtw_btcoex_wifionly.c 2021-03-07 18:16:17.018954351 +0200
+@@ -0,0 +1,47 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2013 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#include
++#include
++#include
++
++void rtw_btcoex_wifionly_switchband_notify(PADAPTER padapter)
++{
++ hal_btcoex_wifionly_switchband_notify(padapter);
++}
++
++void rtw_btcoex_wifionly_scan_notify(PADAPTER padapter)
++{
++ hal_btcoex_wifionly_scan_notify(padapter);
++}
++
++void rtw_btcoex_wifionly_connect_notify(PADAPTER padapter)
++{
++ hal_btcoex_wifionly_connect_notify(padapter);
++}
++
++void rtw_btcoex_wifionly_hw_config(PADAPTER padapter)
++{
++ hal_btcoex_wifionly_hw_config(padapter);
++}
++
++void rtw_btcoex_wifionly_initialize(PADAPTER padapter)
++{
++ hal_btcoex_wifionly_initlizevariables(padapter);
++}
++
++void rtw_btcoex_wifionly_AntInfoSetting(PADAPTER padapter)
++{
++ hal_btcoex_wifionly_AntInfoSetting(padapter);
++}
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/core/rtw_bt_mp.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/core/rtw_bt_mp.c
+--- linux-5.11.4/3rdparty/rtl8812au/core/rtw_bt_mp.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/core/rtw_bt_mp.c 2021-03-07 18:16:17.017954304 +0200
@@ -0,0 +1,1575 @@
+/******************************************************************************
+ *
@@ -25815,1832 +24713,9 @@ index 000000000..9b4fc2432
+}
+
+#endif
-diff --git linux-5.8/3rdparty/rtl8812au/core/rtw_btcoex.c linux-5.8/3rdparty/rtl8812au/core/rtw_btcoex.c
-new file mode 100644
-index 000000000..d5b89bdc3
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/core/rtw_btcoex.c
-@@ -0,0 +1,1762 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2013 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#include
-+#include
-+#ifdef CONFIG_BT_COEXIST
-+#include
-+
-+void rtw_btcoex_Initialize(PADAPTER padapter)
-+{
-+ hal_btcoex_Initialize(padapter);
-+}
-+
-+void rtw_btcoex_PowerOnSetting(PADAPTER padapter)
-+{
-+ hal_btcoex_PowerOnSetting(padapter);
-+}
-+
-+void rtw_btcoex_AntInfoSetting(PADAPTER padapter)
-+{
-+ hal_btcoex_AntInfoSetting(padapter);
-+}
-+
-+void rtw_btcoex_PowerOffSetting(PADAPTER padapter)
-+{
-+ hal_btcoex_PowerOffSetting(padapter);
-+}
-+
-+void rtw_btcoex_PreLoadFirmware(PADAPTER padapter)
-+{
-+ hal_btcoex_PreLoadFirmware(padapter);
-+}
-+
-+void rtw_btcoex_HAL_Initialize(PADAPTER padapter, u8 bWifiOnly)
-+{
-+ hal_btcoex_InitHwConfig(padapter, bWifiOnly);
-+}
-+
-+void rtw_btcoex_IpsNotify(PADAPTER padapter, u8 type)
-+{
-+ PHAL_DATA_TYPE pHalData;
-+
-+ pHalData = GET_HAL_DATA(padapter);
-+ if (_FALSE == pHalData->EEPROMBluetoothCoexist)
-+ return;
-+
-+ hal_btcoex_IpsNotify(padapter, type);
-+}
-+
-+void rtw_btcoex_LpsNotify(PADAPTER padapter, u8 type)
-+{
-+ PHAL_DATA_TYPE pHalData;
-+
-+ pHalData = GET_HAL_DATA(padapter);
-+ if (_FALSE == pHalData->EEPROMBluetoothCoexist)
-+ return;
-+
-+ hal_btcoex_LpsNotify(padapter, type);
-+}
-+
-+void rtw_btcoex_ScanNotify(PADAPTER padapter, u8 type)
-+{
-+ PHAL_DATA_TYPE pHalData;
-+#ifdef CONFIG_BT_COEXIST_SOCKET_TRX
-+ struct bt_coex_info *pcoex_info = &padapter->coex_info;
-+ PBT_MGNT pBtMgnt = &pcoex_info->BtMgnt;
-+#endif /* CONFIG_BT_COEXIST_SOCKET_TRX */
-+
-+ pHalData = GET_HAL_DATA(padapter);
-+ if (_FALSE == pHalData->EEPROMBluetoothCoexist)
-+ return;
-+
-+ if (_FALSE == type) {
-+ #ifdef CONFIG_CONCURRENT_MODE
-+ if (rtw_mi_buddy_check_fwstate(padapter, WIFI_SITE_MONITOR))
-+ return;
-+ #endif
-+
-+ if (DEV_MGMT_TX_NUM(adapter_to_dvobj(padapter))
-+ || DEV_ROCH_NUM(adapter_to_dvobj(padapter)))
-+ return;
-+ }
-+
-+#ifdef CONFIG_BT_COEXIST_SOCKET_TRX
-+ if (pBtMgnt->ExtConfig.bEnableWifiScanNotify)
-+ rtw_btcoex_SendScanNotify(padapter, type);
-+#endif /* CONFIG_BT_COEXIST_SOCKET_TRX */
-+
-+ hal_btcoex_ScanNotify(padapter, type);
-+}
-+
-+void rtw_btcoex_ConnectNotify(PADAPTER padapter, u8 action)
-+{
-+ PHAL_DATA_TYPE pHalData;
-+
-+ pHalData = GET_HAL_DATA(padapter);
-+ if (_FALSE == pHalData->EEPROMBluetoothCoexist)
-+ return;
-+
-+#ifdef DBG_CONFIG_ERROR_RESET
-+ if (_TRUE == rtw_hal_sreset_inprogress(padapter)) {
-+ RTW_INFO(FUNC_ADPT_FMT ": [BTCoex] under reset, skip notify!\n",
-+ FUNC_ADPT_ARG(padapter));
-+ return;
-+ }
-+#endif /* DBG_CONFIG_ERROR_RESET */
-+
-+#ifdef CONFIG_CONCURRENT_MODE
-+ if (_FALSE == action) {
-+ if (rtw_mi_buddy_check_fwstate(padapter, WIFI_UNDER_LINKING))
-+ return;
-+ }
-+#endif
-+
-+ hal_btcoex_ConnectNotify(padapter, action);
-+}
-+
-+void rtw_btcoex_MediaStatusNotify(PADAPTER padapter, u8 mediaStatus)
-+{
-+ PHAL_DATA_TYPE pHalData;
-+
-+ pHalData = GET_HAL_DATA(padapter);
-+ if (_FALSE == pHalData->EEPROMBluetoothCoexist)
-+ return;
-+
-+#ifdef DBG_CONFIG_ERROR_RESET
-+ if (_TRUE == rtw_hal_sreset_inprogress(padapter)) {
-+ RTW_INFO(FUNC_ADPT_FMT ": [BTCoex] under reset, skip notify!\n",
-+ FUNC_ADPT_ARG(padapter));
-+ return;
-+ }
-+#endif /* DBG_CONFIG_ERROR_RESET */
-+
-+#ifdef CONFIG_CONCURRENT_MODE
-+ if (RT_MEDIA_DISCONNECT == mediaStatus) {
-+ if (rtw_mi_buddy_check_fwstate(padapter, WIFI_ASOC_STATE))
-+ return;
-+ }
-+#endif /* CONFIG_CONCURRENT_MODE */
-+
-+ if ((RT_MEDIA_CONNECT == mediaStatus)
-+ && (check_fwstate(&padapter->mlmepriv, WIFI_AP_STATE) == _TRUE))
-+ rtw_hal_set_hwreg(padapter, HW_VAR_DL_RSVD_PAGE, NULL);
-+
-+ hal_btcoex_MediaStatusNotify(padapter, mediaStatus);
-+}
-+
-+void rtw_btcoex_SpecialPacketNotify(PADAPTER padapter, u8 pktType)
-+{
-+ PHAL_DATA_TYPE pHalData;
-+
-+ pHalData = GET_HAL_DATA(padapter);
-+ if (_FALSE == pHalData->EEPROMBluetoothCoexist)
-+ return;
-+
-+ hal_btcoex_SpecialPacketNotify(padapter, pktType);
-+}
-+
-+void rtw_btcoex_IQKNotify(PADAPTER padapter, u8 state)
-+{
-+ PHAL_DATA_TYPE pHalData;
-+
-+ pHalData = GET_HAL_DATA(padapter);
-+ if (_FALSE == pHalData->EEPROMBluetoothCoexist)
-+ return;
-+
-+ hal_btcoex_IQKNotify(padapter, state);
-+}
-+
-+void rtw_btcoex_BtInfoNotify(PADAPTER padapter, u8 length, u8 *tmpBuf)
-+{
-+ PHAL_DATA_TYPE pHalData;
-+
-+ pHalData = GET_HAL_DATA(padapter);
-+ if (_FALSE == pHalData->EEPROMBluetoothCoexist)
-+ return;
-+
-+ hal_btcoex_BtInfoNotify(padapter, length, tmpBuf);
-+}
-+
-+void rtw_btcoex_BtMpRptNotify(PADAPTER padapter, u8 length, u8 *tmpBuf)
-+{
-+ PHAL_DATA_TYPE pHalData;
-+
-+ pHalData = GET_HAL_DATA(padapter);
-+ if (_FALSE == pHalData->EEPROMBluetoothCoexist)
-+ return;
-+
-+ if (padapter->registrypriv.mp_mode == 1)
-+ return;
-+
-+ hal_btcoex_BtMpRptNotify(padapter, length, tmpBuf);
-+}
-+
-+void rtw_btcoex_SuspendNotify(PADAPTER padapter, u8 state)
-+{
-+ PHAL_DATA_TYPE pHalData;
-+
-+ pHalData = GET_HAL_DATA(padapter);
-+ if (_FALSE == pHalData->EEPROMBluetoothCoexist)
-+ return;
-+
-+ hal_btcoex_SuspendNotify(padapter, state);
-+}
-+
-+void rtw_btcoex_HaltNotify(PADAPTER padapter)
-+{
-+ PHAL_DATA_TYPE pHalData;
-+ u8 do_halt = 1;
-+
-+ pHalData = GET_HAL_DATA(padapter);
-+ if (_FALSE == pHalData->EEPROMBluetoothCoexist)
-+ do_halt = 0;
-+
-+ if (_FALSE == padapter->bup) {
-+ RTW_INFO(FUNC_ADPT_FMT ": bup=%d Skip!\n",
-+ FUNC_ADPT_ARG(padapter), padapter->bup);
-+ do_halt = 0;
-+ }
-+
-+ if (rtw_is_surprise_removed(padapter)) {
-+ RTW_INFO(FUNC_ADPT_FMT ": bSurpriseRemoved=%s Skip!\n",
-+ FUNC_ADPT_ARG(padapter), rtw_is_surprise_removed(padapter) ? "True" : "False");
-+ do_halt = 0;
-+ }
-+
-+ hal_btcoex_HaltNotify(padapter, do_halt);
-+}
-+
-+void rtw_btcoex_switchband_notify(u8 under_scan, u8 band_type)
-+{
-+ hal_btcoex_switchband_notify(under_scan, band_type);
-+}
-+
-+void rtw_btcoex_WlFwDbgInfoNotify(PADAPTER padapter, u8* tmpBuf, u8 length)
-+{
-+ hal_btcoex_WlFwDbgInfoNotify(padapter, tmpBuf, length);
-+}
-+
-+void rtw_btcoex_rx_rate_change_notify(PADAPTER padapter, u8 is_data_frame, u8 rate_id)
-+{
-+ hal_btcoex_rx_rate_change_notify(padapter, is_data_frame, rate_id);
-+}
-+
-+void rtw_btcoex_SwitchBtTRxMask(PADAPTER padapter)
-+{
-+ hal_btcoex_SwitchBtTRxMask(padapter);
-+}
-+
-+void rtw_btcoex_Switch(PADAPTER padapter, u8 enable)
-+{
-+ hal_btcoex_SetBTCoexist(padapter, enable);
-+}
-+
-+u8 rtw_btcoex_IsBtDisabled(PADAPTER padapter)
-+{
-+ return hal_btcoex_IsBtDisabled(padapter);
-+}
-+
-+void rtw_btcoex_Handler(PADAPTER padapter)
-+{
-+ PHAL_DATA_TYPE pHalData;
-+
-+ pHalData = GET_HAL_DATA(padapter);
-+
-+ if (_FALSE == pHalData->EEPROMBluetoothCoexist)
-+ return;
-+
-+ hal_btcoex_Hanlder(padapter);
-+}
-+
-+s32 rtw_btcoex_IsBTCoexRejectAMPDU(PADAPTER padapter)
-+{
-+ s32 coexctrl;
-+
-+ coexctrl = hal_btcoex_IsBTCoexRejectAMPDU(padapter);
-+
-+ return coexctrl;
-+}
-+
-+s32 rtw_btcoex_IsBTCoexCtrlAMPDUSize(PADAPTER padapter)
-+{
-+ s32 coexctrl;
-+
-+ coexctrl = hal_btcoex_IsBTCoexCtrlAMPDUSize(padapter);
-+
-+ return coexctrl;
-+}
-+
-+u32 rtw_btcoex_GetAMPDUSize(PADAPTER padapter)
-+{
-+ u32 size;
-+
-+ size = hal_btcoex_GetAMPDUSize(padapter);
-+
-+ return size;
-+}
-+
-+void rtw_btcoex_SetManualControl(PADAPTER padapter, u8 manual)
-+{
-+ if (_TRUE == manual)
-+ hal_btcoex_SetManualControl(padapter, _TRUE);
-+ else
-+ hal_btcoex_SetManualControl(padapter, _FALSE);
-+}
-+
-+u8 rtw_btcoex_1Ant(PADAPTER padapter)
-+{
-+ return hal_btcoex_1Ant(padapter);
-+}
-+
-+u8 rtw_btcoex_IsBtControlLps(PADAPTER padapter)
-+{
-+ return hal_btcoex_IsBtControlLps(padapter);
-+}
-+
-+u8 rtw_btcoex_IsLpsOn(PADAPTER padapter)
-+{
-+ return hal_btcoex_IsLpsOn(padapter);
-+}
-+
-+u8 rtw_btcoex_RpwmVal(PADAPTER padapter)
-+{
-+ return hal_btcoex_RpwmVal(padapter);
-+}
-+
-+u8 rtw_btcoex_LpsVal(PADAPTER padapter)
-+{
-+ return hal_btcoex_LpsVal(padapter);
-+}
-+
-+u32 rtw_btcoex_GetRaMask(PADAPTER padapter)
-+{
-+ return hal_btcoex_GetRaMask(padapter);
-+}
-+
-+void rtw_btcoex_RecordPwrMode(PADAPTER padapter, u8 *pCmdBuf, u8 cmdLen)
-+{
-+ hal_btcoex_RecordPwrMode(padapter, pCmdBuf, cmdLen);
-+}
-+
-+void rtw_btcoex_DisplayBtCoexInfo(PADAPTER padapter, u8 *pbuf, u32 bufsize)
-+{
-+ hal_btcoex_DisplayBtCoexInfo(padapter, pbuf, bufsize);
-+}
-+
-+void rtw_btcoex_SetDBG(PADAPTER padapter, u32 *pDbgModule)
-+{
-+ hal_btcoex_SetDBG(padapter, pDbgModule);
-+}
-+
-+u32 rtw_btcoex_GetDBG(PADAPTER padapter, u8 *pStrBuf, u32 bufSize)
-+{
-+ return hal_btcoex_GetDBG(padapter, pStrBuf, bufSize);
-+}
-+
-+u8 rtw_btcoex_IncreaseScanDeviceNum(PADAPTER padapter)
-+{
-+ return hal_btcoex_IncreaseScanDeviceNum(padapter);
-+}
-+
-+u8 rtw_btcoex_IsBtLinkExist(PADAPTER padapter)
-+{
-+ return hal_btcoex_IsBtLinkExist(padapter);
-+}
-+
-+void rtw_btcoex_SetBtPatchVersion(PADAPTER padapter, u16 btHciVer, u16 btPatchVer)
-+{
-+ hal_btcoex_SetBtPatchVersion(padapter, btHciVer, btPatchVer);
-+}
-+
-+void rtw_btcoex_SetHciVersion(PADAPTER padapter, u16 hciVersion)
-+{
-+ hal_btcoex_SetHciVersion(padapter, hciVersion);
-+}
-+
-+void rtw_btcoex_StackUpdateProfileInfo(void)
-+{
-+ hal_btcoex_StackUpdateProfileInfo();
-+}
-+
-+void rtw_btcoex_pta_off_on_notify(PADAPTER padapter, u8 bBTON)
-+{
-+ hal_btcoex_pta_off_on_notify(padapter, bBTON);
-+}
-+
-+#ifdef CONFIG_RF4CE_COEXIST
-+void rtw_btcoex_SetRf4ceLinkState(PADAPTER padapter, u8 state)
-+{
-+ hal_btcoex_set_rf4ce_link_state(state);
-+}
-+
-+u8 rtw_btcoex_GetRf4ceLinkState(PADAPTER padapter)
-+{
-+ return hal_btcoex_get_rf4ce_link_state();
-+}
-+#endif
-+
-+/* ==================================================
-+ * Below Functions are called by BT-Coex
-+ * ================================================== */
-+void rtw_btcoex_rx_ampdu_apply(PADAPTER padapter)
-+{
-+ rtw_rx_ampdu_apply(padapter);
-+}
-+
-+void rtw_btcoex_LPS_Enter(PADAPTER padapter)
-+{
-+ struct pwrctrl_priv *pwrpriv;
-+ u8 lpsVal;
-+
-+
-+ pwrpriv = adapter_to_pwrctl(padapter);
-+
-+ pwrpriv->bpower_saving = _TRUE;
-+ lpsVal = rtw_btcoex_LpsVal(padapter);
-+ rtw_set_ps_mode(padapter, PS_MODE_MIN, 0, lpsVal, "BTCOEX");
-+}
-+
-+u8 rtw_btcoex_LPS_Leave(PADAPTER padapter)
-+{
-+ struct pwrctrl_priv *pwrpriv;
-+
-+
-+ pwrpriv = adapter_to_pwrctl(padapter);
-+
-+ if (pwrpriv->pwr_mode != PS_MODE_ACTIVE) {
-+ rtw_set_ps_mode(padapter, PS_MODE_ACTIVE, 0, 0, "BTCOEX");
-+ pwrpriv->bpower_saving = _FALSE;
-+ }
-+
-+ return _TRUE;
-+}
-+
-+u16 rtw_btcoex_btreg_read(PADAPTER padapter, u8 type, u16 addr, u32 *data)
-+{
-+ return hal_btcoex_btreg_read(padapter, type, addr, data);
-+}
-+
-+u16 rtw_btcoex_btreg_write(PADAPTER padapter, u8 type, u16 addr, u16 val)
-+{
-+ return hal_btcoex_btreg_write(padapter, type, addr, val);
-+}
-+
-+u8 rtw_btcoex_get_bt_coexist(PADAPTER padapter)
-+{
-+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
-+
-+ return pHalData->EEPROMBluetoothCoexist;
-+}
-+
-+u8 rtw_btcoex_get_chip_type(PADAPTER padapter)
-+{
-+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
-+
-+ return pHalData->EEPROMBluetoothType;
-+}
-+
-+u8 rtw_btcoex_get_pg_ant_num(PADAPTER padapter)
-+{
-+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
-+
-+ return pHalData->EEPROMBluetoothAntNum == Ant_x2 ? 2 : 1;
-+}
-+
-+u8 rtw_btcoex_get_pg_single_ant_path(PADAPTER padapter)
-+{
-+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
-+
-+ return pHalData->ant_path;
-+}
-+
-+u8 rtw_btcoex_get_pg_rfe_type(PADAPTER padapter)
-+{
-+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
-+
-+ return pHalData->rfe_type;
-+}
-+
-+u8 rtw_btcoex_is_tfbga_package_type(PADAPTER padapter)
-+{
-+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
-+
-+#ifdef CONFIG_RTL8723B
-+ if ((pHalData->PackageType == PACKAGE_TFBGA79) || (pHalData->PackageType == PACKAGE_TFBGA80)
-+ || (pHalData->PackageType == PACKAGE_TFBGA90))
-+ return _TRUE;
-+#endif
-+
-+ return _FALSE;
-+}
-+
-+u8 rtw_btcoex_get_ant_div_cfg(PADAPTER padapter)
-+{
-+ PHAL_DATA_TYPE pHalData;
-+
-+ pHalData = GET_HAL_DATA(padapter);
-+
-+ return (pHalData->AntDivCfg == 0) ? _FALSE : _TRUE;
-+}
-+
-+/* ==================================================
-+ * Below Functions are BT-Coex socket related function
-+ * ================================================== */
-+
-+#ifdef CONFIG_BT_COEXIST_SOCKET_TRX
-+_adapter *pbtcoexadapter; /* = NULL; */ /* do not initialise globals to 0 or NULL */
-+u8 rtw_btcoex_btinfo_cmd(_adapter *adapter, u8 *buf, u16 len)
-+{
-+ struct cmd_obj *ph2c;
-+ struct drvextra_cmd_parm *pdrvextra_cmd_parm;
-+ u8 *btinfo;
-+ struct cmd_priv *pcmdpriv = &adapter->cmdpriv;
-+ u8 res = _SUCCESS;
-+
-+ ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
-+ if (ph2c == NULL) {
-+ res = _FAIL;
-+ goto exit;
-+ }
-+
-+ pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));
-+ if (pdrvextra_cmd_parm == NULL) {
-+ rtw_mfree((u8 *)ph2c, sizeof(struct cmd_obj));
-+ res = _FAIL;
-+ goto exit;
-+ }
-+
-+ btinfo = rtw_zmalloc(len);
-+ if (btinfo == NULL) {
-+ rtw_mfree((u8 *)ph2c, sizeof(struct cmd_obj));
-+ rtw_mfree((u8 *)pdrvextra_cmd_parm, sizeof(struct drvextra_cmd_parm));
-+ res = _FAIL;
-+ goto exit;
-+ }
-+
-+ pdrvextra_cmd_parm->ec_id = BTINFO_WK_CID;
-+ pdrvextra_cmd_parm->type = 0;
-+ pdrvextra_cmd_parm->size = len;
-+ pdrvextra_cmd_parm->pbuf = btinfo;
-+
-+ _rtw_memcpy(btinfo, buf, len);
-+
-+ init_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, GEN_CMD_CODE(_Set_Drv_Extra));
-+
-+ res = rtw_enqueue_cmd(pcmdpriv, ph2c);
-+
-+exit:
-+ return res;
-+}
-+
-+u8 rtw_btcoex_send_event_to_BT(_adapter *padapter, u8 status, u8 event_code, u8 opcode_low, u8 opcode_high, u8 *dbg_msg)
-+{
-+ u8 localBuf[6] = "";
-+ u8 *pRetPar;
-+ u8 len = 0, tx_event_length = 0;
-+ rtw_HCI_event *pEvent;
-+
-+ pEvent = (rtw_HCI_event *)(&localBuf[0]);
-+
-+ pEvent->EventCode = event_code;
-+ pEvent->Data[0] = 0x1; /* packet # */
-+ pEvent->Data[1] = opcode_low;
-+ pEvent->Data[2] = opcode_high;
-+ len = len + 3;
-+
-+ /* Return parameters starts from here */
-+ pRetPar = &pEvent->Data[len];
-+ pRetPar[0] = status; /* status */
-+
-+ len++;
-+ pEvent->Length = len;
-+
-+ /* total tx event length + EventCode length + sizeof(length) */
-+ tx_event_length = pEvent->Length + 2;
-+#if 0
-+ rtw_btcoex_dump_tx_msg((u8 *)pEvent, tx_event_length, dbg_msg);
-+#endif
-+ status = rtw_btcoex_sendmsgbysocket(padapter, (u8 *)pEvent, tx_event_length, _FALSE);
-+
-+ return status;
-+}
-+
-+/*
-+Ref:
-+Realtek Wi-Fi Driver
-+Host Controller Interface for
-+Bluetooth 3.0 + HS V1.4 2013/02/07
-+
-+Window team code & BT team code
-+ */
-+
-+
-+u8 rtw_btcoex_parse_BT_info_notify_cmd(_adapter *padapter, u8 *pcmd, u16 cmdlen)
-+{
-+#define BT_INFO_LENGTH 8
-+
-+ u8 curPollEnable = pcmd[0];
-+ u8 curPollTime = pcmd[1];
-+ u8 btInfoReason = pcmd[2];
-+ u8 btInfoLen = pcmd[3];
-+ u8 btinfo[BT_INFO_LENGTH];
-+
-+ u8 localBuf[6] = "";
-+ u8 *pRetPar;
-+ u8 len = 0, tx_event_length = 0;
-+ RTW_HCI_STATUS status = HCI_STATUS_SUCCESS;
-+ rtw_HCI_event *pEvent;
-+
-+ /* RTW_INFO("%s\n",__func__);
-+ RTW_INFO("current Poll Enable: %d, currrent Poll Time: %d\n",curPollEnable,curPollTime);
-+ RTW_INFO("BT Info reason: %d, BT Info length: %d\n",btInfoReason,btInfoLen);
-+ RTW_INFO("%02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n"
-+ ,pcmd[4],pcmd[5],pcmd[6],pcmd[7],pcmd[8],pcmd[9],pcmd[10],pcmd[11]);*/
-+
-+ _rtw_memset(btinfo, 0, BT_INFO_LENGTH);
-+
-+#if 1
-+ if (BT_INFO_LENGTH != btInfoLen) {
-+ status = HCI_STATUS_INVALID_HCI_CMD_PARA_VALUE;
-+ RTW_INFO("Error BT Info Length: %d\n", btInfoLen);
-+ /* return _FAIL; */
-+ } else
-+#endif
-+ {
-+ if (0x1 == btInfoReason || 0x2 == btInfoReason) {
-+ _rtw_memcpy(btinfo, &pcmd[4], btInfoLen);
-+ btinfo[0] = btInfoReason;
-+ rtw_btcoex_btinfo_cmd(padapter, btinfo, btInfoLen);
-+ } else
-+ RTW_INFO("Other BT info reason\n");
-+ }
-+
-+ /* send complete event to BT */
-+ {
-+
-+ pEvent = (rtw_HCI_event *)(&localBuf[0]);
-+
-+ pEvent->EventCode = HCI_EVENT_COMMAND_COMPLETE;
-+ pEvent->Data[0] = 0x1; /* packet # */
-+ pEvent->Data[1] = HCIOPCODELOW(HCI_BT_INFO_NOTIFY, OGF_EXTENSION);
-+ pEvent->Data[2] = HCIOPCODEHIGHT(HCI_BT_INFO_NOTIFY, OGF_EXTENSION);
-+ len = len + 3;
-+
-+ /* Return parameters starts from here */
-+ pRetPar = &pEvent->Data[len];
-+ pRetPar[0] = status; /* status */
-+
-+ len++;
-+ pEvent->Length = len;
-+
-+ /* total tx event length + EventCode length + sizeof(length) */
-+ tx_event_length = pEvent->Length + 2;
-+#if 0
-+ rtw_btcoex_dump_tx_msg((u8 *)pEvent, tx_event_length, "BT_info_event");
-+#endif
-+ status = rtw_btcoex_sendmsgbysocket(padapter, (u8 *)pEvent, tx_event_length, _FALSE);
-+
-+ return status;
-+ /* bthci_IndicateEvent(Adapter, PPacketIrpEvent, len+2); */
-+ }
-+}
-+
-+u8 rtw_btcoex_parse_BT_patch_ver_info_cmd(_adapter *padapter, u8 *pcmd, u16 cmdlen)
-+{
-+ RTW_HCI_STATUS status = HCI_STATUS_SUCCESS;
-+ u16 btPatchVer = 0x0, btHciVer = 0x0;
-+ /* u16 *pU2tmp; */
-+
-+ u8 localBuf[6] = "";
-+ u8 *pRetPar;
-+ u8 len = 0, tx_event_length = 0;
-+ rtw_HCI_event *pEvent;
-+
-+ btHciVer = pcmd[0] | pcmd[1] << 8;
-+ btPatchVer = pcmd[2] | pcmd[3] << 8;
-+
-+
-+ RTW_INFO("%s, cmd:%02x %02x %02x %02x\n", __func__, pcmd[0] , pcmd[1] , pcmd[2] , pcmd[3]);
-+ RTW_INFO("%s, HCI Ver:%d, Patch Ver:%d\n", __func__, btHciVer, btPatchVer);
-+
-+ rtw_btcoex_SetBtPatchVersion(padapter, btHciVer, btPatchVer);
-+
-+
-+ /* send complete event to BT */
-+ {
-+ pEvent = (rtw_HCI_event *)(&localBuf[0]);
-+
-+
-+ pEvent->EventCode = HCI_EVENT_COMMAND_COMPLETE;
-+ pEvent->Data[0] = 0x1; /* packet # */
-+ pEvent->Data[1] = HCIOPCODELOW(HCI_BT_PATCH_VERSION_NOTIFY, OGF_EXTENSION);
-+ pEvent->Data[2] = HCIOPCODEHIGHT(HCI_BT_PATCH_VERSION_NOTIFY, OGF_EXTENSION);
-+ len = len + 3;
-+
-+ /* Return parameters starts from here */
-+ pRetPar = &pEvent->Data[len];
-+ pRetPar[0] = status; /* status */
-+
-+ len++;
-+ pEvent->Length = len;
-+
-+ /* total tx event length + EventCode length + sizeof(length) */
-+ tx_event_length = pEvent->Length + 2;
-+#if 0
-+ rtw_btcoex_dump_tx_msg((u8 *)pEvent, tx_event_length, "BT_patch_event");
-+#endif
-+ status = rtw_btcoex_sendmsgbysocket(padapter, (u8 *)pEvent, tx_event_length, _FALSE);
-+ return status;
-+ /* bthci_IndicateEvent(Adapter, PPacketIrpEvent, len+2); */
-+ }
-+}
-+
-+u8 rtw_btcoex_parse_HCI_Ver_notify_cmd(_adapter *padapter, u8 *pcmd, u16 cmdlen)
-+{
-+ RTW_HCI_STATUS status = HCI_STATUS_SUCCESS;
-+ u16 hciver = pcmd[0] | pcmd[1] << 8;
-+
-+ u8 localBuf[6] = "";
-+ u8 *pRetPar;
-+ u8 len = 0, tx_event_length = 0;
-+ rtw_HCI_event *pEvent;
-+
-+ struct bt_coex_info *pcoex_info = &padapter->coex_info;
-+ PBT_MGNT pBtMgnt = &pcoex_info->BtMgnt;
-+ pBtMgnt->ExtConfig.HCIExtensionVer = hciver;
-+ RTW_INFO("%s, HCI Version: %d\n", __func__, pBtMgnt->ExtConfig.HCIExtensionVer);
-+ if (pBtMgnt->ExtConfig.HCIExtensionVer < 4) {
-+ status = HCI_STATUS_INVALID_HCI_CMD_PARA_VALUE;
-+ RTW_INFO("%s, Version = %d, HCI Version < 4\n", __func__, pBtMgnt->ExtConfig.HCIExtensionVer);
-+ } else
-+ rtw_btcoex_SetHciVersion(padapter, hciver);
-+ /* send complete event to BT */
-+ {
-+ pEvent = (rtw_HCI_event *)(&localBuf[0]);
-+
-+
-+ pEvent->EventCode = HCI_EVENT_COMMAND_COMPLETE;
-+ pEvent->Data[0] = 0x1; /* packet # */
-+ pEvent->Data[1] = HCIOPCODELOW(HCI_EXTENSION_VERSION_NOTIFY, OGF_EXTENSION);
-+ pEvent->Data[2] = HCIOPCODEHIGHT(HCI_EXTENSION_VERSION_NOTIFY, OGF_EXTENSION);
-+ len = len + 3;
-+
-+ /* Return parameters starts from here */
-+ pRetPar = &pEvent->Data[len];
-+ pRetPar[0] = status; /* status */
-+
-+ len++;
-+ pEvent->Length = len;
-+
-+ /* total tx event length + EventCode length + sizeof(length) */
-+ tx_event_length = pEvent->Length + 2;
-+
-+ status = rtw_btcoex_sendmsgbysocket(padapter, (u8 *)pEvent, tx_event_length, _FALSE);
-+ return status;
-+ /* bthci_IndicateEvent(Adapter, PPacketIrpEvent, len+2); */
-+ }
-+
-+}
-+
-+u8 rtw_btcoex_parse_WIFI_scan_notify_cmd(_adapter *padapter, u8 *pcmd, u16 cmdlen)
-+{
-+ RTW_HCI_STATUS status = HCI_STATUS_SUCCESS;
-+
-+ u8 localBuf[6] = "";
-+ u8 *pRetPar;
-+ u8 len = 0, tx_event_length = 0;
-+ rtw_HCI_event *pEvent;
-+
-+ struct bt_coex_info *pcoex_info = &padapter->coex_info;
-+ PBT_MGNT pBtMgnt = &pcoex_info->BtMgnt;
-+ pBtMgnt->ExtConfig.bEnableWifiScanNotify = pcmd[0];
-+ RTW_INFO("%s, bEnableWifiScanNotify: %d\n", __func__, pBtMgnt->ExtConfig.bEnableWifiScanNotify);
-+
-+ /* send complete event to BT */
-+ {
-+ pEvent = (rtw_HCI_event *)(&localBuf[0]);
-+
-+
-+ pEvent->EventCode = HCI_EVENT_COMMAND_COMPLETE;
-+ pEvent->Data[0] = 0x1; /* packet # */
-+ pEvent->Data[1] = HCIOPCODELOW(HCI_ENABLE_WIFI_SCAN_NOTIFY, OGF_EXTENSION);
-+ pEvent->Data[2] = HCIOPCODEHIGHT(HCI_ENABLE_WIFI_SCAN_NOTIFY, OGF_EXTENSION);
-+ len = len + 3;
-+
-+ /* Return parameters starts from here */
-+ pRetPar = &pEvent->Data[len];
-+ pRetPar[0] = status; /* status */
-+
-+ len++;
-+ pEvent->Length = len;
-+
-+ /* total tx event length + EventCode length + sizeof(length) */
-+ tx_event_length = pEvent->Length + 2;
-+
-+ status = rtw_btcoex_sendmsgbysocket(padapter, (u8 *)pEvent, tx_event_length, _FALSE);
-+ return status;
-+ /* bthci_IndicateEvent(Adapter, PPacketIrpEvent, len+2); */
-+ }
-+}
-+
-+u8 rtw_btcoex_parse_HCI_link_status_notify_cmd(_adapter *padapter, u8 *pcmd, u16 cmdlen)
-+{
-+ RTW_HCI_STATUS status = HCI_STATUS_SUCCESS;
-+ struct bt_coex_info *pcoex_info = &padapter->coex_info;
-+ PBT_MGNT pBtMgnt = &pcoex_info->BtMgnt;
-+ /* PBT_DBG pBtDbg=&padapter->MgntInfo.BtInfo.BtDbg; */
-+ u8 i, numOfHandle = 0, numOfAcl = 0;
-+ u16 conHandle;
-+ u8 btProfile, btCoreSpec, linkRole;
-+ u8 *pTriple;
-+
-+ u8 localBuf[6] = "";
-+ u8 *pRetPar;
-+ u8 len = 0, tx_event_length = 0;
-+ rtw_HCI_event *pEvent;
-+
-+ /* pBtDbg->dbgHciInfo.hciCmdCntLinkStatusNotify++; */
-+ /* RT_DISP_DATA(FIOCTL, IOCTL_BT_HCICMD_EXT, "LinkStatusNotify, Hex Data :\n", */
-+ /* &pHciCmd->Data[0], pHciCmd->Length); */
-+
-+ RTW_INFO("BTLinkStatusNotify\n");
-+
-+ /* Current only RTL8723 support this command. */
-+ /* pBtMgnt->bSupportProfile = TRUE; */
-+ pBtMgnt->bSupportProfile = _FALSE;
-+
-+ pBtMgnt->ExtConfig.NumberOfACL = 0;
-+ pBtMgnt->ExtConfig.NumberOfSCO = 0;
-+
-+ numOfHandle = pcmd[0];
-+ /* RT_DISP(FIOCTL, IOCTL_BT_HCICMD_EXT, ("numOfHandle = 0x%x\n", numOfHandle)); */
-+ /* RT_DISP(FIOCTL, IOCTL_BT_HCICMD_EXT, ("HCIExtensionVer = %d\n", pBtMgnt->ExtConfig.HCIExtensionVer)); */
-+ RTW_INFO("numOfHandle = 0x%x\n", numOfHandle);
-+ RTW_INFO("HCIExtensionVer = %d\n", pBtMgnt->ExtConfig.HCIExtensionVer);
-+
-+ pTriple = &pcmd[1];
-+ for (i = 0; i < numOfHandle; i++) {
-+ if (pBtMgnt->ExtConfig.HCIExtensionVer < 1) {
-+ conHandle = *((u8 *)&pTriple[0]);
-+ btProfile = pTriple[2];
-+ btCoreSpec = pTriple[3];
-+ if (BT_PROFILE_SCO == btProfile)
-+ pBtMgnt->ExtConfig.NumberOfSCO++;
-+ else {
-+ pBtMgnt->ExtConfig.NumberOfACL++;
-+ pBtMgnt->ExtConfig.aclLink[i].ConnectHandle = conHandle;
-+ pBtMgnt->ExtConfig.aclLink[i].BTProfile = btProfile;
-+ pBtMgnt->ExtConfig.aclLink[i].BTCoreSpec = btCoreSpec;
-+ }
-+ /* RT_DISP(FIOCTL, IOCTL_BT_HCICMD_EXT, */
-+ /* ("Connection_Handle=0x%x, BTProfile=%d, BTSpec=%d\n", */
-+ /* conHandle, btProfile, btCoreSpec)); */
-+ RTW_INFO("Connection_Handle=0x%x, BTProfile=%d, BTSpec=%d\n", conHandle, btProfile, btCoreSpec);
-+ pTriple += 4;
-+ } else if (pBtMgnt->ExtConfig.HCIExtensionVer >= 1) {
-+ conHandle = *((pu2Byte)&pTriple[0]);
-+ btProfile = pTriple[2];
-+ btCoreSpec = pTriple[3];
-+ linkRole = pTriple[4];
-+ if (BT_PROFILE_SCO == btProfile)
-+ pBtMgnt->ExtConfig.NumberOfSCO++;
-+ else {
-+ pBtMgnt->ExtConfig.NumberOfACL++;
-+ pBtMgnt->ExtConfig.aclLink[i].ConnectHandle = conHandle;
-+ pBtMgnt->ExtConfig.aclLink[i].BTProfile = btProfile;
-+ pBtMgnt->ExtConfig.aclLink[i].BTCoreSpec = btCoreSpec;
-+ pBtMgnt->ExtConfig.aclLink[i].linkRole = linkRole;
-+ }
-+ /* RT_DISP(FIOCTL, IOCTL_BT_HCICMD_EXT, */
-+ RTW_INFO("Connection_Handle=0x%x, BTProfile=%d, BTSpec=%d, LinkRole=%d\n",
-+ conHandle, btProfile, btCoreSpec, linkRole);
-+ pTriple += 5;
-+ }
-+ }
-+ rtw_btcoex_StackUpdateProfileInfo();
-+
-+ /* send complete event to BT */
-+ {
-+ pEvent = (rtw_HCI_event *)(&localBuf[0]);
-+
-+
-+ pEvent->EventCode = HCI_EVENT_COMMAND_COMPLETE;
-+ pEvent->Data[0] = 0x1; /* packet # */
-+ pEvent->Data[1] = HCIOPCODELOW(HCI_LINK_STATUS_NOTIFY, OGF_EXTENSION);
-+ pEvent->Data[2] = HCIOPCODEHIGHT(HCI_LINK_STATUS_NOTIFY, OGF_EXTENSION);
-+ len = len + 3;
-+
-+ /* Return parameters starts from here */
-+ pRetPar = &pEvent->Data[len];
-+ pRetPar[0] = status; /* status */
-+
-+ len++;
-+ pEvent->Length = len;
-+
-+ /* total tx event length + EventCode length + sizeof(length) */
-+ tx_event_length = pEvent->Length + 2;
-+
-+ status = rtw_btcoex_sendmsgbysocket(padapter, (u8 *)pEvent, tx_event_length, _FALSE);
-+ return status;
-+ /* bthci_IndicateEvent(Adapter, PPacketIrpEvent, len+2); */
-+ }
-+
-+
-+}
-+
-+u8 rtw_btcoex_parse_HCI_BT_coex_notify_cmd(_adapter *padapter, u8 *pcmd, u16 cmdlen)
-+{
-+ u8 localBuf[6] = "";
-+ u8 *pRetPar;
-+ u8 len = 0, tx_event_length = 0;
-+ rtw_HCI_event *pEvent;
-+ RTW_HCI_STATUS status = HCI_STATUS_SUCCESS;
-+
-+ {
-+ pEvent = (rtw_HCI_event *)(&localBuf[0]);
-+
-+
-+ pEvent->EventCode = HCI_EVENT_COMMAND_COMPLETE;
-+ pEvent->Data[0] = 0x1; /* packet # */
-+ pEvent->Data[1] = HCIOPCODELOW(HCI_BT_COEX_NOTIFY, OGF_EXTENSION);
-+ pEvent->Data[2] = HCIOPCODEHIGHT(HCI_BT_COEX_NOTIFY, OGF_EXTENSION);
-+ len = len + 3;
-+
-+ /* Return parameters starts from here */
-+ pRetPar = &pEvent->Data[len];
-+ pRetPar[0] = status; /* status */
-+
-+ len++;
-+ pEvent->Length = len;
-+
-+ /* total tx event length + EventCode length + sizeof(length) */
-+ tx_event_length = pEvent->Length + 2;
-+
-+ status = rtw_btcoex_sendmsgbysocket(padapter, (u8 *)pEvent, tx_event_length, _FALSE);
-+ return status;
-+ /* bthci_IndicateEvent(Adapter, PPacketIrpEvent, len+2); */
-+ }
-+}
-+
-+u8 rtw_btcoex_parse_HCI_BT_operation_notify_cmd(_adapter *padapter, u8 *pcmd, u16 cmdlen)
-+{
-+ u8 localBuf[6] = "";
-+ u8 *pRetPar;
-+ u8 len = 0, tx_event_length = 0;
-+ rtw_HCI_event *pEvent;
-+ RTW_HCI_STATUS status = HCI_STATUS_SUCCESS;
-+
-+ RTW_INFO("%s, OP code: %d\n", __func__, pcmd[0]);
-+
-+ switch (pcmd[0]) {
-+ case HCI_BT_OP_NONE:
-+ RTW_INFO("[bt operation] : Operation None!!\n");
-+ break;
-+ case HCI_BT_OP_INQUIRY_START:
-+ RTW_INFO("[bt operation] : Inquiry start!!\n");
-+ break;
-+ case HCI_BT_OP_INQUIRY_FINISH:
-+ RTW_INFO("[bt operation] : Inquiry finished!!\n");
-+ break;
-+ case HCI_BT_OP_PAGING_START:
-+ RTW_INFO("[bt operation] : Paging is started!!\n");
-+ break;
-+ case HCI_BT_OP_PAGING_SUCCESS:
-+ RTW_INFO("[bt operation] : Paging complete successfully!!\n");
-+ break;
-+ case HCI_BT_OP_PAGING_UNSUCCESS:
-+ RTW_INFO("[bt operation] : Paging complete unsuccessfully!!\n");
-+ break;
-+ case HCI_BT_OP_PAIRING_START:
-+ RTW_INFO("[bt operation] : Pairing start!!\n");
-+ break;
-+ case HCI_BT_OP_PAIRING_FINISH:
-+ RTW_INFO("[bt operation] : Pairing finished!!\n");
-+ break;
-+ case HCI_BT_OP_BT_DEV_ENABLE:
-+ RTW_INFO("[bt operation] : BT Device is enabled!!\n");
-+ break;
-+ case HCI_BT_OP_BT_DEV_DISABLE:
-+ RTW_INFO("[bt operation] : BT Device is disabled!!\n");
-+ break;
-+ default:
-+ RTW_INFO("[bt operation] : Unknown, error!!\n");
-+ break;
-+ }
-+
-+ /* send complete event to BT */
-+ {
-+ pEvent = (rtw_HCI_event *)(&localBuf[0]);
-+
-+
-+ pEvent->EventCode = HCI_EVENT_COMMAND_COMPLETE;
-+ pEvent->Data[0] = 0x1; /* packet # */
-+ pEvent->Data[1] = HCIOPCODELOW(HCI_BT_OPERATION_NOTIFY, OGF_EXTENSION);
-+ pEvent->Data[2] = HCIOPCODEHIGHT(HCI_BT_OPERATION_NOTIFY, OGF_EXTENSION);
-+ len = len + 3;
-+
-+ /* Return parameters starts from here */
-+ pRetPar = &pEvent->Data[len];
-+ pRetPar[0] = status; /* status */
-+
-+ len++;
-+ pEvent->Length = len;
-+
-+ /* total tx event length + EventCode length + sizeof(length) */
-+ tx_event_length = pEvent->Length + 2;
-+
-+ status = rtw_btcoex_sendmsgbysocket(padapter, (u8 *)pEvent, tx_event_length, _FALSE);
-+ return status;
-+ /* bthci_IndicateEvent(Adapter, PPacketIrpEvent, len+2); */
-+ }
-+}
-+
-+u8 rtw_btcoex_parse_BT_AFH_MAP_notify_cmd(_adapter *padapter, u8 *pcmd, u16 cmdlen)
-+{
-+ u8 localBuf[6] = "";
-+ u8 *pRetPar;
-+ u8 len = 0, tx_event_length = 0;
-+ rtw_HCI_event *pEvent;
-+ RTW_HCI_STATUS status = HCI_STATUS_SUCCESS;
-+
-+ {
-+ pEvent = (rtw_HCI_event *)(&localBuf[0]);
-+
-+
-+ pEvent->EventCode = HCI_EVENT_COMMAND_COMPLETE;
-+ pEvent->Data[0] = 0x1; /* packet # */
-+ pEvent->Data[1] = HCIOPCODELOW(HCI_BT_AFH_MAP_NOTIFY, OGF_EXTENSION);
-+ pEvent->Data[2] = HCIOPCODEHIGHT(HCI_BT_AFH_MAP_NOTIFY, OGF_EXTENSION);
-+ len = len + 3;
-+
-+ /* Return parameters starts from here */
-+ pRetPar = &pEvent->Data[len];
-+ pRetPar[0] = status; /* status */
-+
-+ len++;
-+ pEvent->Length = len;
-+
-+ /* total tx event length + EventCode length + sizeof(length) */
-+ tx_event_length = pEvent->Length + 2;
-+
-+ status = rtw_btcoex_sendmsgbysocket(padapter, (u8 *)pEvent, tx_event_length, _FALSE);
-+ return status;
-+ /* bthci_IndicateEvent(Adapter, PPacketIrpEvent, len+2); */
-+ }
-+}
-+
-+u8 rtw_btcoex_parse_BT_register_val_notify_cmd(_adapter *padapter, u8 *pcmd, u16 cmdlen)
-+{
-+
-+ u8 localBuf[6] = "";
-+ u8 *pRetPar;
-+ u8 len = 0, tx_event_length = 0;
-+ rtw_HCI_event *pEvent;
-+ RTW_HCI_STATUS status = HCI_STATUS_SUCCESS;
-+
-+ {
-+ pEvent = (rtw_HCI_event *)(&localBuf[0]);
-+
-+
-+ pEvent->EventCode = HCI_EVENT_COMMAND_COMPLETE;
-+ pEvent->Data[0] = 0x1; /* packet # */
-+ pEvent->Data[1] = HCIOPCODELOW(HCI_BT_REGISTER_VALUE_NOTIFY, OGF_EXTENSION);
-+ pEvent->Data[2] = HCIOPCODEHIGHT(HCI_BT_REGISTER_VALUE_NOTIFY, OGF_EXTENSION);
-+ len = len + 3;
-+
-+ /* Return parameters starts from here */
-+ pRetPar = &pEvent->Data[len];
-+ pRetPar[0] = status; /* status */
-+
-+ len++;
-+ pEvent->Length = len;
-+
-+ /* total tx event length + EventCode length + sizeof(length) */
-+ tx_event_length = pEvent->Length + 2;
-+
-+ status = rtw_btcoex_sendmsgbysocket(padapter, (u8 *)pEvent, tx_event_length, _FALSE);
-+ return status;
-+ /* bthci_IndicateEvent(Adapter, PPacketIrpEvent, len+2); */
-+ }
-+}
-+
-+u8 rtw_btcoex_parse_HCI_BT_abnormal_notify_cmd(_adapter *padapter, u8 *pcmd, u16 cmdlen)
-+{
-+ u8 localBuf[6] = "";
-+ u8 *pRetPar;
-+ u8 len = 0, tx_event_length = 0;
-+ rtw_HCI_event *pEvent;
-+ RTW_HCI_STATUS status = HCI_STATUS_SUCCESS;
-+
-+ {
-+ pEvent = (rtw_HCI_event *)(&localBuf[0]);
-+
-+
-+ pEvent->EventCode = HCI_EVENT_COMMAND_COMPLETE;
-+ pEvent->Data[0] = 0x1; /* packet # */
-+ pEvent->Data[1] = HCIOPCODELOW(HCI_BT_ABNORMAL_NOTIFY, OGF_EXTENSION);
-+ pEvent->Data[2] = HCIOPCODEHIGHT(HCI_BT_ABNORMAL_NOTIFY, OGF_EXTENSION);
-+ len = len + 3;
-+
-+ /* Return parameters starts from here */
-+ pRetPar = &pEvent->Data[len];
-+ pRetPar[0] = status; /* status */
-+
-+ len++;
-+ pEvent->Length = len;
-+
-+ /* total tx event length + EventCode length + sizeof(length) */
-+ tx_event_length = pEvent->Length + 2;
-+
-+ status = rtw_btcoex_sendmsgbysocket(padapter, (u8 *)pEvent, tx_event_length, _FALSE);
-+ return status;
-+ /* bthci_IndicateEvent(Adapter, PPacketIrpEvent, len+2); */
-+ }
-+}
-+
-+u8 rtw_btcoex_parse_HCI_query_RF_status_cmd(_adapter *padapter, u8 *pcmd, u16 cmdlen)
-+{
-+ u8 localBuf[6] = "";
-+ u8 *pRetPar;
-+ u8 len = 0, tx_event_length = 0;
-+ rtw_HCI_event *pEvent;
-+ RTW_HCI_STATUS status = HCI_STATUS_SUCCESS;
-+
-+ {
-+ pEvent = (rtw_HCI_event *)(&localBuf[0]);
-+
-+
-+ pEvent->EventCode = HCI_EVENT_COMMAND_COMPLETE;
-+ pEvent->Data[0] = 0x1; /* packet # */
-+ pEvent->Data[1] = HCIOPCODELOW(HCI_QUERY_RF_STATUS, OGF_EXTENSION);
-+ pEvent->Data[2] = HCIOPCODEHIGHT(HCI_QUERY_RF_STATUS, OGF_EXTENSION);
-+ len = len + 3;
-+
-+ /* Return parameters starts from here */
-+ pRetPar = &pEvent->Data[len];
-+ pRetPar[0] = status; /* status */
-+
-+ len++;
-+ pEvent->Length = len;
-+
-+ /* total tx event length + EventCode length + sizeof(length) */
-+ tx_event_length = pEvent->Length + 2;
-+
-+ status = rtw_btcoex_sendmsgbysocket(padapter, (u8 *)pEvent, tx_event_length, _FALSE);
-+ return status;
-+ /* bthci_IndicateEvent(Adapter, PPacketIrpEvent, len+2); */
-+ }
-+}
-+
-+/*****************************************
-+* HCI cmd format :
-+*| 15 - 0 |
-+*| OPcode (OCF|OGF<<10) |
-+*| 15 - 8 |7 - 0 |
-+*|Cmd para |Cmd para Length |
-+*|Cmd para...... |
-+******************************************/
-+
-+/* bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
-+ * | OCF | OGF | */
-+void rtw_btcoex_parse_hci_extend_cmd(_adapter *padapter, u8 *pcmd, u16 len, const u16 hci_OCF)
-+{
-+
-+ RTW_INFO("%s: OCF: %x\n", __func__, hci_OCF);
-+ switch (hci_OCF) {
-+ case HCI_EXTENSION_VERSION_NOTIFY:
-+ RTW_INFO("HCI_EXTENSION_VERSION_NOTIFY\n");
-+ rtw_btcoex_parse_HCI_Ver_notify_cmd(padapter, pcmd, len);
-+ break;
-+ case HCI_LINK_STATUS_NOTIFY:
-+ RTW_INFO("HCI_LINK_STATUS_NOTIFY\n");
-+ rtw_btcoex_parse_HCI_link_status_notify_cmd(padapter, pcmd, len);
-+ break;
-+ case HCI_BT_OPERATION_NOTIFY:
-+ /* only for 8723a 2ant */
-+ RTW_INFO("HCI_BT_OPERATION_NOTIFY\n");
-+ rtw_btcoex_parse_HCI_BT_operation_notify_cmd(padapter, pcmd, len);
-+ /* */
-+ break;
-+ case HCI_ENABLE_WIFI_SCAN_NOTIFY:
-+ RTW_INFO("HCI_ENABLE_WIFI_SCAN_NOTIFY\n");
-+ rtw_btcoex_parse_WIFI_scan_notify_cmd(padapter, pcmd, len);
-+ break;
-+ case HCI_QUERY_RF_STATUS:
-+ /* only for 8723b 2ant */
-+ RTW_INFO("HCI_QUERY_RF_STATUS\n");
-+ rtw_btcoex_parse_HCI_query_RF_status_cmd(padapter, pcmd, len);
-+ break;
-+ case HCI_BT_ABNORMAL_NOTIFY:
-+ RTW_INFO("HCI_BT_ABNORMAL_NOTIFY\n");
-+ rtw_btcoex_parse_HCI_BT_abnormal_notify_cmd(padapter, pcmd, len);
-+ break;
-+ case HCI_BT_INFO_NOTIFY:
-+ RTW_INFO("HCI_BT_INFO_NOTIFY\n");
-+ rtw_btcoex_parse_BT_info_notify_cmd(padapter, pcmd, len);
-+ break;
-+ case HCI_BT_COEX_NOTIFY:
-+ RTW_INFO("HCI_BT_COEX_NOTIFY\n");
-+ rtw_btcoex_parse_HCI_BT_coex_notify_cmd(padapter, pcmd, len);
-+ break;
-+ case HCI_BT_PATCH_VERSION_NOTIFY:
-+ RTW_INFO("HCI_BT_PATCH_VERSION_NOTIFY\n");
-+ rtw_btcoex_parse_BT_patch_ver_info_cmd(padapter, pcmd, len);
-+ break;
-+ case HCI_BT_AFH_MAP_NOTIFY:
-+ RTW_INFO("HCI_BT_AFH_MAP_NOTIFY\n");
-+ rtw_btcoex_parse_BT_AFH_MAP_notify_cmd(padapter, pcmd, len);
-+ break;
-+ case HCI_BT_REGISTER_VALUE_NOTIFY:
-+ RTW_INFO("HCI_BT_REGISTER_VALUE_NOTIFY\n");
-+ rtw_btcoex_parse_BT_register_val_notify_cmd(padapter, pcmd, len);
-+ break;
-+ default:
-+ RTW_INFO("ERROR!!! Unknown OCF: %x\n", hci_OCF);
-+ break;
-+
-+ }
-+}
-+
-+void rtw_btcoex_parse_hci_cmd(_adapter *padapter, u8 *pcmd, u16 len)
-+{
-+ u16 opcode = pcmd[0] | pcmd[1] << 8;
-+ u16 hci_OGF = HCI_OGF(opcode);
-+ u16 hci_OCF = HCI_OCF(opcode);
-+ u8 cmdlen = len - 3;
-+ u8 pare_len = pcmd[2];
-+
-+ RTW_INFO("%s OGF: %x,OCF: %x\n", __func__, hci_OGF, hci_OCF);
-+ switch (hci_OGF) {
-+ case OGF_EXTENSION:
-+ RTW_INFO("HCI_EXTENSION_CMD_OGF\n");
-+ rtw_btcoex_parse_hci_extend_cmd(padapter, &pcmd[3], cmdlen, hci_OCF);
-+ break;
-+ default:
-+ RTW_INFO("Other OGF: %x\n", hci_OGF);
-+ break;
-+ }
-+}
-+
-+u16 rtw_btcoex_parse_recv_data(u8 *msg, u8 msg_size)
-+{
-+ u8 cmp_msg1[32] = attend_ack;
-+ u8 cmp_msg2[32] = leave_ack;
-+ u8 cmp_msg3[32] = bt_leave;
-+ u8 cmp_msg4[32] = invite_req;
-+ u8 cmp_msg5[32] = attend_req;
-+ u8 cmp_msg6[32] = invite_rsp;
-+ u8 res = OTHER;
-+
-+ if (_rtw_memcmp(cmp_msg1, msg, msg_size) == _TRUE) {
-+ /*RTW_INFO("%s, msg:%s\n",__func__,msg);*/
-+ res = RX_ATTEND_ACK;
-+ } else if (_rtw_memcmp(cmp_msg2, msg, msg_size) == _TRUE) {
-+ /*RTW_INFO("%s, msg:%s\n",__func__,msg);*/
-+ res = RX_LEAVE_ACK;
-+ } else if (_rtw_memcmp(cmp_msg3, msg, msg_size) == _TRUE) {
-+ /*RTW_INFO("%s, msg:%s\n",__func__,msg);*/
-+ res = RX_BT_LEAVE;
-+ } else if (_rtw_memcmp(cmp_msg4, msg, msg_size) == _TRUE) {
-+ /*RTW_INFO("%s, msg:%s\n",__func__,msg);*/
-+ res = RX_INVITE_REQ;
-+ } else if (_rtw_memcmp(cmp_msg5, msg, msg_size) == _TRUE)
-+ res = RX_ATTEND_REQ;
-+ else if (_rtw_memcmp(cmp_msg6, msg, msg_size) == _TRUE)
-+ res = RX_INVITE_RSP;
-+ else {
-+ /*RTW_INFO("%s, %s\n", __func__, msg);*/
-+ res = OTHER;
-+ }
-+
-+ /*RTW_INFO("%s, res:%d\n", __func__, res);*/
-+
-+ return res;
-+}
-+
-+void rtw_btcoex_recvmsgbysocket(void *data)
-+{
-+ u8 recv_data[255];
-+ u8 tx_msg[255] = leave_ack;
-+ u32 len = 0;
-+ u16 recv_length = 0;
-+ u16 parse_res = 0;
-+#if 0
-+ u8 para_len = 0, polling_enable = 0, poling_interval = 0, reason = 0, btinfo_len = 0;
-+ u8 btinfo[BT_INFO_LEN] = {0};
-+#endif
-+
-+ struct bt_coex_info *pcoex_info = NULL;
-+ struct sock *sk = NULL;
-+ struct sk_buff *skb = NULL;
-+
-+ /*RTW_INFO("%s\n",__func__);*/
-+
-+ if (pbtcoexadapter == NULL) {
-+ RTW_INFO("%s: btcoexadapter NULL!\n", __func__);
-+ return;
-+ }
-+
-+ pcoex_info = &pbtcoexadapter->coex_info;
-+ sk = pcoex_info->sk_store;
-+
-+ if (sk == NULL) {
-+ RTW_INFO("%s: critical error when receive socket data!\n", __func__);
-+ return;
-+ }
-+
-+ len = skb_queue_len(&sk->sk_receive_queue);
-+ while (len > 0) {
-+ skb = skb_dequeue(&sk->sk_receive_queue);
-+
-+ /*important: cut the udp header from skb->data! header length is 8 byte*/
-+ recv_length = skb->len - 8;
-+ _rtw_memset(recv_data, 0, sizeof(recv_data));
-+ _rtw_memcpy(recv_data, skb->data + 8, recv_length);
-+
-+ parse_res = rtw_btcoex_parse_recv_data(recv_data, recv_length);
-+#if 0
-+ if (RX_ATTEND_ACK == parse_res) {
-+ /* attend ack */
-+ pcoex_info->BT_attend = _TRUE;
-+ RTW_INFO("RX_ATTEND_ACK!,sock_open:%d, BT_attend:%d\n", pcoex_info->sock_open, pcoex_info->BT_attend);
-+ } else if (RX_ATTEND_REQ == parse_res) {
-+ /* attend req from BT */
-+ pcoex_info->BT_attend = _TRUE;
-+ RTW_INFO("RX_BT_ATTEND_REQ!,sock_open:%d, BT_attend:%d\n", pcoex_info->sock_open, pcoex_info->BT_attend);
-+ rtw_btcoex_sendmsgbysocket(pbtcoexadapter, attend_ack, sizeof(attend_ack), _FALSE);
-+ } else if (RX_INVITE_REQ == parse_res) {
-+ /* invite req from BT */
-+ pcoex_info->BT_attend = _TRUE;
-+ RTW_INFO("RX_INVITE_REQ!,sock_open:%d, BT_attend:%d\n", pcoex_info->sock_open, pcoex_info->BT_attend);
-+ rtw_btcoex_sendmsgbysocket(pbtcoexadapter, invite_rsp, sizeof(invite_rsp), _FALSE);
-+ } else if (RX_INVITE_RSP == parse_res) {
-+ /* invite rsp */
-+ pcoex_info->BT_attend = _TRUE;
-+ RTW_INFO("RX_INVITE_RSP!,sock_open:%d, BT_attend:%d\n", pcoex_info->sock_open, pcoex_info->BT_attend);
-+ } else if (RX_LEAVE_ACK == parse_res) {
-+ /* mean BT know wifi will leave */
-+ pcoex_info->BT_attend = _FALSE;
-+ RTW_INFO("RX_LEAVE_ACK!,sock_open:%d, BT_attend:%d\n", pcoex_info->sock_open, pcoex_info->BT_attend);
-+ } else if (RX_BT_LEAVE == parse_res) {
-+ /* BT leave */
-+ rtw_btcoex_sendmsgbysocket(pbtcoexadapter, leave_ack, sizeof(leave_ack), _FALSE); /* no ack */
-+ pcoex_info->BT_attend = _FALSE;
-+ RTW_INFO("RX_BT_LEAVE!sock_open:%d, BT_attend:%d\n", pcoex_info->sock_open, pcoex_info->BT_attend);
-+ } else {
-+ /* todo: check if recv data are really hci cmds */
-+ if (_TRUE == pcoex_info->BT_attend)
-+ rtw_btcoex_parse_hci_cmd(pbtcoexadapter, recv_data, recv_length);
-+ }
-+#endif
-+ switch (parse_res) {
-+ case RX_ATTEND_ACK:
-+ /* attend ack */
-+ pcoex_info->BT_attend = _TRUE;
-+ RTW_INFO("RX_ATTEND_ACK!,sock_open:%d, BT_attend:%d\n", pcoex_info->sock_open, pcoex_info->BT_attend);
-+ rtw_btcoex_pta_off_on_notify(pbtcoexadapter, pcoex_info->BT_attend);
-+ break;
-+
-+ case RX_ATTEND_REQ:
-+ pcoex_info->BT_attend = _TRUE;
-+ RTW_INFO("RX_BT_ATTEND_REQ!,sock_open:%d, BT_attend:%d\n", pcoex_info->sock_open, pcoex_info->BT_attend);
-+ rtw_btcoex_sendmsgbysocket(pbtcoexadapter, attend_ack, sizeof(attend_ack), _FALSE);
-+ rtw_btcoex_pta_off_on_notify(pbtcoexadapter, pcoex_info->BT_attend);
-+ break;
-+
-+ case RX_INVITE_REQ:
-+ /* invite req from BT */
-+ pcoex_info->BT_attend = _TRUE;
-+ RTW_INFO("RX_INVITE_REQ!,sock_open:%d, BT_attend:%d\n", pcoex_info->sock_open, pcoex_info->BT_attend);
-+ rtw_btcoex_sendmsgbysocket(pbtcoexadapter, invite_rsp, sizeof(invite_rsp), _FALSE);
-+ rtw_btcoex_pta_off_on_notify(pbtcoexadapter, pcoex_info->BT_attend);
-+ break;
-+
-+ case RX_INVITE_RSP:
-+ /*invite rsp*/
-+ pcoex_info->BT_attend = _TRUE;
-+ RTW_INFO("RX_INVITE_RSP!,sock_open:%d, BT_attend:%d\n", pcoex_info->sock_open, pcoex_info->BT_attend);
-+ rtw_btcoex_pta_off_on_notify(pbtcoexadapter, pcoex_info->BT_attend);
-+ break;
-+
-+ case RX_LEAVE_ACK:
-+ /* mean BT know wifi will leave */
-+ pcoex_info->BT_attend = _FALSE;
-+ RTW_INFO("RX_LEAVE_ACK!,sock_open:%d, BT_attend:%d\n", pcoex_info->sock_open, pcoex_info->BT_attend);
-+ rtw_btcoex_pta_off_on_notify(pbtcoexadapter, pcoex_info->BT_attend);
-+ break;
-+
-+ case RX_BT_LEAVE:
-+ /* BT leave */
-+ rtw_btcoex_sendmsgbysocket(pbtcoexadapter, leave_ack, sizeof(leave_ack), _FALSE); /* no ack */
-+ pcoex_info->BT_attend = _FALSE;
-+ RTW_INFO("RX_BT_LEAVE!sock_open:%d, BT_attend:%d\n", pcoex_info->sock_open, pcoex_info->BT_attend);
-+ rtw_btcoex_pta_off_on_notify(pbtcoexadapter, pcoex_info->BT_attend);
-+ break;
-+
-+ default:
-+ if (_TRUE == pcoex_info->BT_attend)
-+ rtw_btcoex_parse_hci_cmd(pbtcoexadapter, recv_data, recv_length);
-+ else
-+ RTW_INFO("ERROR!! BT is UP\n");
-+ break;
-+
-+ }
-+
-+ len--;
-+ kfree_skb(skb);
-+ }
-+}
-+
-+#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 15, 0))
-+ void rtw_btcoex_recvmsg_init(struct sock *sk_in, s32 bytes)
-+#else
-+ void rtw_btcoex_recvmsg_init(struct sock *sk_in)
-+#endif
-+{
-+ struct bt_coex_info *pcoex_info = NULL;
-+
-+ if (pbtcoexadapter == NULL) {
-+ RTW_INFO("%s: btcoexadapter NULL\n", __func__);
-+ return;
-+ }
-+ pcoex_info = &pbtcoexadapter->coex_info;
-+ pcoex_info->sk_store = sk_in;
-+ if (pcoex_info->btcoex_wq != NULL)
-+ queue_delayed_work(pcoex_info->btcoex_wq, &pcoex_info->recvmsg_work, 0);
-+ else
-+ RTW_INFO("%s: BTCOEX workqueue NULL\n", __func__);
-+}
-+
-+u8 rtw_btcoex_sendmsgbysocket(_adapter *padapter, u8 *msg, u8 msg_size, bool force)
-+{
-+ u8 error;
-+ struct msghdr udpmsg;
-+ mm_segment_t oldfs;
-+ struct iovec iov;
-+ struct bt_coex_info *pcoex_info = &padapter->coex_info;
-+
-+ /* RTW_INFO("%s: msg:%s, force:%s\n", __func__, msg, force == _TRUE?"TRUE":"FALSE"); */
-+ if (_FALSE == force) {
-+ if (_FALSE == pcoex_info->BT_attend) {
-+ RTW_INFO("TX Blocked: WiFi-BT disconnected\n");
-+ return _FAIL;
-+ }
-+ }
-+
-+ iov.iov_base = (void *)msg;
-+ iov.iov_len = msg_size;
-+ udpmsg.msg_name = &pcoex_info->bt_sockaddr;
-+ udpmsg.msg_namelen = sizeof(struct sockaddr_in);
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 19, 0))
-+ /* referece:sock_xmit in kernel code
-+ * WRITE for sock_sendmsg, READ for sock_recvmsg
-+ * third parameter for msg_iovlen
-+ * last parameter for iov_len
-+ */
-+ iov_iter_init(&udpmsg.msg_iter, WRITE, &iov, 1, msg_size);
-+#else
-+ udpmsg.msg_iov = &iov;
-+ udpmsg.msg_iovlen = 1;
-+#endif
-+ udpmsg.msg_control = NULL;
-+ udpmsg.msg_controllen = 0;
-+ udpmsg.msg_flags = MSG_DONTWAIT | MSG_NOSIGNAL;
-+ oldfs = get_fs();
-+ set_fs(KERNEL_DS);
-+
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 1, 0))
-+ error = sock_sendmsg(pcoex_info->udpsock, &udpmsg);
-+#else
-+ error = sock_sendmsg(pcoex_info->udpsock, &udpmsg, msg_size);
-+#endif
-+ set_fs(oldfs);
-+ if (error < 0) {
-+ RTW_INFO("Error when sendimg msg, error:%d\n", error);
-+ return _FAIL;
-+ } else
-+ return _SUCCESS;
-+}
-+
-+u8 rtw_btcoex_create_kernel_socket(_adapter *padapter)
-+{
-+ s8 kernel_socket_err;
-+ u8 tx_msg[255] = attend_req;
-+ struct bt_coex_info *pcoex_info = &padapter->coex_info;
-+ s32 sock_reuse = 1;
-+ u8 status = _FAIL;
-+
-+ RTW_INFO("%s CONNECT_PORT %d\n", __func__, CONNECT_PORT);
-+
-+ if (NULL == pcoex_info) {
-+ RTW_INFO("coex_info: NULL\n");
-+ status = _FAIL;
-+ }
-+
-+ kernel_socket_err = sock_create(PF_INET, SOCK_DGRAM, 0, &pcoex_info->udpsock);
-+
-+ if (kernel_socket_err < 0) {
-+ RTW_INFO("Error during creation of socket error:%d\n", kernel_socket_err);
-+ status = _FAIL;
-+ } else {
-+ _rtw_memset(&(pcoex_info->wifi_sockaddr), 0, sizeof(pcoex_info->wifi_sockaddr));
-+ pcoex_info->wifi_sockaddr.sin_family = AF_INET;
-+ pcoex_info->wifi_sockaddr.sin_port = htons(CONNECT_PORT);
-+ pcoex_info->wifi_sockaddr.sin_addr.s_addr = htonl(INADDR_LOOPBACK);
-+
-+ _rtw_memset(&(pcoex_info->bt_sockaddr), 0, sizeof(pcoex_info->bt_sockaddr));
-+ pcoex_info->bt_sockaddr.sin_family = AF_INET;
-+ pcoex_info->bt_sockaddr.sin_port = htons(CONNECT_PORT_BT);
-+ pcoex_info->bt_sockaddr.sin_addr.s_addr = htonl(INADDR_LOOPBACK);
-+
-+ pcoex_info->sk_store = NULL;
-+ kernel_socket_err = pcoex_info->udpsock->ops->bind(pcoex_info->udpsock, (struct sockaddr *)&pcoex_info->wifi_sockaddr,
-+ sizeof(pcoex_info->wifi_sockaddr));
-+ if (kernel_socket_err == 0) {
-+ RTW_INFO("binding socket success\n");
-+ pcoex_info->udpsock->sk->sk_data_ready = rtw_btcoex_recvmsg_init;
-+ pcoex_info->sock_open |= KERNEL_SOCKET_OK;
-+ pcoex_info->BT_attend = _FALSE;
-+ RTW_INFO("WIFI sending attend_req\n");
-+ rtw_btcoex_sendmsgbysocket(padapter, attend_req, sizeof(attend_req), _TRUE);
-+ status = _SUCCESS;
-+ } else {
-+ pcoex_info->BT_attend = _FALSE;
-+ sock_release(pcoex_info->udpsock); /* bind fail release socket */
-+ RTW_INFO("Error binding socket: %d\n", kernel_socket_err);
-+ status = _FAIL;
-+ }
-+
-+ }
-+
-+ return status;
-+}
-+
-+void rtw_btcoex_close_kernel_socket(_adapter *padapter)
-+{
-+ struct bt_coex_info *pcoex_info = &padapter->coex_info;
-+ if (pcoex_info->sock_open & KERNEL_SOCKET_OK) {
-+ RTW_INFO("release kernel socket\n");
-+ sock_release(pcoex_info->udpsock);
-+ pcoex_info->sock_open &= ~(KERNEL_SOCKET_OK);
-+ if (_TRUE == pcoex_info->BT_attend)
-+ pcoex_info->BT_attend = _FALSE;
-+
-+ RTW_INFO("sock_open:%d, BT_attend:%d\n", pcoex_info->sock_open, pcoex_info->BT_attend);
-+ }
-+}
-+
-+void rtw_btcoex_init_socket(_adapter *padapter)
-+{
-+
-+ u8 is_invite = _FALSE;
-+ struct bt_coex_info *pcoex_info = &padapter->coex_info;
-+ RTW_INFO("%s\n", __func__);
-+ if (_FALSE == pcoex_info->is_exist) {
-+ _rtw_memset(pcoex_info, 0, sizeof(struct bt_coex_info));
-+ pcoex_info->btcoex_wq = create_workqueue("BTCOEX");
-+ INIT_DELAYED_WORK(&pcoex_info->recvmsg_work,
-+ (void *)rtw_btcoex_recvmsgbysocket);
-+ pbtcoexadapter = padapter;
-+ /* We expect BT is off if BT don't send ack to wifi */
-+ RTW_INFO("We expect BT is off if BT send ack to wifi\n");
-+ rtw_btcoex_pta_off_on_notify(pbtcoexadapter, _FALSE);
-+ if (rtw_btcoex_create_kernel_socket(padapter) == _SUCCESS)
-+ pcoex_info->is_exist = _TRUE;
-+ else {
-+ pcoex_info->is_exist = _FALSE;
-+ pbtcoexadapter = NULL;
-+ }
-+
-+ RTW_INFO("%s: pbtcoexadapter:%p, coex_info->is_exist: %s\n"
-+ , __func__, pbtcoexadapter, pcoex_info->is_exist == _TRUE ? "TRUE" : "FALSE");
-+ }
-+}
-+
-+void rtw_btcoex_close_socket(_adapter *padapter)
-+{
-+ struct bt_coex_info *pcoex_info = &padapter->coex_info;
-+
-+ RTW_INFO("%s--coex_info->is_exist: %s, pcoex_info->BT_attend:%s\n"
-+ , __func__, pcoex_info->is_exist == _TRUE ? "TRUE" : "FALSE", pcoex_info->BT_attend == _TRUE ? "TRUE" : "FALSE");
-+
-+ if (_TRUE == pcoex_info->is_exist) {
-+ if (_TRUE == pcoex_info->BT_attend) {
-+ /*inform BT wifi leave*/
-+ rtw_btcoex_sendmsgbysocket(padapter, wifi_leave, sizeof(wifi_leave), _FALSE);
-+ msleep(50);
-+ }
-+
-+ if (pcoex_info->btcoex_wq != NULL) {
-+ flush_workqueue(pcoex_info->btcoex_wq);
-+ destroy_workqueue(pcoex_info->btcoex_wq);
-+ }
-+
-+ rtw_btcoex_close_kernel_socket(padapter);
-+ pbtcoexadapter = NULL;
-+ pcoex_info->is_exist = _FALSE;
-+ }
-+}
-+
-+void rtw_btcoex_dump_tx_msg(u8 *tx_msg, u8 len, u8 *msg_name)
-+{
-+ u8 i = 0;
-+ RTW_INFO("======> Msg name: %s\n", msg_name);
-+ for (i = 0; i < len; i++)
-+ printk("%02x ", tx_msg[i]);
-+ printk("\n");
-+ RTW_INFO("Msg name: %s <======\n", msg_name);
-+}
-+
-+/* Porting from Windows team */
-+void rtw_btcoex_SendEventExtBtCoexControl(PADAPTER padapter, u8 bNeedDbgRsp, u8 dataLen, void *pData)
-+{
-+ u8 len = 0, tx_event_length = 0;
-+ u8 localBuf[32] = "";
-+ u8 *pRetPar;
-+ u8 opCode = 0;
-+ u8 *pInBuf = (pu1Byte)pData;
-+ u8 *pOpCodeContent;
-+ rtw_HCI_event *pEvent;
-+
-+ opCode = pInBuf[0];
-+
-+ RTW_INFO("%s, OPCode:%02x\n", __func__, opCode);
-+
-+ pEvent = (rtw_HCI_event *)(&localBuf[0]);
-+
-+ /* len += bthci_ExtensionEventHeaderRtk(&localBuf[0], */
-+ /* HCI_EVENT_EXT_BT_COEX_CONTROL); */
-+ pEvent->EventCode = HCI_EVENT_EXTENSION_RTK;
-+ pEvent->Data[0] = HCI_EVENT_EXT_BT_COEX_CONTROL; /* extension event code */
-+ len++;
-+
-+ /* Return parameters starts from here */
-+ pRetPar = &pEvent->Data[len];
-+ _rtw_memcpy(&pRetPar[0], pData, dataLen);
-+
-+ len += dataLen;
-+
-+ pEvent->Length = len;
-+
-+ /* total tx event length + EventCode length + sizeof(length) */
-+ tx_event_length = pEvent->Length + 2;
-+#if 0
-+ rtw_btcoex_dump_tx_msg((u8 *)pEvent, tx_event_length, "BT COEX CONTROL", _FALSE);
-+#endif
-+ rtw_btcoex_sendmsgbysocket(padapter, (u8 *)pEvent, tx_event_length, _FALSE);
-+
-+}
-+
-+/* Porting from Windows team */
-+void rtw_btcoex_SendEventExtBtInfoControl(PADAPTER padapter, u8 dataLen, void *pData)
-+{
-+ rtw_HCI_event *pEvent;
-+ u8 *pRetPar;
-+ u8 len = 0, tx_event_length = 0;
-+ u8 localBuf[32] = "";
-+
-+ struct bt_coex_info *pcoex_info = &padapter->coex_info;
-+ PBT_MGNT pBtMgnt = &pcoex_info->BtMgnt;
-+
-+ /* RTW_INFO("%s\n",__func__);*/
-+ if (pBtMgnt->ExtConfig.HCIExtensionVer < 4) { /* not support */
-+ RTW_INFO("ERROR: HCIExtensionVer = %d, HCIExtensionVer<4 !!!!\n", pBtMgnt->ExtConfig.HCIExtensionVer);
-+ return;
-+ }
-+
-+ pEvent = (rtw_HCI_event *)(&localBuf[0]);
-+
-+ /* len += bthci_ExtensionEventHeaderRtk(&localBuf[0], */
-+ /* HCI_EVENT_EXT_BT_INFO_CONTROL); */
-+ pEvent->EventCode = HCI_EVENT_EXTENSION_RTK;
-+ pEvent->Data[0] = HCI_EVENT_EXT_BT_INFO_CONTROL; /* extension event code */
-+ len++;
-+
-+ /* Return parameters starts from here */
-+ pRetPar = &pEvent->Data[len];
-+ _rtw_memcpy(&pRetPar[0], pData, dataLen);
-+
-+ len += dataLen;
-+
-+ pEvent->Length = len;
-+
-+ /* total tx event length + EventCode length + sizeof(length) */
-+ tx_event_length = pEvent->Length + 2;
-+#if 0
-+ rtw_btcoex_dump_tx_msg((u8 *)pEvent, tx_event_length, "BT INFO CONTROL");
-+#endif
-+ rtw_btcoex_sendmsgbysocket(padapter, (u8 *)pEvent, tx_event_length, _FALSE);
-+
-+}
-+
-+void rtw_btcoex_SendScanNotify(PADAPTER padapter, u8 scanType)
-+{
-+ u8 len = 0, tx_event_length = 0;
-+ u8 localBuf[7] = "";
-+ u8 *pRetPar;
-+ u8 *pu1Temp;
-+ rtw_HCI_event *pEvent;
-+ struct bt_coex_info *pcoex_info = &padapter->coex_info;
-+ PBT_MGNT pBtMgnt = &pcoex_info->BtMgnt;
-+
-+ /* if(!pBtMgnt->BtOperationOn)
-+ * return; */
-+
-+ pEvent = (rtw_HCI_event *)(&localBuf[0]);
-+
-+ /* len += bthci_ExtensionEventHeaderRtk(&localBuf[0],
-+ * HCI_EVENT_EXT_WIFI_SCAN_NOTIFY); */
-+
-+ pEvent->EventCode = HCI_EVENT_EXTENSION_RTK;
-+ pEvent->Data[0] = HCI_EVENT_EXT_WIFI_SCAN_NOTIFY; /* extension event code */
-+ len++;
-+
-+ /* Return parameters starts from here */
-+ /* pRetPar = &PPacketIrpEvent->Data[len]; */
-+ /* pu1Temp = (u8 *)&pRetPar[0]; */
-+ /* *pu1Temp = scanType; */
-+ pEvent->Data[len] = scanType;
-+ len += 1;
-+
-+ pEvent->Length = len;
-+
-+ /* total tx event length + EventCode length + sizeof(length) */
-+ tx_event_length = pEvent->Length + 2;
-+#if 0
-+ rtw_btcoex_dump_tx_msg((u8 *)pEvent, tx_event_length, "WIFI SCAN OPERATION");
-+#endif
-+ rtw_btcoex_sendmsgbysocket(padapter, (u8 *)pEvent, tx_event_length, _FALSE);
-+}
-+#endif /* CONFIG_BT_COEXIST_SOCKET_TRX */
-+#endif /* CONFIG_BT_COEXIST */
-+
-+void rtw_btcoex_set_ant_info(PADAPTER padapter)
-+{
-+#ifdef CONFIG_BT_COEXIST
-+ PHAL_DATA_TYPE hal = GET_HAL_DATA(padapter);
-+
-+ if (hal->EEPROMBluetoothCoexist == _TRUE) {
-+ u8 bMacPwrCtrlOn = _FALSE;
-+
-+ rtw_btcoex_AntInfoSetting(padapter);
-+ rtw_hal_get_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);
-+ if (bMacPwrCtrlOn == _TRUE)
-+ rtw_btcoex_PowerOnSetting(padapter);
-+ }
-+ else
-+#endif
-+ rtw_btcoex_wifionly_AntInfoSetting(padapter);
-+}
-+
-diff --git linux-5.8/3rdparty/rtl8812au/core/rtw_btcoex_wifionly.c linux-5.8/3rdparty/rtl8812au/core/rtw_btcoex_wifionly.c
-new file mode 100644
-index 000000000..d9872b022
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/core/rtw_btcoex_wifionly.c
-@@ -0,0 +1,47 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2013 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#include
-+#include
-+#include
-+
-+void rtw_btcoex_wifionly_switchband_notify(PADAPTER padapter)
-+{
-+ hal_btcoex_wifionly_switchband_notify(padapter);
-+}
-+
-+void rtw_btcoex_wifionly_scan_notify(PADAPTER padapter)
-+{
-+ hal_btcoex_wifionly_scan_notify(padapter);
-+}
-+
-+void rtw_btcoex_wifionly_connect_notify(PADAPTER padapter)
-+{
-+ hal_btcoex_wifionly_connect_notify(padapter);
-+}
-+
-+void rtw_btcoex_wifionly_hw_config(PADAPTER padapter)
-+{
-+ hal_btcoex_wifionly_hw_config(padapter);
-+}
-+
-+void rtw_btcoex_wifionly_initialize(PADAPTER padapter)
-+{
-+ hal_btcoex_wifionly_initlizevariables(padapter);
-+}
-+
-+void rtw_btcoex_wifionly_AntInfoSetting(PADAPTER padapter)
-+{
-+ hal_btcoex_wifionly_AntInfoSetting(padapter);
-+}
-diff --git linux-5.8/3rdparty/rtl8812au/core/rtw_chplan.c linux-5.8/3rdparty/rtl8812au/core/rtw_chplan.c
-new file mode 100644
-index 000000000..34263a5fd
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/core/rtw_chplan.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/core/rtw_chplan.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/core/rtw_chplan.c
+--- linux-5.11.4/3rdparty/rtl8812au/core/rtw_chplan.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/core/rtw_chplan.c 2021-03-07 18:16:17.018954351 +0200
@@ -0,0 +1,1193 @@
+/******************************************************************************
+ *
@@ -28835,11 +25910,9 @@ index 000000000..34263a5fd
+{
+ RTW_PRINT_SEL(sel, "%s-%s\n", RTW_DOMAIN_MAP_VER, RTW_COUNTRY_MAP_VER);
+}
-diff --git linux-5.8/3rdparty/rtl8812au/core/rtw_chplan.h linux-5.8/3rdparty/rtl8812au/core/rtw_chplan.h
-new file mode 100644
-index 000000000..cdf9f75b2
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/core/rtw_chplan.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/core/rtw_chplan.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/core/rtw_chplan.h
+--- linux-5.11.4/3rdparty/rtl8812au/core/rtw_chplan.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/core/rtw_chplan.h 2021-03-07 18:16:17.018954351 +0200
@@ -0,0 +1,181 @@
+/******************************************************************************
+ *
@@ -29022,11 +26095,9 @@ index 000000000..cdf9f75b2
+void dump_chplan_ver(void *sel);
+
+#endif /* __RTW_CHPLAN_H__ */
-diff --git linux-5.8/3rdparty/rtl8812au/core/rtw_cmd.c linux-5.8/3rdparty/rtl8812au/core/rtw_cmd.c
-new file mode 100644
-index 000000000..2984f9bea
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/core/rtw_cmd.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/core/rtw_cmd.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/core/rtw_cmd.c
+--- linux-5.11.4/3rdparty/rtl8812au/core/rtw_cmd.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/core/rtw_cmd.c 2021-03-07 18:16:17.018954351 +0200
@@ -0,0 +1,5765 @@
+/******************************************************************************
+ *
@@ -34793,11 +31864,9 @@ index 000000000..2984f9bea
+
+
+}
-diff --git linux-5.8/3rdparty/rtl8812au/core/rtw_debug.c linux-5.8/3rdparty/rtl8812au/core/rtw_debug.c
-new file mode 100644
-index 000000000..22ff44f8b
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/core/rtw_debug.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/core/rtw_debug.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/core/rtw_debug.c
+--- linux-5.11.4/3rdparty/rtl8812au/core/rtw_debug.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/core/rtw_debug.c 2021-03-07 18:16:17.019954399 +0200
@@ -0,0 +1,7096 @@
+/******************************************************************************
+ *
@@ -41895,11 +38964,9 @@ index 000000000..22ff44f8b
+ return count;
+}
+#endif /* CONFIG_RTW_SW_LED */
-diff --git linux-5.8/3rdparty/rtl8812au/core/rtw_eeprom.c linux-5.8/3rdparty/rtl8812au/core/rtw_eeprom.c
-new file mode 100644
-index 000000000..d48996e86
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/core/rtw_eeprom.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/core/rtw_eeprom.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/core/rtw_eeprom.c
+--- linux-5.11.4/3rdparty/rtl8812au/core/rtw_eeprom.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/core/rtw_eeprom.c 2021-03-07 18:16:17.019954399 +0200
@@ -0,0 +1,369 @@
+/******************************************************************************
+ *
@@ -42270,11 +39337,9 @@ index 000000000..d48996e86
+
+
+}
-diff --git linux-5.8/3rdparty/rtl8812au/core/rtw_ieee80211.c linux-5.8/3rdparty/rtl8812au/core/rtw_ieee80211.c
-new file mode 100644
-index 000000000..94e3d5985
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/core/rtw_ieee80211.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/core/rtw_ieee80211.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/core/rtw_ieee80211.c
+--- linux-5.11.4/3rdparty/rtl8812au/core/rtw_ieee80211.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/core/rtw_ieee80211.c 2021-03-07 18:16:17.019954399 +0200
@@ -0,0 +1,2934 @@
+/******************************************************************************
+ *
@@ -45210,11 +42275,9 @@ index 000000000..94e3d5985
+ return _action_public_str[action];
+}
+
-diff --git linux-5.8/3rdparty/rtl8812au/core/rtw_io.c linux-5.8/3rdparty/rtl8812au/core/rtw_io.c
-new file mode 100644
-index 000000000..5751c071a
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/core/rtw_io.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/core/rtw_io.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/core/rtw_io.c
+--- linux-5.11.4/3rdparty/rtl8812au/core/rtw_io.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/core/rtw_io.c 2021-03-07 18:16:17.019954399 +0200
@@ -0,0 +1,899 @@
+/******************************************************************************
+ *
@@ -46115,11 +43178,9 @@ index 000000000..5751c071a
+#endif /* CONFIG_SDIO_HCI */
+
+#endif
-diff --git linux-5.8/3rdparty/rtl8812au/core/rtw_ioctl_query.c linux-5.8/3rdparty/rtl8812au/core/rtw_ioctl_query.c
-new file mode 100644
-index 000000000..6f7613ecd
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/core/rtw_ioctl_query.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/core/rtw_ioctl_query.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/core/rtw_ioctl_query.c
+--- linux-5.11.4/3rdparty/rtl8812au/core/rtw_ioctl_query.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/core/rtw_ioctl_query.c 2021-03-07 18:16:17.019954399 +0200
@@ -0,0 +1,166 @@
+/******************************************************************************
+ *
@@ -46287,11 +43348,9 @@ index 000000000..6f7613ecd
+ return _TRUE;
+}
+#endif
-diff --git linux-5.8/3rdparty/rtl8812au/core/rtw_ioctl_rtl.c linux-5.8/3rdparty/rtl8812au/core/rtw_ioctl_rtl.c
-new file mode 100644
-index 000000000..5d9e76b60
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/core/rtw_ioctl_rtl.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/core/rtw_ioctl_rtl.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/core/rtw_ioctl_rtl.c
+--- linux-5.11.4/3rdparty/rtl8812au/core/rtw_ioctl_rtl.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/core/rtw_ioctl_rtl.c 2021-03-07 18:16:17.020954446 +0200
@@ -0,0 +1,901 @@
+/******************************************************************************
+ *
@@ -47194,11 +44253,9 @@ index 000000000..5d9e76b60
+ return status;
+}
+/* ************** oid_rtl_seg_03_00 section end ************** */
-diff --git linux-5.8/3rdparty/rtl8812au/core/rtw_ioctl_set.c linux-5.8/3rdparty/rtl8812au/core/rtw_ioctl_set.c
-new file mode 100644
-index 000000000..1b91233fe
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/core/rtw_ioctl_set.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/core/rtw_ioctl_set.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/core/rtw_ioctl_set.c
+--- linux-5.11.4/3rdparty/rtl8812au/core/rtw_ioctl_set.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/core/rtw_ioctl_set.c 2021-03-07 18:16:17.020954446 +0200
@@ -0,0 +1,930 @@
+/******************************************************************************
+ *
@@ -48130,11 +45187,9 @@ index 000000000..1b91233fe
+ RTW_PRINT(FUNC_ADPT_FMT" band:%d fail\n", FUNC_ADPT_ARG(adapter), band);
+ return _FAIL;
+}
-diff --git linux-5.8/3rdparty/rtl8812au/core/rtw_iol.c linux-5.8/3rdparty/rtl8812au/core/rtw_iol.c
-new file mode 100644
-index 000000000..643ec6c1d
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/core/rtw_iol.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/core/rtw_iol.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/core/rtw_iol.c
+--- linux-5.11.4/3rdparty/rtl8812au/core/rtw_iol.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/core/rtw_iol.c 2021-03-07 18:16:17.020954446 +0200
@@ -0,0 +1,394 @@
+/******************************************************************************
+ *
@@ -48530,11 +45585,9 @@ index 000000000..643ec6c1d
+
+
+#endif /* CONFIG_IOL */
-diff --git linux-5.8/3rdparty/rtl8812au/core/rtw_mem.c linux-5.8/3rdparty/rtl8812au/core/rtw_mem.c
-new file mode 100644
-index 000000000..d9f5652f9
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/core/rtw_mem.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/core/rtw_mem.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/core/rtw_mem.c
+--- linux-5.11.4/3rdparty/rtl8812au/core/rtw_mem.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/core/rtw_mem.c 2021-03-07 18:16:17.020954446 +0200
@@ -0,0 +1,128 @@
+/******************************************************************************
+ *
@@ -48664,11 +45717,9 @@ index 000000000..d9f5652f9
+
+module_init(rtw_mem_init);
+module_exit(rtw_mem_exit);
-diff --git linux-5.8/3rdparty/rtl8812au/core/rtw_mi.c linux-5.8/3rdparty/rtl8812au/core/rtw_mi.c
-new file mode 100644
-index 000000000..2a9added7
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/core/rtw_mi.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/core/rtw_mi.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/core/rtw_mi.c
+--- linux-5.11.4/3rdparty/rtl8812au/core/rtw_mi.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/core/rtw_mi.c 2021-03-07 18:16:17.020954446 +0200
@@ -0,0 +1,1571 @@
+/******************************************************************************
+ *
@@ -50241,11 +47292,9 @@ index 000000000..2a9added7
+#endif
+ return n_assoc_iface;
+}
-diff --git linux-5.8/3rdparty/rtl8812au/core/rtw_mlme.c linux-5.8/3rdparty/rtl8812au/core/rtw_mlme.c
-new file mode 100644
-index 000000000..8cc28c648
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/core/rtw_mlme.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/core/rtw_mlme.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/core/rtw_mlme.c
+--- linux-5.11.4/3rdparty/rtl8812au/core/rtw_mlme.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/core/rtw_mlme.c 2021-03-07 18:16:17.021954493 +0200
@@ -0,0 +1,5359 @@
+/******************************************************************************
+ *
@@ -55606,11 +52655,9 @@ index 000000000..8cc28c648
+ , MAC_ARG(ARP_TARGET_MAC_ADDR(arp)), IP_ARG(ARP_TARGET_IP_ADDR(arp)));
+}
+
-diff --git linux-5.8/3rdparty/rtl8812au/core/rtw_mlme_ext.c linux-5.8/3rdparty/rtl8812au/core/rtw_mlme_ext.c
-new file mode 100644
-index 000000000..01136fb37
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/core/rtw_mlme_ext.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/core/rtw_mlme_ext.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/core/rtw_mlme_ext.c
+--- linux-5.11.4/3rdparty/rtl8812au/core/rtw_mlme_ext.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/core/rtw_mlme_ext.c 2021-03-07 18:16:17.023954587 +0200
@@ -0,0 +1,16825 @@
+/******************************************************************************
+ *
@@ -72437,11 +69484,9 @@ index 000000000..01136fb37
+#endif /* CONFIG_IOCTL_CFG80211 */
+}
+
-diff --git linux-5.8/3rdparty/rtl8812au/core/rtw_mp.c linux-5.8/3rdparty/rtl8812au/core/rtw_mp.c
-new file mode 100644
-index 000000000..aca3e8b4b
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/core/rtw_mp.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/core/rtw_mp.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/core/rtw_mp.c
+--- linux-5.11.4/3rdparty/rtl8812au/core/rtw_mp.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/core/rtw_mp.c 2021-03-07 18:16:17.023954587 +0200
@@ -0,0 +1,3867 @@
+/******************************************************************************
+ *
@@ -76310,11 +73355,9 @@ index 000000000..aca3e8b4b
+
+#endif
+#endif
-diff --git linux-5.8/3rdparty/rtl8812au/core/rtw_mp_ioctl.c linux-5.8/3rdparty/rtl8812au/core/rtw_mp_ioctl.c
-new file mode 100644
-index 000000000..035d2815d
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/core/rtw_mp_ioctl.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/core/rtw_mp_ioctl.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/core/rtw_mp_ioctl.c
+--- linux-5.11.4/3rdparty/rtl8812au/core/rtw_mp_ioctl.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/core/rtw_mp_ioctl.c 2021-03-07 18:16:17.023954587 +0200
@@ -0,0 +1,2529 @@
+/******************************************************************************
+ *
@@ -78845,11 +75888,9 @@ index 000000000..035d2815d
+ return 0;
+#endif
+}
-diff --git linux-5.8/3rdparty/rtl8812au/core/rtw_odm.c linux-5.8/3rdparty/rtl8812au/core/rtw_odm.c
-new file mode 100644
-index 000000000..720418116
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/core/rtw_odm.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/core/rtw_odm.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/core/rtw_odm.c
+--- linux-5.11.4/3rdparty/rtl8812au/core/rtw_odm.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/core/rtw_odm.c 2021-03-07 18:16:17.023954587 +0200
@@ -0,0 +1,420 @@
+/******************************************************************************
+ *
@@ -79271,11 +76312,9 @@ index 000000000..720418116
+
+}
+
-diff --git linux-5.8/3rdparty/rtl8812au/core/rtw_p2p.c linux-5.8/3rdparty/rtl8812au/core/rtw_p2p.c
-new file mode 100644
-index 000000000..f66fa7155
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/core/rtw_p2p.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/core/rtw_p2p.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/core/rtw_p2p.c
+--- linux-5.11.4/3rdparty/rtl8812au/core/rtw_p2p.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/core/rtw_p2p.c 2021-03-07 18:16:17.024954635 +0200
@@ -0,0 +1,5456 @@
+/******************************************************************************
+ *
@@ -84733,11 +81772,9 @@ index 000000000..f66fa7155
+}
+
+#endif /* CONFIG_P2P */
-diff --git linux-5.8/3rdparty/rtl8812au/core/rtw_pwrctrl.c linux-5.8/3rdparty/rtl8812au/core/rtw_pwrctrl.c
-new file mode 100644
-index 000000000..b7d6dca29
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/core/rtw_pwrctrl.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/core/rtw_pwrctrl.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/core/rtw_pwrctrl.c
+--- linux-5.11.4/3rdparty/rtl8812au/core/rtw_pwrctrl.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/core/rtw_pwrctrl.c 2021-03-07 18:16:17.024954635 +0200
@@ -0,0 +1,2765 @@
+/******************************************************************************
+ *
@@ -87504,11 +84541,9 @@ index 000000000..b7d6dca29
+ _rtw_ssmps(adapter, sta);
+}
+
-diff --git linux-5.8/3rdparty/rtl8812au/core/rtw_recv.c linux-5.8/3rdparty/rtl8812au/core/rtw_recv.c
-new file mode 100644
-index 000000000..83fa1429f
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/core/rtw_recv.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/core/rtw_recv.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/core/rtw_recv.c
+--- linux-5.11.4/3rdparty/rtl8812au/core/rtw_recv.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/core/rtw_recv.c 2021-03-07 18:16:17.025954682 +0200
@@ -0,0 +1,5141 @@
+/******************************************************************************
+ *
@@ -91502,7 +88537,7 @@ index 000000000..83fa1429f
+
+ u8 data_rate[] = {
+ 2, 4, 11, 22, /* CCK */
-+ 12, 18, 24, 36, 48, 72, 93, 108, /* OFDM */
++ 12, 18, 24, 36, 48, 72, 96, 108, /* OFDM */
+ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, /* HT MCS index */
+ 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
+ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, /* VHT Nss 1 */
@@ -92651,12 +89686,10 @@ index 000000000..83fa1429f
+ );
+}
+#endif /* DBG_RX_BH_TRACKING */
-diff --git linux-5.8/3rdparty/rtl8812au/core/rtw_rf.c linux-5.8/3rdparty/rtl8812au/core/rtw_rf.c
-new file mode 100644
-index 000000000..ab4c31828
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/core/rtw_rf.c
-@@ -0,0 +1,1384 @@
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/core/rtw_rf.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/core/rtw_rf.c
+--- linux-5.11.4/3rdparty/rtl8812au/core/rtw_rf.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/core/rtw_rf.c 2021-03-07 18:16:17.025954682 +0200
+@@ -0,0 +1,1394 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
@@ -92710,6 +89743,8 @@ index 000000000..ab4c31828
+};
+
+u8 center_ch_5g_all[CENTER_CH_5G_ALL_NUM] = {
++ 15, 16, 17, 18,
++ 20, 24, 28, 32,
+/* G00 */36, 38, 40,
+ 42,
+/* G01 */44, 46, 48,
@@ -92717,6 +89752,8 @@ index 000000000..ab4c31828
+/* G02 */52, 54, 56,
+ 58,
+/* G03 */60, 62, 64,
++ 68, 72, 76, 80,
++ 84, 88, 92, 96,
+/* G04 */100, 102, 104,
+ 106,
+/* G05 */108, 110, 112,
@@ -92737,10 +89774,14 @@ index 000000000..ab4c31828
+};
+
+u8 center_ch_5g_20m[CENTER_CH_5G_20M_NUM] = {
++ 15, 16, 17, 18,
++ 20, 24, 28, 32,
+/* G00 */36, 40,
+/* G01 */44, 48,
+/* G02 */52, 56,
+/* G03 */60, 64,
++ 68, 72, 76, 80,
++ 84, 88, 92, 96,
+/* G04 */100, 104,
+/* G05 */108, 112,
+/* G06 */116, 120,
@@ -92770,6 +89811,7 @@ index 000000000..ab4c31828
+/* G13 */175
+};
+
++#if 0
+u8 center_ch_5g_20m_40m[CENTER_CH_5G_20M_NUM + CENTER_CH_5G_40M_NUM] = {
+/* G00 */36, 38, 40,
+/* G01 */44, 46, 48,
@@ -92786,6 +89828,7 @@ index 000000000..ab4c31828
+/* G12 */165, 167, 169,
+/* G13 */173, 175, 177
+};
++#endif
+
+u8 op_chs_of_cch_5g_40m[CENTER_CH_5G_40M_NUM][2] = {
+ {36, 40}, /* 38 */
@@ -93035,15 +90078,15 @@ index 000000000..ab4c31828
+ } else {
+ band = BAND_ON_5G;
+
-+ if (36 <= ch && ch <= 42)
++ if (15 <= ch && ch <= 42)
+ gp = 0;
+ else if (44 <= ch && ch <= 48)
+ gp = 1;
+ else if (50 <= ch && ch <= 58)
+ gp = 2;
-+ else if (60 <= ch && ch <= 64)
++ else if (60 <= ch && ch <= 80)
+ gp = 3;
-+ else if (100 <= ch && ch <= 106)
++ else if (82 <= ch && ch <= 106)
+ gp = 4;
+ else if (108 <= ch && ch <= 114)
+ gp = 5;
@@ -94041,11 +91084,9 @@ index 000000000..ab4c31828
+
+ return rtw_is_long_cac_range(hi, lo, dfs_region) ? _TRUE : _FALSE;
+}
-diff --git linux-5.8/3rdparty/rtl8812au/core/rtw_rm.c linux-5.8/3rdparty/rtl8812au/core/rtw_rm.c
-new file mode 100644
-index 000000000..6576597b1
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/core/rtw_rm.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/core/rtw_rm.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/core/rtw_rm.c
+--- linux-5.11.4/3rdparty/rtl8812au/core/rtw_rm.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/core/rtw_rm.c 2021-03-07 18:16:17.025954682 +0200
@@ -0,0 +1,2470 @@
+/******************************************************************************
+ *
@@ -96517,11 +93558,9 @@ index 000000000..6576597b1
+#endif
+}
+#endif /* CONFIG_RTW_80211K */
-diff --git linux-5.8/3rdparty/rtl8812au/core/rtw_rm_fsm.c linux-5.8/3rdparty/rtl8812au/core/rtw_rm_fsm.c
-new file mode 100644
-index 000000000..21fb323bc
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/core/rtw_rm_fsm.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/core/rtw_rm_fsm.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/core/rtw_rm_fsm.c
+--- linux-5.11.4/3rdparty/rtl8812au/core/rtw_rm_fsm.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/core/rtw_rm_fsm.c 2021-03-07 18:16:17.025954682 +0200
@@ -0,0 +1,998 @@
+/******************************************************************************
+ *
@@ -97521,11 +94560,9 @@ index 000000000..21fb323bc
+ rm_state_run(prm, RM_EV_state_in);
+}
+#endif /* CONFIG_RTW_80211K */
-diff --git linux-5.8/3rdparty/rtl8812au/core/rtw_rson.c linux-5.8/3rdparty/rtl8812au/core/rtw_rson.c
-new file mode 100644
-index 000000000..4fbdbb5e8
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/core/rtw_rson.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/core/rtw_rson.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/core/rtw_rson.c
+--- linux-5.11.4/3rdparty/rtl8812au/core/rtw_rson.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/core/rtw_rson.c 2021-03-07 18:16:17.025954682 +0200
@@ -0,0 +1,595 @@
+/******************************************************************************
+ *
@@ -98122,11 +95159,9 @@ index 000000000..4fbdbb5e8
+}
+
+#endif /* CONFIG_RTW_REPEATER_SON */
-diff --git linux-5.8/3rdparty/rtl8812au/core/rtw_sdio.c linux-5.8/3rdparty/rtl8812au/core/rtw_sdio.c
-new file mode 100644
-index 000000000..e8f49bfc3
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/core/rtw_sdio.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/core/rtw_sdio.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/core/rtw_sdio.c
+--- linux-5.11.4/3rdparty/rtl8812au/core/rtw_sdio.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/core/rtw_sdio.c 2021-03-07 18:16:17.025954682 +0200
@@ -0,0 +1,130 @@
+/******************************************************************************
+ *
@@ -98258,11 +95293,9 @@ index 000000000..e8f49bfc3
+
+ return ret;
+}
-diff --git linux-5.8/3rdparty/rtl8812au/core/rtw_security.c linux-5.8/3rdparty/rtl8812au/core/rtw_security.c
-new file mode 100644
-index 000000000..eb08ef580
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/core/rtw_security.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/core/rtw_security.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/core/rtw_security.c
+--- linux-5.11.4/3rdparty/rtl8812au/core/rtw_security.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/core/rtw_security.c 2021-03-07 18:16:17.026954729 +0200
@@ -0,0 +1,3122 @@
+/******************************************************************************
+ *
@@ -101386,11 +98419,9 @@ index 000000000..eb08ef580
+ return crc;
+}
+#endif /*CONFIG_WOWLAN*/
-diff --git linux-5.8/3rdparty/rtl8812au/core/rtw_sreset.c linux-5.8/3rdparty/rtl8812au/core/rtw_sreset.c
-new file mode 100644
-index 000000000..03dba20f3
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/core/rtw_sreset.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/core/rtw_sreset.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/core/rtw_sreset.c
+--- linux-5.11.4/3rdparty/rtl8812au/core/rtw_sreset.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/core/rtw_sreset.c 2021-03-07 18:16:17.026954729 +0200
@@ -0,0 +1,314 @@
+/******************************************************************************
+ *
@@ -101706,11 +98737,9 @@ index 000000000..03dba20f3
+ psrtpriv->rx_cnt = 0;
+#endif
+}
-diff --git linux-5.8/3rdparty/rtl8812au/core/rtw_sta_mgt.c linux-5.8/3rdparty/rtl8812au/core/rtw_sta_mgt.c
-new file mode 100644
-index 000000000..f8c390dec
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/core/rtw_sta_mgt.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/core/rtw_sta_mgt.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/core/rtw_sta_mgt.c
+--- linux-5.11.4/3rdparty/rtl8812au/core/rtw_sta_mgt.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/core/rtw_sta_mgt.c 2021-03-07 18:16:17.026954729 +0200
@@ -0,0 +1,1323 @@
+/******************************************************************************
+ *
@@ -103035,11 +100064,9 @@ index 000000000..f8c390dec
+}
+#endif /* CONFIG_RTW_PRE_LINK_STA */
+
-diff --git linux-5.8/3rdparty/rtl8812au/core/rtw_tdls.c linux-5.8/3rdparty/rtl8812au/core/rtw_tdls.c
-new file mode 100644
-index 000000000..4cb38921c
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/core/rtw_tdls.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/core/rtw_tdls.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/core/rtw_tdls.c
+--- linux-5.11.4/3rdparty/rtl8812au/core/rtw_tdls.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/core/rtw_tdls.c 2021-03-07 18:16:17.026954729 +0200
@@ -0,0 +1,3505 @@
+/******************************************************************************
+ *
@@ -106546,1152 +103573,9 @@ index 000000000..4cb38921c
+}
+
+#endif /* CONFIG_TDLS */
-diff --git linux-5.8/3rdparty/rtl8812au/core/rtw_vht.c linux-5.8/3rdparty/rtl8812au/core/rtw_vht.c
-new file mode 100644
-index 000000000..9a7608c8e
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/core/rtw_vht.c
-@@ -0,0 +1,1135 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#define _RTW_VHT_C
-+
-+#include
-+#include
-+
-+#ifdef CONFIG_80211AC_VHT
-+const u16 _vht_max_mpdu_len[] = {
-+ 3895,
-+ 7991,
-+ 11454,
-+ 0,
-+};
-+
-+const u8 _vht_sup_ch_width_set_to_bw_cap[] = {
-+ BW_CAP_80M,
-+ BW_CAP_80M | BW_CAP_160M,
-+ BW_CAP_80M | BW_CAP_160M | BW_CAP_80_80M,
-+ 0,
-+};
-+
-+const char *const _vht_sup_ch_width_set_str[] = {
-+ "80MHz",
-+ "160MHz",
-+ "160MHz & 80+80MHz",
-+ "BW-RSVD",
-+};
-+
-+void dump_vht_cap_ie_content(void *sel, const u8 *buf, u32 buf_len)
-+{
-+ if (buf_len != VHT_CAP_IE_LEN) {
-+ RTW_PRINT_SEL(sel, "Invalid VHT capability IE len:%d != %d\n", buf_len, VHT_CAP_IE_LEN);
-+ return;
-+ }
-+
-+ RTW_PRINT_SEL(sel, "cap_info:%02x %02x %02x %02x: MAX_MPDU_LEN:%u %s%s%s%s%s RX-STBC:%u MAX_AMPDU_LEN:%u\n"
-+ , *(buf), *(buf + 1), *(buf + 2), *(buf + 3)
-+ , vht_max_mpdu_len(GET_VHT_CAPABILITY_ELE_MAX_MPDU_LENGTH(buf))
-+ , vht_sup_ch_width_set_str(GET_VHT_CAPABILITY_ELE_CHL_WIDTH(buf))
-+ , GET_VHT_CAPABILITY_ELE_RX_LDPC(buf) ? " RX-LDPC" : ""
-+ , GET_VHT_CAPABILITY_ELE_SHORT_GI80M(buf) ? " SGI-80" : ""
-+ , GET_VHT_CAPABILITY_ELE_SHORT_GI160M(buf) ? " SGI-160" : ""
-+ , GET_VHT_CAPABILITY_ELE_TX_STBC(buf) ? " TX-STBC" : ""
-+ , GET_VHT_CAPABILITY_ELE_RX_STBC(buf)
-+ , VHT_MAX_AMPDU_LEN(GET_VHT_CAPABILITY_ELE_MAX_RXAMPDU_FACTOR(buf))
-+ );
-+}
-+
-+void dump_vht_cap_ie(void *sel, const u8 *ie, u32 ie_len)
-+{
-+ const u8 *vht_cap_ie;
-+ sint vht_cap_ielen;
-+
-+ vht_cap_ie = rtw_get_ie(ie, WLAN_EID_VHT_CAPABILITY, &vht_cap_ielen, ie_len);
-+ if (!ie || vht_cap_ie != ie)
-+ return;
-+
-+ dump_vht_cap_ie_content(sel, vht_cap_ie + 2, vht_cap_ielen);
-+}
-+
-+const char *const _vht_op_ch_width_str[] = {
-+ "20 or 40MHz",
-+ "80MHz",
-+ "160MHz",
-+ "80+80MHz",
-+ "BW-RSVD",
-+};
-+
-+void dump_vht_op_ie_content(void *sel, const u8 *buf, u32 buf_len)
-+{
-+ if (buf_len != VHT_OP_IE_LEN) {
-+ RTW_PRINT_SEL(sel, "Invalid VHT operation IE len:%d != %d\n", buf_len, VHT_OP_IE_LEN);
-+ return;
-+ }
-+
-+ RTW_PRINT_SEL(sel, "%s, ch0:%u, ch1:%u\n"
-+ , vht_op_ch_width_str(GET_VHT_OPERATION_ELE_CHL_WIDTH(buf))
-+ , GET_VHT_OPERATION_ELE_CENTER_FREQ1(buf)
-+ , GET_VHT_OPERATION_ELE_CENTER_FREQ2(buf)
-+ );
-+}
-+
-+void dump_vht_op_ie(void *sel, const u8 *ie, u32 ie_len)
-+{
-+ const u8 *vht_op_ie;
-+ sint vht_op_ielen;
-+
-+ vht_op_ie = rtw_get_ie(ie, WLAN_EID_VHT_OPERATION, &vht_op_ielen, ie_len);
-+ if (!ie || vht_op_ie != ie)
-+ return;
-+
-+ dump_vht_op_ie_content(sel, vht_op_ie + 2, vht_op_ielen);
-+}
-+
-+/* 20/40/80, ShortGI, MCS Rate */
-+const u16 VHT_MCS_DATA_RATE[3][2][30] = {
-+ { {
-+ 13, 26, 39, 52, 78, 104, 117, 130, 156, 156,
-+ 26, 52, 78, 104, 156, 208, 234, 260, 312, 312,
-+ 39, 78, 117, 156, 234, 312, 351, 390, 468, 520
-+ }, /* Long GI, 20MHz */
-+ {
-+ 14, 29, 43, 58, 87, 116, 130, 144, 173, 173,
-+ 29, 58, 87, 116, 173, 231, 260, 289, 347, 347,
-+ 43, 87, 130, 173, 260, 347, 390, 433, 520, 578
-+ }
-+ }, /* Short GI, 20MHz */
-+ { {
-+ 27, 54, 81, 108, 162, 216, 243, 270, 324, 360,
-+ 54, 108, 162, 216, 324, 432, 486, 540, 648, 720,
-+ 81, 162, 243, 324, 486, 648, 729, 810, 972, 1080
-+ }, /* Long GI, 40MHz */
-+ {
-+ 30, 60, 90, 120, 180, 240, 270, 300, 360, 400,
-+ 60, 120, 180, 240, 360, 480, 540, 600, 720, 800,
-+ 90, 180, 270, 360, 540, 720, 810, 900, 1080, 1200
-+ }
-+ }, /* Short GI, 40MHz */
-+ { {
-+ 59, 117, 176, 234, 351, 468, 527, 585, 702, 780,
-+ 117, 234, 351, 468, 702, 936, 1053, 1170, 1404, 1560,
-+ 176, 351, 527, 702, 1053, 1404, 1580, 1755, 2106, 2340
-+ }, /* Long GI, 80MHz */
-+ {
-+ 65, 130, 195, 260, 390, 520, 585, 650, 780, 867,
-+ 130, 260, 390, 520, 780, 1040, 1170, 1300, 1560, 1734,
-+ 195, 390, 585, 780, 1170, 1560, 1755, 1950, 2340, 2600
-+ }
-+ } /* Short GI, 80MHz */
-+};
-+
-+u8 rtw_get_vht_highest_rate(u8 *pvht_mcs_map)
-+{
-+ u8 i, j;
-+ u8 bit_map;
-+ u8 vht_mcs_rate = 0;
-+
-+ for (i = 0; i < 2; i++) {
-+ if (pvht_mcs_map[i] != 0xff) {
-+ for (j = 0; j < 8; j += 2) {
-+ bit_map = (pvht_mcs_map[i] >> j) & 3;
-+
-+ if (bit_map != 3)
-+ vht_mcs_rate = MGN_VHT1SS_MCS7 + 10 * j / 2 + i * 40 + bit_map; /* VHT rate indications begin from 0x90 */
-+ }
-+ }
-+ }
-+
-+ /* RTW_INFO("HighestVHTMCSRate is %x\n", vht_mcs_rate); */
-+ return vht_mcs_rate;
-+}
-+
-+u8 rtw_vht_mcsmap_to_nss(u8 *pvht_mcs_map)
-+{
-+ u8 i, j;
-+ u8 bit_map;
-+ u8 nss = 0;
-+
-+ for (i = 0; i < 2; i++) {
-+ if (pvht_mcs_map[i] != 0xff) {
-+ for (j = 0; j < 8; j += 2) {
-+ bit_map = (pvht_mcs_map[i] >> j) & 3;
-+
-+ if (bit_map != 3)
-+ nss++;
-+ }
-+ }
-+ }
-+
-+ /* RTW_INFO("%s : %dSS\n", __FUNCTION__, nss); */
-+ return nss;
-+}
-+
-+void rtw_vht_nss_to_mcsmap(u8 nss, u8 *target_mcs_map, u8 *cur_mcs_map)
-+{
-+ u8 i, j;
-+ u8 cur_rate, target_rate;
-+
-+ for (i = 0; i < 2; i++) {
-+ target_mcs_map[i] = 0;
-+ for (j = 0; j < 8; j += 2) {
-+ cur_rate = (cur_mcs_map[i] >> j) & 3;
-+ if (cur_rate == 3) /* 0x3 indicates not supported that num of SS */
-+ target_rate = 3;
-+ else if (nss <= ((j / 2) + i * 4))
-+ target_rate = 3;
-+ else
-+ target_rate = cur_rate;
-+
-+ target_mcs_map[i] |= (target_rate << j);
-+ }
-+ }
-+
-+ /* RTW_INFO("%s : %dSS\n", __FUNCTION__, nss); */
-+}
-+
-+u16 rtw_vht_mcs_to_data_rate(u8 bw, u8 short_GI, u8 vht_mcs_rate)
-+{
-+ if (vht_mcs_rate > MGN_VHT3SS_MCS9)
-+ vht_mcs_rate = MGN_VHT3SS_MCS9;
-+ /* RTW_INFO("bw=%d, short_GI=%d, ((vht_mcs_rate - MGN_VHT1SS_MCS0)&0x3f)=%d\n", bw, short_GI, ((vht_mcs_rate - MGN_VHT1SS_MCS0)&0x3f)); */
-+ return VHT_MCS_DATA_RATE[bw][short_GI][((vht_mcs_rate - MGN_VHT1SS_MCS0) & 0x3f)];
-+}
-+
-+void rtw_vht_use_default_setting(_adapter *padapter)
-+{
-+ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
-+ struct vht_priv *pvhtpriv = &pmlmepriv->vhtpriv;
-+ struct registry_priv *pregistrypriv = &padapter->registrypriv;
-+ BOOLEAN bHwLDPCSupport = _FALSE, bHwSTBCSupport = _FALSE;
-+#ifdef CONFIG_BEAMFORMING
-+ BOOLEAN bHwSupportBeamformer = _FALSE, bHwSupportBeamformee = _FALSE;
-+ u8 mu_bfer, mu_bfee;
-+#endif /* CONFIG_BEAMFORMING */
-+ u8 rf_type = 0;
-+ u8 tx_nss, rx_nss;
-+ struct hal_spec_t *hal_spec = GET_HAL_SPEC(padapter);
-+ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
-+ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
-+ pvhtpriv->sgi_80m = TEST_FLAG(pregistrypriv->short_gi, BIT2) ? _TRUE : _FALSE;
-+
-+ /* LDPC support */
-+ rtw_hal_get_def_var(padapter, HAL_DEF_RX_LDPC, (u8 *)&bHwLDPCSupport);
-+ CLEAR_FLAGS(pvhtpriv->ldpc_cap);
-+ if (bHwLDPCSupport) {
-+ if (TEST_FLAG(pregistrypriv->ldpc_cap, BIT0))
-+ SET_FLAG(pvhtpriv->ldpc_cap, LDPC_VHT_ENABLE_RX);
-+ }
-+ rtw_hal_get_def_var(padapter, HAL_DEF_TX_LDPC, (u8 *)&bHwLDPCSupport);
-+ if (bHwLDPCSupport) {
-+ if (TEST_FLAG(pregistrypriv->ldpc_cap, BIT1))
-+ SET_FLAG(pvhtpriv->ldpc_cap, LDPC_VHT_ENABLE_TX);
-+ }
-+ if (pvhtpriv->ldpc_cap)
-+ RTW_INFO("[VHT] Support LDPC = 0x%02X\n", pvhtpriv->ldpc_cap);
-+
-+ /* STBC */
-+ rtw_hal_get_def_var(padapter, HAL_DEF_TX_STBC, (u8 *)&bHwSTBCSupport);
-+ CLEAR_FLAGS(pvhtpriv->stbc_cap);
-+ if (bHwSTBCSupport) {
-+ if (TEST_FLAG(pregistrypriv->stbc_cap, BIT1))
-+ SET_FLAG(pvhtpriv->stbc_cap, STBC_VHT_ENABLE_TX);
-+ }
-+ rtw_hal_get_def_var(padapter, HAL_DEF_RX_STBC, (u8 *)&bHwSTBCSupport);
-+ if (bHwSTBCSupport) {
-+ if (TEST_FLAG(pregistrypriv->stbc_cap, BIT0))
-+ SET_FLAG(pvhtpriv->stbc_cap, STBC_VHT_ENABLE_RX);
-+ }
-+ if (pvhtpriv->stbc_cap)
-+ RTW_INFO("[VHT] Support STBC = 0x%02X\n", pvhtpriv->stbc_cap);
-+
-+ /* Beamforming setting */
-+ CLEAR_FLAGS(pvhtpriv->beamform_cap);
-+#ifdef CONFIG_BEAMFORMING
-+#ifdef RTW_BEAMFORMING_VERSION_2
-+ /* only enable beamforming in STA client mode */
-+ if (MLME_IS_STA(padapter) && !MLME_IS_GC(padapter)
-+ && !MLME_IS_ADHOC(padapter)
-+ && !MLME_IS_MESH(padapter))
-+#endif
-+ {
-+ rtw_hal_get_def_var(padapter, HAL_DEF_EXPLICIT_BEAMFORMER,
-+ (u8 *)&bHwSupportBeamformer);
-+ rtw_hal_get_def_var(padapter, HAL_DEF_EXPLICIT_BEAMFORMEE,
-+ (u8 *)&bHwSupportBeamformee);
-+ mu_bfer = _FALSE;
-+ mu_bfee = _FALSE;
-+ rtw_hal_get_def_var(padapter, HAL_DEF_VHT_MU_BEAMFORMER, &mu_bfer);
-+ rtw_hal_get_def_var(padapter, HAL_DEF_VHT_MU_BEAMFORMEE, &mu_bfee);
-+ if (TEST_FLAG(pregistrypriv->beamform_cap, BIT0) && bHwSupportBeamformer) {
-+#ifdef CONFIG_CONCURRENT_MODE
-+ if ((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE) {
-+ SET_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_BEAMFORMER_ENABLE);
-+ RTW_INFO("[VHT] CONCURRENT AP Support Beamformer\n");
-+ if (TEST_FLAG(pregistrypriv->beamform_cap, BIT(2))
-+ && (_TRUE == mu_bfer)) {
-+ SET_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_MU_MIMO_AP_ENABLE);
-+ RTW_INFO("[VHT] Support MU-MIMO AP\n");
-+ }
-+ } else
-+ RTW_INFO("[VHT] CONCURRENT not AP ;not allow Support Beamformer\n");
-+#else
-+ SET_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_BEAMFORMER_ENABLE);
-+ RTW_INFO("[VHT] Support Beamformer\n");
-+ if (TEST_FLAG(pregistrypriv->beamform_cap, BIT(2))
-+ && (_TRUE == mu_bfer)
-+ && ((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE)) {
-+ SET_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_MU_MIMO_AP_ENABLE);
-+ RTW_INFO("[VHT] Support MU-MIMO AP\n");
-+ }
-+#endif
-+ }
-+ if (TEST_FLAG(pregistrypriv->beamform_cap, BIT1) && bHwSupportBeamformee) {
-+ SET_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_BEAMFORMEE_ENABLE);
-+ RTW_INFO("[VHT] Support Beamformee\n");
-+ if (TEST_FLAG(pregistrypriv->beamform_cap, BIT(3))
-+ && (_TRUE == mu_bfee)
-+ && ((pmlmeinfo->state & 0x03) != WIFI_FW_AP_STATE)) {
-+ SET_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_MU_MIMO_STA_ENABLE);
-+ RTW_INFO("[VHT] Support MU-MIMO STA\n");
-+ }
-+ }
-+ }
-+#endif /* CONFIG_BEAMFORMING */
-+
-+ pvhtpriv->ampdu_len = pregistrypriv->ampdu_factor;
-+
-+ rtw_hal_get_hwreg(padapter, HW_VAR_RF_TYPE, (u8 *)(&rf_type));
-+ tx_nss = rtw_min(rf_type_to_rf_tx_cnt(rf_type), hal_spec->tx_nss_num);
-+ rx_nss = rtw_min(rf_type_to_rf_rx_cnt(rf_type), hal_spec->rx_nss_num);
-+
-+ /* for now, vhtpriv.vht_mcs_map comes from RX NSS */
-+ rtw_vht_nss_to_mcsmap(rx_nss, pvhtpriv->vht_mcs_map, pregistrypriv->vht_rx_mcs_map);
-+ pvhtpriv->vht_highest_rate = rtw_get_vht_highest_rate(pvhtpriv->vht_mcs_map);
-+}
-+
-+u64 rtw_vht_mcs_map_to_bitmap(u8 *mcs_map, u8 nss)
-+{
-+ u8 i, j, tmp;
-+ u64 bitmap = 0;
-+ u8 bits_nss = nss * 2;
-+
-+ for (i = j = 0; i < bits_nss; i += 2, j += 10) {
-+ /* every two bits means single sptial stream */
-+ tmp = (mcs_map[i / 8] >> i) & 3;
-+
-+ switch (tmp) {
-+ case 2:
-+ bitmap = bitmap | (0x03ff << j);
-+ break;
-+ case 1:
-+ bitmap = bitmap | (0x01ff << j);
-+ break;
-+ case 0:
-+ bitmap = bitmap | (0x00ff << j);
-+ break;
-+ default:
-+ break;
-+ }
-+ }
-+
-+ RTW_INFO("vht_mcs_map=%02x %02x, nss=%u => bitmap=%016llx\n"
-+ , mcs_map[0], mcs_map[1], nss, bitmap);
-+
-+ return bitmap;
-+}
-+
-+#ifdef CONFIG_BEAMFORMING
-+void update_sta_vht_info_apmode_bf_cap(_adapter *padapter, struct sta_info *psta)
-+{
-+ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
-+ struct vht_priv *pvhtpriv_ap = &pmlmepriv->vhtpriv;
-+ struct vht_priv *pvhtpriv_sta = &psta->vhtpriv;
-+ u16 cur_beamform_cap = 0;
-+
-+ /* B11 SU Beamformer Capable, the target supports Beamformer and we are Beamformee */
-+ if (TEST_FLAG(pvhtpriv_ap->beamform_cap, BEAMFORMING_VHT_BEAMFORMER_ENABLE) &&
-+ GET_VHT_CAPABILITY_ELE_SU_BFEE(pvhtpriv_sta->vht_cap)) {
-+ SET_FLAG(cur_beamform_cap, BEAMFORMING_VHT_BEAMFORMEE_ENABLE);
-+ /*Shift to BEAMFORMING_VHT_BEAMFORMER_STS_CAP*/
-+ SET_FLAG(cur_beamform_cap, GET_VHT_CAPABILITY_ELE_SU_BFEE_STS_CAP(pvhtpriv_sta->vht_cap) << 8);
-+ }
-+
-+ /* B12 SU Beamformee Capable, the target supports Beamformee and we are Beamformer */
-+ if (TEST_FLAG(pvhtpriv_ap->beamform_cap, BEAMFORMING_VHT_BEAMFORMEE_ENABLE) &&
-+ GET_VHT_CAPABILITY_ELE_SU_BFER(pvhtpriv_sta->vht_cap)) {
-+ SET_FLAG(cur_beamform_cap, BEAMFORMING_VHT_BEAMFORMER_ENABLE);
-+ /*Shit to BEAMFORMING_VHT_BEAMFORMEE_SOUND_DIM*/
-+ SET_FLAG(cur_beamform_cap, GET_VHT_CAPABILITY_ELE_SU_BFER_SOUND_DIM_NUM(pvhtpriv_sta->vht_cap) << 12);
-+ }
-+
-+ if (cur_beamform_cap)
-+ RTW_INFO("Current STA(%d) VHT Beamforming Setting = %02X\n", psta->cmn.aid, cur_beamform_cap);
-+
-+ pvhtpriv_sta->beamform_cap = cur_beamform_cap;
-+ psta->cmn.bf_info.vht_beamform_cap = cur_beamform_cap;
-+}
-+#endif
-+
-+void update_sta_vht_info_apmode(_adapter *padapter, PVOID sta)
-+{
-+ struct sta_info *psta = (struct sta_info *)sta;
-+ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
-+ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
-+ struct vht_priv *pvhtpriv_ap = &pmlmepriv->vhtpriv;
-+ struct vht_priv *pvhtpriv_sta = &psta->vhtpriv;
-+ u8 cur_ldpc_cap = 0, cur_stbc_cap = 0;
-+ s8 bw_mode = -1;
-+ u8 *pcap_mcs;
-+
-+ if (pvhtpriv_sta->vht_option == _FALSE)
-+ return;
-+
-+ if (pvhtpriv_sta->op_present) {
-+ switch (GET_VHT_OPERATION_ELE_CHL_WIDTH(pvhtpriv_sta->vht_op)) {
-+ case 1: /* 80MHz */
-+ case 2: /* 160MHz */
-+ case 3: /* 80+80 */
-+ bw_mode = CHANNEL_WIDTH_80; /* only support up to 80MHz for now */
-+ break;
-+ }
-+ }
-+
-+ if (pvhtpriv_sta->notify_present)
-+ bw_mode = GET_VHT_OPERATING_MODE_FIELD_CHNL_WIDTH(&pvhtpriv_sta->vht_op_mode_notify);
-+ else if (MLME_IS_AP(padapter)) {
-+ /* for VHT client without Operating Mode Notify IE; minimal 80MHz */
-+ if (bw_mode < CHANNEL_WIDTH_80)
-+ bw_mode = CHANNEL_WIDTH_80;
-+ }
-+
-+ if (bw_mode != -1)
-+ psta->cmn.bw_mode = bw_mode; /* update bw_mode only if get value from VHT IEs */
-+
-+ psta->cmn.ra_info.is_vht_enable = _TRUE;
-+
-+ /* B4 Rx LDPC */
-+ if (TEST_FLAG(pvhtpriv_ap->ldpc_cap, LDPC_VHT_ENABLE_TX) &&
-+ GET_VHT_CAPABILITY_ELE_RX_LDPC(pvhtpriv_sta->vht_cap)) {
-+ SET_FLAG(cur_ldpc_cap, (LDPC_VHT_ENABLE_TX | LDPC_VHT_CAP_TX));
-+ RTW_INFO("Current STA(%d) VHT LDPC = %02X\n", psta->cmn.aid, cur_ldpc_cap);
-+ }
-+ pvhtpriv_sta->ldpc_cap = cur_ldpc_cap;
-+
-+ if (psta->cmn.bw_mode > pmlmeext->cur_bwmode)
-+ psta->cmn.bw_mode = pmlmeext->cur_bwmode;
-+
-+ if (psta->cmn.bw_mode == CHANNEL_WIDTH_80) {
-+ /* B5 Short GI for 80 MHz */
-+ pvhtpriv_sta->sgi_80m = (GET_VHT_CAPABILITY_ELE_SHORT_GI80M(pvhtpriv_sta->vht_cap) & pvhtpriv_ap->sgi_80m) ? _TRUE : _FALSE;
-+ /* RTW_INFO("Current STA ShortGI80MHz = %d\n", pvhtpriv_sta->sgi_80m); */
-+ } else if (psta->cmn.bw_mode >= CHANNEL_WIDTH_160) {
-+ /* B5 Short GI for 80 MHz */
-+ pvhtpriv_sta->sgi_80m = (GET_VHT_CAPABILITY_ELE_SHORT_GI160M(pvhtpriv_sta->vht_cap) & pvhtpriv_ap->sgi_80m) ? _TRUE : _FALSE;
-+ /* RTW_INFO("Current STA ShortGI160MHz = %d\n", pvhtpriv_sta->sgi_80m); */
-+ }
-+
-+ /* B8 B9 B10 Rx STBC */
-+ if (TEST_FLAG(pvhtpriv_ap->stbc_cap, STBC_VHT_ENABLE_TX) &&
-+ GET_VHT_CAPABILITY_ELE_RX_STBC(pvhtpriv_sta->vht_cap)) {
-+ SET_FLAG(cur_stbc_cap, (STBC_VHT_ENABLE_TX | STBC_VHT_CAP_TX));
-+ RTW_INFO("Current STA(%d) VHT STBC = %02X\n", psta->cmn.aid, cur_stbc_cap);
-+ }
-+ pvhtpriv_sta->stbc_cap = cur_stbc_cap;
-+
-+#ifdef CONFIG_BEAMFORMING
-+ update_sta_vht_info_apmode_bf_cap(padapter, psta);
-+#endif
-+
-+ /* B23 B24 B25 Maximum A-MPDU Length Exponent */
-+ pvhtpriv_sta->ampdu_len = GET_VHT_CAPABILITY_ELE_MAX_RXAMPDU_FACTOR(pvhtpriv_sta->vht_cap);
-+
-+ pcap_mcs = GET_VHT_CAPABILITY_ELE_RX_MCS(pvhtpriv_sta->vht_cap);
-+ _rtw_memcpy(pvhtpriv_sta->vht_mcs_map, pcap_mcs, 2);
-+ pvhtpriv_sta->vht_highest_rate = rtw_get_vht_highest_rate(pvhtpriv_sta->vht_mcs_map);
-+}
-+
-+void update_hw_vht_param(_adapter *padapter)
-+{
-+ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
-+ struct vht_priv *pvhtpriv = &pmlmepriv->vhtpriv;
-+ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
-+ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
-+ u8 ht_AMPDU_len;
-+
-+ ht_AMPDU_len = pmlmeinfo->HT_caps.u.HT_cap_element.AMPDU_para & 0x03;
-+
-+ if (pvhtpriv->ampdu_len > ht_AMPDU_len)
-+ rtw_hal_set_hwreg(padapter, HW_VAR_AMPDU_FACTOR, (u8 *)(&pvhtpriv->ampdu_len));
-+}
-+
-+#ifdef ROKU_PRIVATE
-+u8 VHT_get_ss_from_map(u8 *vht_mcs_map)
-+{
-+ u8 i, j;
-+ u8 ss = 0;
-+
-+ for (i = 0; i < 2; i++) {
-+ if (vht_mcs_map[i] != 0xff) {
-+ for (j = 0; j < 8; j += 2) {
-+ if (((vht_mcs_map[i] >> j) & 0x03) == 0x03)
-+ break;
-+ ss++;
-+ }
-+ }
-+
-+ }
-+
-+return ss;
-+}
-+
-+void VHT_caps_handler_infra_ap(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE)
-+{
-+ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
-+ struct vht_priv_infra_ap *pvhtpriv = &pmlmepriv->vhtpriv_infra_ap;
-+ u8 cur_stbc_cap_infra_ap = 0;
-+ u16 cur_beamform_cap_infra_ap = 0;
-+ u8 *pcap_mcs;
-+ u8 *pcap_mcs_tx;
-+ u8 Rx_ss = 0, Tx_ss = 0;
-+
-+ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
-+ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
-+
-+ if (pIE == NULL)
-+ return;
-+
-+ pmlmeinfo->ht_vht_received |= BIT(1);
-+
-+ pvhtpriv->ldpc_cap_infra_ap = GET_VHT_CAPABILITY_ELE_RX_LDPC(pIE->data);
-+
-+ if (GET_VHT_CAPABILITY_ELE_RX_STBC(pIE->data))
-+ SET_FLAG(cur_stbc_cap_infra_ap, STBC_VHT_ENABLE_RX);
-+ if (GET_VHT_CAPABILITY_ELE_TX_STBC(pIE->data))
-+ SET_FLAG(cur_stbc_cap_infra_ap, STBC_VHT_ENABLE_TX);
-+ pvhtpriv->stbc_cap_infra_ap = cur_stbc_cap_infra_ap;
-+
-+ /*store ap info for channel bandwidth*/
-+ pvhtpriv->channel_width_infra_ap = GET_VHT_CAPABILITY_ELE_CHL_WIDTH(pIE->data);
-+
-+ /*check B11: SU Beamformer Capable and B12: SU Beamformee B19: MU Beamformer B20:MU Beamformee*/
-+ if (GET_VHT_CAPABILITY_ELE_SU_BFER(pIE->data))
-+ SET_FLAG(cur_beamform_cap_infra_ap, BEAMFORMING_VHT_BEAMFORMER_ENABLE);
-+ if (GET_VHT_CAPABILITY_ELE_SU_BFEE(pIE->data))
-+ SET_FLAG(cur_beamform_cap_infra_ap, BEAMFORMING_VHT_BEAMFORMEE_ENABLE);
-+ if (GET_VHT_CAPABILITY_ELE_MU_BFER(pIE->data))
-+ SET_FLAG(cur_beamform_cap_infra_ap, BEAMFORMING_VHT_MU_MIMO_AP_ENABLE);
-+ if (GET_VHT_CAPABILITY_ELE_MU_BFEE(pIE->data))
-+ SET_FLAG(cur_beamform_cap_infra_ap, BEAMFORMING_VHT_MU_MIMO_STA_ENABLE);
-+ pvhtpriv->beamform_cap_infra_ap = cur_beamform_cap_infra_ap;
-+
-+ /*store information about vht_mcs_set*/
-+ pcap_mcs = GET_VHT_CAPABILITY_ELE_RX_MCS(pIE->data);
-+ pcap_mcs_tx = GET_VHT_CAPABILITY_ELE_TX_MCS(pIE->data);
-+ _rtw_memcpy(pvhtpriv->vht_mcs_map_infra_ap, pcap_mcs, 2);
-+ _rtw_memcpy(pvhtpriv->vht_mcs_map_tx_infra_ap, pcap_mcs_tx, 2);
-+
-+ Rx_ss = VHT_get_ss_from_map(pvhtpriv->vht_mcs_map_infra_ap);
-+ Tx_ss = VHT_get_ss_from_map(pvhtpriv->vht_mcs_map_tx_infra_ap);
-+ if (Rx_ss >= Tx_ss) {
-+ pvhtpriv->number_of_streams_infra_ap = Rx_ss;
-+ } else{
-+ pvhtpriv->number_of_streams_infra_ap = Tx_ss;
-+ }
-+
-+}
-+#endif /* ROKU_PRIVATE */
-+
-+void VHT_caps_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE)
-+{
-+ struct hal_spec_t *hal_spec = GET_HAL_SPEC(padapter);
-+ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
-+ struct vht_priv *pvhtpriv = &pmlmepriv->vhtpriv;
-+ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
-+ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
-+ u8 cur_ldpc_cap = 0, cur_stbc_cap = 0, rf_type = RF_1T1R, tx_nss = 0;
-+ u16 cur_beamform_cap = 0;
-+ u8 *pcap_mcs;
-+
-+ if (pIE == NULL)
-+ return;
-+
-+ if (pvhtpriv->vht_option == _FALSE)
-+ return;
-+
-+ pmlmeinfo->VHT_enable = 1;
-+
-+ /* B4 Rx LDPC */
-+ if (TEST_FLAG(pvhtpriv->ldpc_cap, LDPC_VHT_ENABLE_TX) &&
-+ GET_VHT_CAPABILITY_ELE_RX_LDPC(pIE->data)) {
-+ SET_FLAG(cur_ldpc_cap, (LDPC_VHT_ENABLE_TX | LDPC_VHT_CAP_TX));
-+ RTW_INFO("Current VHT LDPC Setting = %02X\n", cur_ldpc_cap);
-+ }
-+ pvhtpriv->ldpc_cap = cur_ldpc_cap;
-+
-+ /* B5 Short GI for 80 MHz */
-+ pvhtpriv->sgi_80m = (GET_VHT_CAPABILITY_ELE_SHORT_GI80M(pIE->data) & pvhtpriv->sgi_80m) ? _TRUE : _FALSE;
-+ /* RTW_INFO("Current ShortGI80MHz = %d\n", pvhtpriv->sgi_80m); */
-+
-+ /* B8 B9 B10 Rx STBC */
-+ if (TEST_FLAG(pvhtpriv->stbc_cap, STBC_VHT_ENABLE_TX) &&
-+ GET_VHT_CAPABILITY_ELE_RX_STBC(pIE->data)) {
-+ SET_FLAG(cur_stbc_cap, (STBC_VHT_ENABLE_TX | STBC_VHT_CAP_TX));
-+ RTW_INFO("Current VHT STBC Setting = %02X\n", cur_stbc_cap);
-+ }
-+ pvhtpriv->stbc_cap = cur_stbc_cap;
-+#ifdef CONFIG_BEAMFORMING
-+#ifdef RTW_BEAMFORMING_VERSION_2
-+ /*
-+ * B11 SU Beamformer Capable,
-+ * the target supports Beamformer and we are Beamformee
-+ */
-+ if (TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_BEAMFORMEE_ENABLE)
-+ && GET_VHT_CAPABILITY_ELE_SU_BFER(pIE->data)) {
-+ SET_FLAG(cur_beamform_cap, BEAMFORMING_VHT_BEAMFORMEE_ENABLE);
-+
-+ /* Shift to BEAMFORMING_VHT_BEAMFORMEE_STS_CAP */
-+ SET_FLAG(cur_beamform_cap, GET_VHT_CAPABILITY_ELE_SU_BFEE_STS_CAP(pIE->data) << 8);
-+
-+ /*
-+ * B19 MU Beamformer Capable,
-+ * the target supports Beamformer and we are Beamformee
-+ */
-+ if (TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_MU_MIMO_STA_ENABLE)
-+ && GET_VHT_CAPABILITY_ELE_MU_BFER(pIE->data))
-+ SET_FLAG(cur_beamform_cap, BEAMFORMING_VHT_MU_MIMO_STA_ENABLE);
-+ }
-+
-+ /*
-+ * B12 SU Beamformee Capable,
-+ * the target supports Beamformee and we are Beamformer
-+ */
-+ if (TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_BEAMFORMER_ENABLE)
-+ && GET_VHT_CAPABILITY_ELE_SU_BFEE(pIE->data)) {
-+ SET_FLAG(cur_beamform_cap, BEAMFORMING_VHT_BEAMFORMER_ENABLE);
-+
-+ /* Shit to BEAMFORMING_VHT_BEAMFORMER_SOUND_DIM */
-+ SET_FLAG(cur_beamform_cap, GET_VHT_CAPABILITY_ELE_SU_BFER_SOUND_DIM_NUM(pIE->data) << 12);
-+
-+ /*
-+ * B20 MU Beamformee Capable,
-+ * the target supports Beamformee and we are Beamformer
-+ */
-+ if (TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_MU_MIMO_AP_ENABLE)
-+ && GET_VHT_CAPABILITY_ELE_MU_BFEE(pIE->data))
-+ SET_FLAG(cur_beamform_cap, BEAMFORMING_VHT_MU_MIMO_AP_ENABLE);
-+ }
-+
-+ pvhtpriv->beamform_cap = cur_beamform_cap;
-+ RTW_INFO("Current VHT Beamforming Setting=0x%04X\n", cur_beamform_cap);
-+#else /* !RTW_BEAMFORMING_VERSION_2 */
-+ /* B11 SU Beamformer Capable, the target supports Beamformer and we are Beamformee */
-+ if (TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_BEAMFORMER_ENABLE) &&
-+ GET_VHT_CAPABILITY_ELE_SU_BFEE(pIE->data)) {
-+ SET_FLAG(cur_beamform_cap, BEAMFORMING_VHT_BEAMFORMEE_ENABLE);
-+ /*Shift to BEAMFORMING_VHT_BEAMFORMER_STS_CAP*/
-+ SET_FLAG(cur_beamform_cap, GET_VHT_CAPABILITY_ELE_SU_BFEE_STS_CAP(pIE->data) << 8);
-+ }
-+
-+ /* B12 SU Beamformee Capable, the target supports Beamformee and we are Beamformer */
-+ if (TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_BEAMFORMEE_ENABLE) &&
-+ GET_VHT_CAPABILITY_ELE_SU_BFER(pIE->data)) {
-+ SET_FLAG(cur_beamform_cap, BEAMFORMING_VHT_BEAMFORMER_ENABLE);
-+ /*Shit to BEAMFORMING_VHT_BEAMFORMEE_SOUND_DIM*/
-+ SET_FLAG(cur_beamform_cap, GET_VHT_CAPABILITY_ELE_SU_BFER_SOUND_DIM_NUM(pIE->data) << 12);
-+
-+ }
-+ pvhtpriv->beamform_cap = cur_beamform_cap;
-+ if (cur_beamform_cap)
-+ RTW_INFO("Current VHT Beamforming Setting = %02X\n", cur_beamform_cap);
-+#endif /* !RTW_BEAMFORMING_VERSION_2 */
-+#endif /* CONFIG_BEAMFORMING */
-+ /* B23 B24 B25 Maximum A-MPDU Length Exponent */
-+ pvhtpriv->ampdu_len = GET_VHT_CAPABILITY_ELE_MAX_RXAMPDU_FACTOR(pIE->data);
-+
-+ pcap_mcs = GET_VHT_CAPABILITY_ELE_RX_MCS(pIE->data);
-+ rtw_hal_get_hwreg(padapter, HW_VAR_RF_TYPE, (u8 *)(&rf_type));
-+ tx_nss = rtw_min(rf_type_to_rf_tx_cnt(rf_type), hal_spec->tx_nss_num);
-+ rtw_vht_nss_to_mcsmap(tx_nss, pvhtpriv->vht_mcs_map, pcap_mcs);
-+ pvhtpriv->vht_highest_rate = rtw_get_vht_highest_rate(pvhtpriv->vht_mcs_map);
-+}
-+
-+void VHT_operation_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE)
-+{
-+ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
-+ struct vht_priv *pvhtpriv = &pmlmepriv->vhtpriv;
-+
-+ if (pIE == NULL)
-+ return;
-+
-+ if (pvhtpriv->vht_option == _FALSE)
-+ return;
-+}
-+
-+void rtw_process_vht_op_mode_notify(_adapter *padapter, u8 *pframe, PVOID sta)
-+{
-+ struct sta_info *psta = (struct sta_info *)sta;
-+ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
-+ struct vht_priv *pvhtpriv = &pmlmepriv->vhtpriv;
-+ struct registry_priv *regsty = adapter_to_regsty(padapter);
-+ u8 target_bw;
-+ u8 target_rxss, current_rxss;
-+ u8 update_ra = _FALSE;
-+ u8 tx_nss = 0, rf_type = RF_1T1R;
-+ struct hal_spec_t *hal_spec = GET_HAL_SPEC(padapter);
-+
-+ if (pvhtpriv->vht_option == _FALSE)
-+ return;
-+
-+ target_bw = GET_VHT_OPERATING_MODE_FIELD_CHNL_WIDTH(pframe);
-+
-+ rtw_hal_get_hwreg(padapter, HW_VAR_RF_TYPE, (u8 *)(&rf_type));
-+ tx_nss = rtw_min(rf_type_to_rf_tx_cnt(rf_type), hal_spec->tx_nss_num);
-+ target_rxss = rtw_min(tx_nss, (GET_VHT_OPERATING_MODE_FIELD_RX_NSS(pframe) + 1));
-+
-+ if (target_bw != psta->cmn.bw_mode) {
-+ if (hal_is_bw_support(padapter, target_bw)
-+ && REGSTY_IS_BW_5G_SUPPORT(regsty, target_bw)
-+ ) {
-+ update_ra = _TRUE;
-+ psta->cmn.bw_mode = target_bw;
-+ }
-+ }
-+
-+ current_rxss = rtw_vht_mcsmap_to_nss(psta->vhtpriv.vht_mcs_map);
-+ if (target_rxss != current_rxss) {
-+ u8 vht_mcs_map[2] = {};
-+
-+ update_ra = _TRUE;
-+
-+ rtw_vht_nss_to_mcsmap(target_rxss, vht_mcs_map, psta->vhtpriv.vht_mcs_map);
-+ _rtw_memcpy(psta->vhtpriv.vht_mcs_map, vht_mcs_map, 2);
-+
-+ rtw_hal_update_sta_ra_info(padapter, psta);
-+ }
-+
-+ if (update_ra)
-+ rtw_dm_ra_mask_wk_cmd(padapter, (u8 *)psta);
-+}
-+
-+u32 rtw_build_vht_operation_ie(_adapter *padapter, u8 *pbuf, u8 channel)
-+{
-+ struct registry_priv *pregistrypriv = &padapter->registrypriv;
-+ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
-+ struct vht_priv *pvhtpriv = &pmlmepriv->vhtpriv;
-+ /* struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; */
-+ u8 ChnlWidth, center_freq, bw_mode;
-+ u32 len = 0;
-+ u8 operation[5];
-+
-+ _rtw_memset(operation, 0, 5);
-+
-+ bw_mode = REGSTY_BW_5G(pregistrypriv); /* TODO: control op bw with other info */
-+
-+ if (hal_chk_bw_cap(padapter, BW_CAP_80M | BW_CAP_160M)
-+ && REGSTY_BW_5G(pregistrypriv) >= CHANNEL_WIDTH_80
-+ ) {
-+ center_freq = rtw_get_center_ch(channel, bw_mode, HAL_PRIME_CHNL_OFFSET_LOWER);
-+ ChnlWidth = 1;
-+ } else {
-+ center_freq = 0;
-+ ChnlWidth = 0;
-+ }
-+
-+
-+ SET_VHT_OPERATION_ELE_CHL_WIDTH(operation, ChnlWidth);
-+ /* center frequency */
-+ SET_VHT_OPERATION_ELE_CHL_CENTER_FREQ1(operation, center_freq);/* Todo: need to set correct center channel */
-+ SET_VHT_OPERATION_ELE_CHL_CENTER_FREQ2(operation, 0);
-+
-+ _rtw_memcpy(operation + 3, pvhtpriv->vht_mcs_map, 2);
-+
-+ rtw_set_ie(pbuf, EID_VHTOperation, 5, operation, &len);
-+
-+ return len;
-+}
-+
-+u32 rtw_build_vht_op_mode_notify_ie(_adapter *padapter, u8 *pbuf, u8 bw)
-+{
-+ /* struct registry_priv *pregistrypriv = &padapter->registrypriv; */
-+ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
-+ struct vht_priv *pvhtpriv = &pmlmepriv->vhtpriv;
-+ u32 len = 0;
-+ u8 opmode = 0;
-+ u8 chnl_width, rx_nss;
-+
-+ chnl_width = bw;
-+ rx_nss = rtw_vht_mcsmap_to_nss(pvhtpriv->vht_mcs_map);
-+
-+ SET_VHT_OPERATING_MODE_FIELD_CHNL_WIDTH(&opmode, chnl_width);
-+ SET_VHT_OPERATING_MODE_FIELD_RX_NSS(&opmode, (rx_nss - 1));
-+ SET_VHT_OPERATING_MODE_FIELD_RX_NSS_TYPE(&opmode, 0); /* Todo */
-+
-+ pvhtpriv->vht_op_mode_notify = opmode;
-+
-+ pbuf = rtw_set_ie(pbuf, EID_OpModeNotification, 1, &opmode, &len);
-+
-+ return len;
-+}
-+
-+u32 rtw_build_vht_cap_ie(_adapter *padapter, u8 *pbuf)
-+{
-+ u8 bw, rf_num, rx_stbc_nss = 0;
-+ u16 HighestRate;
-+ u8 *pcap, *pcap_mcs;
-+ u32 len = 0;
-+ u32 rx_packet_offset, max_recvbuf_sz;
-+ struct registry_priv *pregistrypriv = &padapter->registrypriv;
-+ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
-+ struct vht_priv *pvhtpriv = &pmlmepriv->vhtpriv;
-+ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
-+ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
-+
-+ pcap = pvhtpriv->vht_cap;
-+ _rtw_memset(pcap, 0, 32);
-+
-+ /* B0 B1 Maximum MPDU Length */
-+ rtw_hal_get_def_var(padapter, HAL_DEF_RX_PACKET_OFFSET, &rx_packet_offset);
-+ rtw_hal_get_def_var(padapter, HAL_DEF_MAX_RECVBUF_SZ, &max_recvbuf_sz);
-+
-+ RTW_DBG("%s, line%d, Available RX buf size = %d bytes\n", __FUNCTION__, __LINE__, max_recvbuf_sz - rx_packet_offset);
-+
-+ if ((max_recvbuf_sz - rx_packet_offset) >= 11454) {
-+ SET_VHT_CAPABILITY_ELE_MAX_MPDU_LENGTH(pcap, 2);
-+ RTW_INFO("%s, line%d, Set MAX MPDU len = 11454 bytes\n", __FUNCTION__, __LINE__);
-+ } else if ((max_recvbuf_sz - rx_packet_offset) >= 7991) {
-+ SET_VHT_CAPABILITY_ELE_MAX_MPDU_LENGTH(pcap, 1);
-+ RTW_INFO("%s, line%d, Set MAX MPDU len = 7991 bytes\n", __FUNCTION__, __LINE__);
-+ } else if ((max_recvbuf_sz - rx_packet_offset) >= 3895) {
-+ SET_VHT_CAPABILITY_ELE_MAX_MPDU_LENGTH(pcap, 0);
-+ RTW_INFO("%s, line%d, Set MAX MPDU len = 3895 bytes\n", __FUNCTION__, __LINE__);
-+ } else
-+ RTW_ERR("%s, line%d, Error!! Available RX buf size < 3895 bytes\n", __FUNCTION__, __LINE__);
-+
-+ /* B2 B3 Supported Channel Width Set */
-+ if (hal_chk_bw_cap(padapter, BW_CAP_160M) && REGSTY_IS_BW_5G_SUPPORT(pregistrypriv, CHANNEL_WIDTH_160)) {
-+ if (hal_chk_bw_cap(padapter, BW_CAP_80_80M) && REGSTY_IS_BW_5G_SUPPORT(pregistrypriv, CHANNEL_WIDTH_80_80))
-+ SET_VHT_CAPABILITY_ELE_CHL_WIDTH(pcap, 2);
-+ else
-+ SET_VHT_CAPABILITY_ELE_CHL_WIDTH(pcap, 1);
-+ } else
-+ SET_VHT_CAPABILITY_ELE_CHL_WIDTH(pcap, 0);
-+
-+ /* B4 Rx LDPC */
-+ if (TEST_FLAG(pvhtpriv->ldpc_cap, LDPC_VHT_ENABLE_RX)) {
-+ SET_VHT_CAPABILITY_ELE_RX_LDPC(pcap, 1);
-+ RTW_INFO("[VHT] Declare supporting RX LDPC\n");
-+ }
-+
-+ /* B5 ShortGI for 80MHz */
-+ SET_VHT_CAPABILITY_ELE_SHORT_GI80M(pcap, pvhtpriv->sgi_80m ? 1 : 0); /* We can receive Short GI of 80M */
-+ if (pvhtpriv->sgi_80m)
-+ RTW_INFO("[VHT] Declare supporting SGI 80MHz\n");
-+
-+ /* B6 ShortGI for 160MHz */
-+ /* SET_VHT_CAPABILITY_ELE_SHORT_GI160M(pcap, pvhtpriv->sgi_80m? 1 : 0); */
-+
-+ /* B7 Tx STBC */
-+ if (TEST_FLAG(pvhtpriv->stbc_cap, STBC_VHT_ENABLE_TX)) {
-+ SET_VHT_CAPABILITY_ELE_TX_STBC(pcap, 1);
-+ RTW_INFO("[VHT] Declare supporting TX STBC\n");
-+ }
-+
-+ /* B8 B9 B10 Rx STBC */
-+ if (TEST_FLAG(pvhtpriv->stbc_cap, STBC_VHT_ENABLE_RX)) {
-+ rtw_hal_get_def_var(padapter, HAL_DEF_RX_STBC, (u8 *)(&rx_stbc_nss));
-+
-+ SET_VHT_CAPABILITY_ELE_RX_STBC(pcap, rx_stbc_nss);
-+ RTW_INFO("[VHT] Declare supporting RX STBC = %d\n", rx_stbc_nss);
-+ }
-+ #ifdef CONFIG_BEAMFORMING
-+ /* B11 SU Beamformer Capable */
-+ if (TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_BEAMFORMER_ENABLE)) {
-+ SET_VHT_CAPABILITY_ELE_SU_BFER(pcap, 1);
-+ RTW_INFO("[VHT] Declare supporting SU Bfer\n");
-+ /* B16 17 18 Number of Sounding Dimensions */
-+ rtw_hal_get_def_var(padapter, HAL_DEF_BEAMFORMER_CAP, (u8 *)&rf_num);
-+ SET_VHT_CAPABILITY_ELE_SOUNDING_DIMENSIONS(pcap, rf_num);
-+ /* B19 MU Beamformer Capable */
-+ if (TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_MU_MIMO_AP_ENABLE)) {
-+ SET_VHT_CAPABILITY_ELE_MU_BFER(pcap, 1);
-+ RTW_INFO("[VHT] Declare supporting MU Bfer\n");
-+ }
-+ }
-+
-+ /* B12 SU Beamformee Capable */
-+ if (TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_BEAMFORMEE_ENABLE)) {
-+ SET_VHT_CAPABILITY_ELE_SU_BFEE(pcap, 1);
-+ RTW_INFO("[VHT] Declare supporting SU Bfee\n");
-+
-+ rtw_hal_get_def_var(padapter, HAL_DEF_BEAMFORMEE_CAP, (u8 *)&rf_num);
-+
-+ /* IOT action suggested by Yu Chen 2017/3/3 */
-+#ifdef CONFIG_80211AC_VHT
-+ if ((pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_BROADCOM) &&
-+ !pvhtpriv->ap_is_mu_bfer)
-+ rf_num = (rf_num >= 2 ? 2 : rf_num);
-+#endif
-+ /* B13 14 15 Compressed Steering Number of Beamformer Antennas Supported */
-+ SET_VHT_CAPABILITY_ELE_BFER_ANT_SUPP(pcap, rf_num);
-+ /* B20 SU Beamformee Capable */
-+ if (TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_MU_MIMO_STA_ENABLE)) {
-+ SET_VHT_CAPABILITY_ELE_MU_BFEE(pcap, 1);
-+ RTW_INFO("[VHT] Declare supporting MU Bfee\n");
-+ }
-+ }
-+ #endif/*CONFIG_BEAMFORMING*/
-+
-+ /* B21 VHT TXOP PS */
-+ SET_VHT_CAPABILITY_ELE_TXOP_PS(pcap, 0);
-+ /* B22 +HTC-VHT Capable */
-+ SET_VHT_CAPABILITY_ELE_HTC_VHT(pcap, 1);
-+ /* B23 24 25 Maximum A-MPDU Length Exponent */
-+ if (pregistrypriv->ampdu_factor != 0xFE)
-+ SET_VHT_CAPABILITY_ELE_MAX_RXAMPDU_FACTOR(pcap, pregistrypriv->ampdu_factor);
-+ else
-+ SET_VHT_CAPABILITY_ELE_MAX_RXAMPDU_FACTOR(pcap, 7);
-+ /* B26 27 VHT Link Adaptation Capable */
-+ SET_VHT_CAPABILITY_ELE_LINK_ADAPTION(pcap, 0);
-+
-+ pcap_mcs = GET_VHT_CAPABILITY_ELE_RX_MCS(pcap);
-+ _rtw_memcpy(pcap_mcs, pvhtpriv->vht_mcs_map, 2);
-+
-+ pcap_mcs = GET_VHT_CAPABILITY_ELE_TX_MCS(pcap);
-+ _rtw_memcpy(pcap_mcs, pvhtpriv->vht_mcs_map, 2);
-+
-+ /* find the largest bw supported by both registry and hal */
-+ bw = hal_largest_bw(padapter, REGSTY_BW_5G(pregistrypriv));
-+
-+ HighestRate = VHT_MCS_DATA_RATE[bw][pvhtpriv->sgi_80m][((pvhtpriv->vht_highest_rate - MGN_VHT1SS_MCS0) & 0x3f)];
-+ HighestRate = (HighestRate + 1) >> 1;
-+
-+ SET_VHT_CAPABILITY_ELE_MCS_RX_HIGHEST_RATE(pcap, HighestRate); /* indicate we support highest rx rate is 600Mbps. */
-+ SET_VHT_CAPABILITY_ELE_MCS_TX_HIGHEST_RATE(pcap, HighestRate); /* indicate we support highest tx rate is 600Mbps. */
-+
-+ pbuf = rtw_set_ie(pbuf, EID_VHTCapability, 12, pcap, &len);
-+
-+ return len;
-+}
-+
-+u32 rtw_restructure_vht_ie(_adapter *padapter, u8 *in_ie, u8 *out_ie, uint in_len, uint *pout_len)
-+{
-+ struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter);
-+ RT_CHANNEL_INFO *chset = rfctl->channel_set;
-+ u32 ielen;
-+ u8 max_bw;
-+ u8 oper_ch, oper_bw = CHANNEL_WIDTH_20, oper_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
-+ u8 *out_vht_op_ie, *ht_op_ie, *vht_cap_ie, *vht_op_ie;
-+ struct registry_priv *pregistrypriv = &padapter->registrypriv;
-+ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
-+ struct vht_priv *pvhtpriv = &pmlmepriv->vhtpriv;
-+
-+ rtw_vht_use_default_setting(padapter);
-+
-+ ht_op_ie = rtw_get_ie(in_ie + 12, WLAN_EID_HT_OPERATION, &ielen, in_len - 12);
-+ if (!ht_op_ie || ielen != HT_OP_IE_LEN)
-+ goto exit;
-+ vht_cap_ie = rtw_get_ie(in_ie + 12, EID_VHTCapability, &ielen, in_len - 12);
-+ if (!vht_cap_ie || ielen != VHT_CAP_IE_LEN)
-+ goto exit;
-+ vht_op_ie = rtw_get_ie(in_ie + 12, EID_VHTOperation, &ielen, in_len - 12);
-+ if (!vht_op_ie || ielen != VHT_OP_IE_LEN)
-+ goto exit;
-+
-+ /* VHT Capabilities element */
-+ *pout_len += rtw_build_vht_cap_ie(padapter, out_ie + *pout_len);
-+
-+
-+ /* VHT Operation element */
-+ out_vht_op_ie = out_ie + *pout_len;
-+ rtw_set_ie(out_vht_op_ie, EID_VHTOperation, VHT_OP_IE_LEN, vht_op_ie + 2 , pout_len);
-+
-+ /* get primary channel from HT_OP_IE */
-+ oper_ch = GET_HT_OP_ELE_PRI_CHL(ht_op_ie + 2);
-+
-+ /* find the largest bw supported by both registry and hal */
-+ max_bw = hal_largest_bw(padapter, REGSTY_BW_5G(pregistrypriv));
-+
-+ if (max_bw >= CHANNEL_WIDTH_40) {
-+ /* get bw offset form HT_OP_IE */
-+ if (GET_HT_OP_ELE_STA_CHL_WIDTH(ht_op_ie + 2)) {
-+ switch (GET_HT_OP_ELE_2ND_CHL_OFFSET(ht_op_ie + 2)) {
-+ case SCA:
-+ oper_bw = CHANNEL_WIDTH_40;
-+ oper_offset = HAL_PRIME_CHNL_OFFSET_LOWER;
-+ break;
-+ case SCB:
-+ oper_bw = CHANNEL_WIDTH_40;
-+ oper_offset = HAL_PRIME_CHNL_OFFSET_UPPER;
-+ break;
-+ }
-+ }
-+
-+ if (oper_bw == CHANNEL_WIDTH_40) {
-+ switch (GET_VHT_OPERATION_ELE_CHL_WIDTH(vht_op_ie + 2)) {
-+ case 1: /* 80MHz */
-+ case 2: /* 160MHz */
-+ case 3: /* 80+80 */
-+ oper_bw = CHANNEL_WIDTH_80; /* only support up to 80MHz for now */
-+ break;
-+ }
-+
-+ oper_bw = rtw_min(oper_bw, max_bw);
-+
-+ /* try downgrage bw to fit in channel plan setting */
-+ while (!rtw_chset_is_chbw_valid(chset, oper_ch, oper_bw, oper_offset)
-+ || (IS_DFS_SLAVE_WITH_RD(rfctl)
-+ && !rtw_odm_dfs_domain_unknown(rfctl_to_dvobj(rfctl))
-+ && rtw_chset_is_chbw_non_ocp(chset, oper_ch, oper_bw, oper_offset))
-+ ) {
-+ oper_bw--;
-+ if (oper_bw == CHANNEL_WIDTH_20) {
-+ oper_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
-+ break;
-+ }
-+ }
-+ }
-+ }
-+
-+ rtw_warn_on(!rtw_chset_is_chbw_valid(chset, oper_ch, oper_bw, oper_offset));
-+ if (IS_DFS_SLAVE_WITH_RD(rfctl) && !rtw_odm_dfs_domain_unknown(rfctl_to_dvobj(rfctl)))
-+ rtw_warn_on(rtw_chset_is_chbw_non_ocp(chset, oper_ch, oper_bw, oper_offset));
-+
-+ /* update VHT_OP_IE */
-+ if (oper_bw < CHANNEL_WIDTH_80) {
-+ SET_VHT_OPERATION_ELE_CHL_WIDTH(out_vht_op_ie + 2, 0);
-+ SET_VHT_OPERATION_ELE_CHL_CENTER_FREQ1(out_vht_op_ie + 2, 0);
-+ SET_VHT_OPERATION_ELE_CHL_CENTER_FREQ2(out_vht_op_ie + 2, 0);
-+ } else if (oper_bw == CHANNEL_WIDTH_80) {
-+ u8 cch = rtw_get_center_ch(oper_ch, oper_bw, oper_offset);
-+
-+ SET_VHT_OPERATION_ELE_CHL_WIDTH(out_vht_op_ie + 2, 1);
-+ SET_VHT_OPERATION_ELE_CHL_CENTER_FREQ1(out_vht_op_ie + 2, cch);
-+ SET_VHT_OPERATION_ELE_CHL_CENTER_FREQ2(out_vht_op_ie + 2, 0);
-+ } else {
-+ RTW_ERR(FUNC_ADPT_FMT" unsupported BW:%u\n", FUNC_ADPT_ARG(padapter), oper_bw);
-+ rtw_warn_on(1);
-+ }
-+
-+ /* Operating Mode Notification element */
-+ *pout_len += rtw_build_vht_op_mode_notify_ie(padapter, out_ie + *pout_len, oper_bw);
-+
-+ pvhtpriv->vht_option = _TRUE;
-+
-+exit:
-+ return pvhtpriv->vht_option;
-+
-+}
-+
-+void VHTOnAssocRsp(_adapter *padapter)
-+{
-+ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
-+ struct vht_priv *pvhtpriv = &pmlmepriv->vhtpriv;
-+ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
-+ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
-+ u8 ht_AMPDU_len;
-+
-+ RTW_INFO("%s\n", __FUNCTION__);
-+
-+ if (!pmlmeinfo->HT_enable)
-+ return;
-+
-+ if (!pmlmeinfo->VHT_enable)
-+ return;
-+
-+ ht_AMPDU_len = pmlmeinfo->HT_caps.u.HT_cap_element.AMPDU_para & 0x03;
-+
-+ if (pvhtpriv->ampdu_len > ht_AMPDU_len)
-+ rtw_hal_set_hwreg(padapter, HW_VAR_AMPDU_FACTOR, (u8 *)(&pvhtpriv->ampdu_len));
-+
-+ rtw_hal_set_hwreg(padapter, HW_VAR_AMPDU_MAX_TIME, (u8 *)(&pvhtpriv->vht_highest_rate));
-+}
-+
-+void rtw_vht_ies_attach(_adapter *padapter, WLAN_BSSID_EX *pnetwork)
-+{
-+ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
-+ u8 cap_len, operation_len;
-+ uint len = 0;
-+ sint ie_len = 0;
-+ u8 *p = NULL;
-+
-+ p = rtw_get_ie(pnetwork->IEs + _BEACON_IE_OFFSET_, EID_VHTCapability, &ie_len,
-+ (pnetwork->IELength - _BEACON_IE_OFFSET_));
-+ if (p && ie_len > 0)
-+ return;
-+
-+ rtw_vht_use_default_setting(padapter);
-+
-+ /* VHT Operation mode notifiy bit in Extended IE (127) */
-+ SET_EXT_CAPABILITY_ELE_OP_MODE_NOTIF(pmlmepriv->ext_capab_ie_data, 1);
-+ pmlmepriv->ext_capab_ie_len = 10;
-+ rtw_set_ie(pnetwork->IEs + pnetwork->IELength, EID_EXTCapability, 8, pmlmepriv->ext_capab_ie_data, &len);
-+ pnetwork->IELength += pmlmepriv->ext_capab_ie_len;
-+
-+ /* VHT Capabilities element */
-+ cap_len = rtw_build_vht_cap_ie(padapter, pnetwork->IEs + pnetwork->IELength);
-+ pnetwork->IELength += cap_len;
-+
-+ /* VHT Operation element */
-+ operation_len = rtw_build_vht_operation_ie(padapter, pnetwork->IEs + pnetwork->IELength,
-+ pnetwork->Configuration.DSConfig);
-+ pnetwork->IELength += operation_len;
-+
-+ rtw_check_for_vht20(padapter, pnetwork->IEs + _BEACON_IE_OFFSET_, pnetwork->IELength - _BEACON_IE_OFFSET_);
-+
-+ pmlmepriv->vhtpriv.vht_option = _TRUE;
-+}
-+
-+void rtw_vht_ies_detach(_adapter *padapter, WLAN_BSSID_EX *pnetwork)
-+{
-+ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
-+
-+ rtw_remove_bcn_ie(padapter, pnetwork, EID_EXTCapability);
-+ rtw_remove_bcn_ie(padapter, pnetwork, EID_VHTCapability);
-+ rtw_remove_bcn_ie(padapter, pnetwork, EID_VHTOperation);
-+
-+ pmlmepriv->vhtpriv.vht_option = _FALSE;
-+}
-+
-+void rtw_check_for_vht20(_adapter *adapter, u8 *ies, int ies_len)
-+{
-+ u8 ht_ch, ht_bw, ht_offset;
-+ u8 vht_ch, vht_bw, vht_offset;
-+
-+ rtw_ies_get_chbw(ies, ies_len, &ht_ch, &ht_bw, &ht_offset, 1, 0);
-+ rtw_ies_get_chbw(ies, ies_len, &vht_ch, &vht_bw, &vht_offset, 1, 1);
-+
-+ if (ht_bw == CHANNEL_WIDTH_20 && vht_bw >= CHANNEL_WIDTH_80) {
-+ u8 *vht_op_ie;
-+ int vht_op_ielen;
-+
-+ RTW_INFO(FUNC_ADPT_FMT" vht80 is not allowed without ht40\n", FUNC_ADPT_ARG(adapter));
-+ vht_op_ie = rtw_get_ie(ies, EID_VHTOperation, &vht_op_ielen, ies_len);
-+ if (vht_op_ie && vht_op_ielen) {
-+ RTW_INFO(FUNC_ADPT_FMT" switch to vht20\n", FUNC_ADPT_ARG(adapter));
-+ SET_VHT_OPERATION_ELE_CHL_WIDTH(vht_op_ie + 2, 0);
-+ SET_VHT_OPERATION_ELE_CHL_CENTER_FREQ1(vht_op_ie + 2, 0);
-+ SET_VHT_OPERATION_ELE_CHL_CENTER_FREQ2(vht_op_ie + 2, 0);
-+ }
-+ }
-+}
-+#endif /* CONFIG_80211AC_VHT */
-diff --git linux-5.8/3rdparty/rtl8812au/core/rtw_wapi.c linux-5.8/3rdparty/rtl8812au/core/rtw_wapi.c
-new file mode 100644
-index 000000000..1c4279f02
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/core/rtw_wapi.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/core/rtw_wapi.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/core/rtw_wapi.c
+--- linux-5.11.4/3rdparty/rtl8812au/core/rtw_wapi.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/core/rtw_wapi.c 2021-03-07 18:16:17.027954777 +0200
@@ -0,0 +1,1312 @@
+/******************************************************************************
+ *
@@ -109005,11 +104889,9 @@ index 000000000..1c4279f02
+ }
+}
+#endif
-diff --git linux-5.8/3rdparty/rtl8812au/core/rtw_wapi_sms4.c linux-5.8/3rdparty/rtl8812au/core/rtw_wapi_sms4.c
-new file mode 100644
-index 000000000..4b7cf957c
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/core/rtw_wapi_sms4.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/core/rtw_wapi_sms4.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/core/rtw_wapi_sms4.c
+--- linux-5.11.4/3rdparty/rtl8812au/core/rtw_wapi_sms4.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/core/rtw_wapi_sms4.c 2021-03-07 18:16:17.027954777 +0200
@@ -0,0 +1,922 @@
+/******************************************************************************
+ *
@@ -109933,12 +105815,1149 @@ index 000000000..4b7cf957c
+#endif
+
+#endif
-diff --git linux-5.8/3rdparty/rtl8812au/core/rtw_wlan_util.c linux-5.8/3rdparty/rtl8812au/core/rtw_wlan_util.c
-new file mode 100644
-index 000000000..b4cecd116
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/core/rtw_wlan_util.c
-@@ -0,0 +1,4971 @@
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/core/rtw_vht.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/core/rtw_vht.c
+--- linux-5.11.4/3rdparty/rtl8812au/core/rtw_vht.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/core/rtw_vht.c 2021-03-07 18:16:17.027954777 +0200
+@@ -0,0 +1,1135 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#define _RTW_VHT_C
++
++#include
++#include
++
++#ifdef CONFIG_80211AC_VHT
++const u16 _vht_max_mpdu_len[] = {
++ 3895,
++ 7991,
++ 11454,
++ 0,
++};
++
++const u8 _vht_sup_ch_width_set_to_bw_cap[] = {
++ BW_CAP_80M,
++ BW_CAP_80M | BW_CAP_160M,
++ BW_CAP_80M | BW_CAP_160M | BW_CAP_80_80M,
++ 0,
++};
++
++const char *const _vht_sup_ch_width_set_str[] = {
++ "80MHz",
++ "160MHz",
++ "160MHz & 80+80MHz",
++ "BW-RSVD",
++};
++
++void dump_vht_cap_ie_content(void *sel, const u8 *buf, u32 buf_len)
++{
++ if (buf_len != VHT_CAP_IE_LEN) {
++ RTW_PRINT_SEL(sel, "Invalid VHT capability IE len:%d != %d\n", buf_len, VHT_CAP_IE_LEN);
++ return;
++ }
++
++ RTW_PRINT_SEL(sel, "cap_info:%02x %02x %02x %02x: MAX_MPDU_LEN:%u %s%s%s%s%s RX-STBC:%u MAX_AMPDU_LEN:%u\n"
++ , *(buf), *(buf + 1), *(buf + 2), *(buf + 3)
++ , vht_max_mpdu_len(GET_VHT_CAPABILITY_ELE_MAX_MPDU_LENGTH(buf))
++ , vht_sup_ch_width_set_str(GET_VHT_CAPABILITY_ELE_CHL_WIDTH(buf))
++ , GET_VHT_CAPABILITY_ELE_RX_LDPC(buf) ? " RX-LDPC" : ""
++ , GET_VHT_CAPABILITY_ELE_SHORT_GI80M(buf) ? " SGI-80" : ""
++ , GET_VHT_CAPABILITY_ELE_SHORT_GI160M(buf) ? " SGI-160" : ""
++ , GET_VHT_CAPABILITY_ELE_TX_STBC(buf) ? " TX-STBC" : ""
++ , GET_VHT_CAPABILITY_ELE_RX_STBC(buf)
++ , VHT_MAX_AMPDU_LEN(GET_VHT_CAPABILITY_ELE_MAX_RXAMPDU_FACTOR(buf))
++ );
++}
++
++void dump_vht_cap_ie(void *sel, const u8 *ie, u32 ie_len)
++{
++ const u8 *vht_cap_ie;
++ sint vht_cap_ielen;
++
++ vht_cap_ie = rtw_get_ie(ie, WLAN_EID_VHT_CAPABILITY, &vht_cap_ielen, ie_len);
++ if (!ie || vht_cap_ie != ie)
++ return;
++
++ dump_vht_cap_ie_content(sel, vht_cap_ie + 2, vht_cap_ielen);
++}
++
++const char *const _vht_op_ch_width_str[] = {
++ "20 or 40MHz",
++ "80MHz",
++ "160MHz",
++ "80+80MHz",
++ "BW-RSVD",
++};
++
++void dump_vht_op_ie_content(void *sel, const u8 *buf, u32 buf_len)
++{
++ if (buf_len != VHT_OP_IE_LEN) {
++ RTW_PRINT_SEL(sel, "Invalid VHT operation IE len:%d != %d\n", buf_len, VHT_OP_IE_LEN);
++ return;
++ }
++
++ RTW_PRINT_SEL(sel, "%s, ch0:%u, ch1:%u\n"
++ , vht_op_ch_width_str(GET_VHT_OPERATION_ELE_CHL_WIDTH(buf))
++ , GET_VHT_OPERATION_ELE_CENTER_FREQ1(buf)
++ , GET_VHT_OPERATION_ELE_CENTER_FREQ2(buf)
++ );
++}
++
++void dump_vht_op_ie(void *sel, const u8 *ie, u32 ie_len)
++{
++ const u8 *vht_op_ie;
++ sint vht_op_ielen;
++
++ vht_op_ie = rtw_get_ie(ie, WLAN_EID_VHT_OPERATION, &vht_op_ielen, ie_len);
++ if (!ie || vht_op_ie != ie)
++ return;
++
++ dump_vht_op_ie_content(sel, vht_op_ie + 2, vht_op_ielen);
++}
++
++/* 20/40/80, ShortGI, MCS Rate */
++const u16 VHT_MCS_DATA_RATE[3][2][30] = {
++ { {
++ 13, 26, 39, 52, 78, 104, 117, 130, 156, 156,
++ 26, 52, 78, 104, 156, 208, 234, 260, 312, 312,
++ 39, 78, 117, 156, 234, 312, 351, 390, 468, 520
++ }, /* Long GI, 20MHz */
++ {
++ 14, 29, 43, 58, 87, 116, 130, 144, 173, 173,
++ 29, 58, 87, 116, 173, 231, 260, 289, 347, 347,
++ 43, 87, 130, 173, 260, 347, 390, 433, 520, 578
++ }
++ }, /* Short GI, 20MHz */
++ { {
++ 27, 54, 81, 108, 162, 216, 243, 270, 324, 360,
++ 54, 108, 162, 216, 324, 432, 486, 540, 648, 720,
++ 81, 162, 243, 324, 486, 648, 729, 810, 972, 1080
++ }, /* Long GI, 40MHz */
++ {
++ 30, 60, 90, 120, 180, 240, 270, 300, 360, 400,
++ 60, 120, 180, 240, 360, 480, 540, 600, 720, 800,
++ 90, 180, 270, 360, 540, 720, 810, 900, 1080, 1200
++ }
++ }, /* Short GI, 40MHz */
++ { {
++ 59, 117, 176, 234, 351, 468, 527, 585, 702, 780,
++ 117, 234, 351, 468, 702, 936, 1053, 1170, 1404, 1560,
++ 176, 351, 527, 702, 1053, 1404, 1580, 1755, 2106, 2340
++ }, /* Long GI, 80MHz */
++ {
++ 65, 130, 195, 260, 390, 520, 585, 650, 780, 867,
++ 130, 260, 390, 520, 780, 1040, 1170, 1300, 1560, 1734,
++ 195, 390, 585, 780, 1170, 1560, 1755, 1950, 2340, 2600
++ }
++ } /* Short GI, 80MHz */
++};
++
++u8 rtw_get_vht_highest_rate(u8 *pvht_mcs_map)
++{
++ u8 i, j;
++ u8 bit_map;
++ u8 vht_mcs_rate = 0;
++
++ for (i = 0; i < 2; i++) {
++ if (pvht_mcs_map[i] != 0xff) {
++ for (j = 0; j < 8; j += 2) {
++ bit_map = (pvht_mcs_map[i] >> j) & 3;
++
++ if (bit_map != 3)
++ vht_mcs_rate = MGN_VHT1SS_MCS7 + 10 * j / 2 + i * 40 + bit_map; /* VHT rate indications begin from 0x90 */
++ }
++ }
++ }
++
++ /* RTW_INFO("HighestVHTMCSRate is %x\n", vht_mcs_rate); */
++ return vht_mcs_rate;
++}
++
++u8 rtw_vht_mcsmap_to_nss(u8 *pvht_mcs_map)
++{
++ u8 i, j;
++ u8 bit_map;
++ u8 nss = 0;
++
++ for (i = 0; i < 2; i++) {
++ if (pvht_mcs_map[i] != 0xff) {
++ for (j = 0; j < 8; j += 2) {
++ bit_map = (pvht_mcs_map[i] >> j) & 3;
++
++ if (bit_map != 3)
++ nss++;
++ }
++ }
++ }
++
++ /* RTW_INFO("%s : %dSS\n", __FUNCTION__, nss); */
++ return nss;
++}
++
++void rtw_vht_nss_to_mcsmap(u8 nss, u8 *target_mcs_map, u8 *cur_mcs_map)
++{
++ u8 i, j;
++ u8 cur_rate, target_rate;
++
++ for (i = 0; i < 2; i++) {
++ target_mcs_map[i] = 0;
++ for (j = 0; j < 8; j += 2) {
++ cur_rate = (cur_mcs_map[i] >> j) & 3;
++ if (cur_rate == 3) /* 0x3 indicates not supported that num of SS */
++ target_rate = 3;
++ else if (nss <= ((j / 2) + i * 4))
++ target_rate = 3;
++ else
++ target_rate = cur_rate;
++
++ target_mcs_map[i] |= (target_rate << j);
++ }
++ }
++
++ /* RTW_INFO("%s : %dSS\n", __FUNCTION__, nss); */
++}
++
++u16 rtw_vht_mcs_to_data_rate(u8 bw, u8 short_GI, u8 vht_mcs_rate)
++{
++ if (vht_mcs_rate > MGN_VHT3SS_MCS9)
++ vht_mcs_rate = MGN_VHT3SS_MCS9;
++ /* RTW_INFO("bw=%d, short_GI=%d, ((vht_mcs_rate - MGN_VHT1SS_MCS0)&0x3f)=%d\n", bw, short_GI, ((vht_mcs_rate - MGN_VHT1SS_MCS0)&0x3f)); */
++ return VHT_MCS_DATA_RATE[bw][short_GI][((vht_mcs_rate - MGN_VHT1SS_MCS0) & 0x3f)];
++}
++
++void rtw_vht_use_default_setting(_adapter *padapter)
++{
++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++ struct vht_priv *pvhtpriv = &pmlmepriv->vhtpriv;
++ struct registry_priv *pregistrypriv = &padapter->registrypriv;
++ BOOLEAN bHwLDPCSupport = _FALSE, bHwSTBCSupport = _FALSE;
++#ifdef CONFIG_BEAMFORMING
++ BOOLEAN bHwSupportBeamformer = _FALSE, bHwSupportBeamformee = _FALSE;
++ u8 mu_bfer, mu_bfee;
++#endif /* CONFIG_BEAMFORMING */
++ u8 rf_type = 0;
++ u8 tx_nss, rx_nss;
++ struct hal_spec_t *hal_spec = GET_HAL_SPEC(padapter);
++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++ pvhtpriv->sgi_80m = TEST_FLAG(pregistrypriv->short_gi, BIT2) ? _TRUE : _FALSE;
++
++ /* LDPC support */
++ rtw_hal_get_def_var(padapter, HAL_DEF_RX_LDPC, (u8 *)&bHwLDPCSupport);
++ CLEAR_FLAGS(pvhtpriv->ldpc_cap);
++ if (bHwLDPCSupport) {
++ if (TEST_FLAG(pregistrypriv->ldpc_cap, BIT0))
++ SET_FLAG(pvhtpriv->ldpc_cap, LDPC_VHT_ENABLE_RX);
++ }
++ rtw_hal_get_def_var(padapter, HAL_DEF_TX_LDPC, (u8 *)&bHwLDPCSupport);
++ if (bHwLDPCSupport) {
++ if (TEST_FLAG(pregistrypriv->ldpc_cap, BIT1))
++ SET_FLAG(pvhtpriv->ldpc_cap, LDPC_VHT_ENABLE_TX);
++ }
++ if (pvhtpriv->ldpc_cap)
++ RTW_INFO("[VHT] Support LDPC = 0x%02X\n", pvhtpriv->ldpc_cap);
++
++ /* STBC */
++ rtw_hal_get_def_var(padapter, HAL_DEF_TX_STBC, (u8 *)&bHwSTBCSupport);
++ CLEAR_FLAGS(pvhtpriv->stbc_cap);
++ if (bHwSTBCSupport) {
++ if (TEST_FLAG(pregistrypriv->stbc_cap, BIT1))
++ SET_FLAG(pvhtpriv->stbc_cap, STBC_VHT_ENABLE_TX);
++ }
++ rtw_hal_get_def_var(padapter, HAL_DEF_RX_STBC, (u8 *)&bHwSTBCSupport);
++ if (bHwSTBCSupport) {
++ if (TEST_FLAG(pregistrypriv->stbc_cap, BIT0))
++ SET_FLAG(pvhtpriv->stbc_cap, STBC_VHT_ENABLE_RX);
++ }
++ if (pvhtpriv->stbc_cap)
++ RTW_INFO("[VHT] Support STBC = 0x%02X\n", pvhtpriv->stbc_cap);
++
++ /* Beamforming setting */
++ CLEAR_FLAGS(pvhtpriv->beamform_cap);
++#ifdef CONFIG_BEAMFORMING
++#ifdef RTW_BEAMFORMING_VERSION_2
++ /* only enable beamforming in STA client mode */
++ if (MLME_IS_STA(padapter) && !MLME_IS_GC(padapter)
++ && !MLME_IS_ADHOC(padapter)
++ && !MLME_IS_MESH(padapter))
++#endif
++ {
++ rtw_hal_get_def_var(padapter, HAL_DEF_EXPLICIT_BEAMFORMER,
++ (u8 *)&bHwSupportBeamformer);
++ rtw_hal_get_def_var(padapter, HAL_DEF_EXPLICIT_BEAMFORMEE,
++ (u8 *)&bHwSupportBeamformee);
++ mu_bfer = _FALSE;
++ mu_bfee = _FALSE;
++ rtw_hal_get_def_var(padapter, HAL_DEF_VHT_MU_BEAMFORMER, &mu_bfer);
++ rtw_hal_get_def_var(padapter, HAL_DEF_VHT_MU_BEAMFORMEE, &mu_bfee);
++ if (TEST_FLAG(pregistrypriv->beamform_cap, BIT0) && bHwSupportBeamformer) {
++#ifdef CONFIG_CONCURRENT_MODE
++ if ((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE) {
++ SET_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_BEAMFORMER_ENABLE);
++ RTW_INFO("[VHT] CONCURRENT AP Support Beamformer\n");
++ if (TEST_FLAG(pregistrypriv->beamform_cap, BIT(2))
++ && (_TRUE == mu_bfer)) {
++ SET_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_MU_MIMO_AP_ENABLE);
++ RTW_INFO("[VHT] Support MU-MIMO AP\n");
++ }
++ } else
++ RTW_INFO("[VHT] CONCURRENT not AP ;not allow Support Beamformer\n");
++#else
++ SET_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_BEAMFORMER_ENABLE);
++ RTW_INFO("[VHT] Support Beamformer\n");
++ if (TEST_FLAG(pregistrypriv->beamform_cap, BIT(2))
++ && (_TRUE == mu_bfer)
++ && ((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE)) {
++ SET_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_MU_MIMO_AP_ENABLE);
++ RTW_INFO("[VHT] Support MU-MIMO AP\n");
++ }
++#endif
++ }
++ if (TEST_FLAG(pregistrypriv->beamform_cap, BIT1) && bHwSupportBeamformee) {
++ SET_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_BEAMFORMEE_ENABLE);
++ RTW_INFO("[VHT] Support Beamformee\n");
++ if (TEST_FLAG(pregistrypriv->beamform_cap, BIT(3))
++ && (_TRUE == mu_bfee)
++ && ((pmlmeinfo->state & 0x03) != WIFI_FW_AP_STATE)) {
++ SET_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_MU_MIMO_STA_ENABLE);
++ RTW_INFO("[VHT] Support MU-MIMO STA\n");
++ }
++ }
++ }
++#endif /* CONFIG_BEAMFORMING */
++
++ pvhtpriv->ampdu_len = pregistrypriv->ampdu_factor;
++
++ rtw_hal_get_hwreg(padapter, HW_VAR_RF_TYPE, (u8 *)(&rf_type));
++ tx_nss = rtw_min(rf_type_to_rf_tx_cnt(rf_type), hal_spec->tx_nss_num);
++ rx_nss = rtw_min(rf_type_to_rf_rx_cnt(rf_type), hal_spec->rx_nss_num);
++
++ /* for now, vhtpriv.vht_mcs_map comes from RX NSS */
++ rtw_vht_nss_to_mcsmap(rx_nss, pvhtpriv->vht_mcs_map, pregistrypriv->vht_rx_mcs_map);
++ pvhtpriv->vht_highest_rate = rtw_get_vht_highest_rate(pvhtpriv->vht_mcs_map);
++}
++
++u64 rtw_vht_mcs_map_to_bitmap(u8 *mcs_map, u8 nss)
++{
++ u8 i, j, tmp;
++ u64 bitmap = 0;
++ u8 bits_nss = nss * 2;
++
++ for (i = j = 0; i < bits_nss; i += 2, j += 10) {
++ /* every two bits means single sptial stream */
++ tmp = (mcs_map[i / 8] >> i) & 3;
++
++ switch (tmp) {
++ case 2:
++ bitmap = bitmap | (0x03ff << j);
++ break;
++ case 1:
++ bitmap = bitmap | (0x01ff << j);
++ break;
++ case 0:
++ bitmap = bitmap | (0x00ff << j);
++ break;
++ default:
++ break;
++ }
++ }
++
++ RTW_INFO("vht_mcs_map=%02x %02x, nss=%u => bitmap=%016llx\n"
++ , mcs_map[0], mcs_map[1], nss, bitmap);
++
++ return bitmap;
++}
++
++#ifdef CONFIG_BEAMFORMING
++void update_sta_vht_info_apmode_bf_cap(_adapter *padapter, struct sta_info *psta)
++{
++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++ struct vht_priv *pvhtpriv_ap = &pmlmepriv->vhtpriv;
++ struct vht_priv *pvhtpriv_sta = &psta->vhtpriv;
++ u16 cur_beamform_cap = 0;
++
++ /* B11 SU Beamformer Capable, the target supports Beamformer and we are Beamformee */
++ if (TEST_FLAG(pvhtpriv_ap->beamform_cap, BEAMFORMING_VHT_BEAMFORMER_ENABLE) &&
++ GET_VHT_CAPABILITY_ELE_SU_BFEE(pvhtpriv_sta->vht_cap)) {
++ SET_FLAG(cur_beamform_cap, BEAMFORMING_VHT_BEAMFORMEE_ENABLE);
++ /*Shift to BEAMFORMING_VHT_BEAMFORMER_STS_CAP*/
++ SET_FLAG(cur_beamform_cap, GET_VHT_CAPABILITY_ELE_SU_BFEE_STS_CAP(pvhtpriv_sta->vht_cap) << 8);
++ }
++
++ /* B12 SU Beamformee Capable, the target supports Beamformee and we are Beamformer */
++ if (TEST_FLAG(pvhtpriv_ap->beamform_cap, BEAMFORMING_VHT_BEAMFORMEE_ENABLE) &&
++ GET_VHT_CAPABILITY_ELE_SU_BFER(pvhtpriv_sta->vht_cap)) {
++ SET_FLAG(cur_beamform_cap, BEAMFORMING_VHT_BEAMFORMER_ENABLE);
++ /*Shit to BEAMFORMING_VHT_BEAMFORMEE_SOUND_DIM*/
++ SET_FLAG(cur_beamform_cap, GET_VHT_CAPABILITY_ELE_SU_BFER_SOUND_DIM_NUM(pvhtpriv_sta->vht_cap) << 12);
++ }
++
++ if (cur_beamform_cap)
++ RTW_INFO("Current STA(%d) VHT Beamforming Setting = %02X\n", psta->cmn.aid, cur_beamform_cap);
++
++ pvhtpriv_sta->beamform_cap = cur_beamform_cap;
++ psta->cmn.bf_info.vht_beamform_cap = cur_beamform_cap;
++}
++#endif
++
++void update_sta_vht_info_apmode(_adapter *padapter, PVOID sta)
++{
++ struct sta_info *psta = (struct sta_info *)sta;
++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++ struct vht_priv *pvhtpriv_ap = &pmlmepriv->vhtpriv;
++ struct vht_priv *pvhtpriv_sta = &psta->vhtpriv;
++ u8 cur_ldpc_cap = 0, cur_stbc_cap = 0;
++ s8 bw_mode = -1;
++ u8 *pcap_mcs;
++
++ if (pvhtpriv_sta->vht_option == _FALSE)
++ return;
++
++ if (pvhtpriv_sta->op_present) {
++ switch (GET_VHT_OPERATION_ELE_CHL_WIDTH(pvhtpriv_sta->vht_op)) {
++ case 1: /* 80MHz */
++ case 2: /* 160MHz */
++ case 3: /* 80+80 */
++ bw_mode = CHANNEL_WIDTH_80; /* only support up to 80MHz for now */
++ break;
++ }
++ }
++
++ if (pvhtpriv_sta->notify_present)
++ bw_mode = GET_VHT_OPERATING_MODE_FIELD_CHNL_WIDTH(&pvhtpriv_sta->vht_op_mode_notify);
++ else if (MLME_IS_AP(padapter)) {
++ /* for VHT client without Operating Mode Notify IE; minimal 80MHz */
++ if (bw_mode < CHANNEL_WIDTH_80)
++ bw_mode = CHANNEL_WIDTH_80;
++ }
++
++ if (bw_mode != -1)
++ psta->cmn.bw_mode = bw_mode; /* update bw_mode only if get value from VHT IEs */
++
++ psta->cmn.ra_info.is_vht_enable = _TRUE;
++
++ /* B4 Rx LDPC */
++ if (TEST_FLAG(pvhtpriv_ap->ldpc_cap, LDPC_VHT_ENABLE_TX) &&
++ GET_VHT_CAPABILITY_ELE_RX_LDPC(pvhtpriv_sta->vht_cap)) {
++ SET_FLAG(cur_ldpc_cap, (LDPC_VHT_ENABLE_TX | LDPC_VHT_CAP_TX));
++ RTW_INFO("Current STA(%d) VHT LDPC = %02X\n", psta->cmn.aid, cur_ldpc_cap);
++ }
++ pvhtpriv_sta->ldpc_cap = cur_ldpc_cap;
++
++ if (psta->cmn.bw_mode > pmlmeext->cur_bwmode)
++ psta->cmn.bw_mode = pmlmeext->cur_bwmode;
++
++ if (psta->cmn.bw_mode == CHANNEL_WIDTH_80) {
++ /* B5 Short GI for 80 MHz */
++ pvhtpriv_sta->sgi_80m = (GET_VHT_CAPABILITY_ELE_SHORT_GI80M(pvhtpriv_sta->vht_cap) & pvhtpriv_ap->sgi_80m) ? _TRUE : _FALSE;
++ /* RTW_INFO("Current STA ShortGI80MHz = %d\n", pvhtpriv_sta->sgi_80m); */
++ } else if (psta->cmn.bw_mode >= CHANNEL_WIDTH_160) {
++ /* B5 Short GI for 80 MHz */
++ pvhtpriv_sta->sgi_80m = (GET_VHT_CAPABILITY_ELE_SHORT_GI160M(pvhtpriv_sta->vht_cap) & pvhtpriv_ap->sgi_80m) ? _TRUE : _FALSE;
++ /* RTW_INFO("Current STA ShortGI160MHz = %d\n", pvhtpriv_sta->sgi_80m); */
++ }
++
++ /* B8 B9 B10 Rx STBC */
++ if (TEST_FLAG(pvhtpriv_ap->stbc_cap, STBC_VHT_ENABLE_TX) &&
++ GET_VHT_CAPABILITY_ELE_RX_STBC(pvhtpriv_sta->vht_cap)) {
++ SET_FLAG(cur_stbc_cap, (STBC_VHT_ENABLE_TX | STBC_VHT_CAP_TX));
++ RTW_INFO("Current STA(%d) VHT STBC = %02X\n", psta->cmn.aid, cur_stbc_cap);
++ }
++ pvhtpriv_sta->stbc_cap = cur_stbc_cap;
++
++#ifdef CONFIG_BEAMFORMING
++ update_sta_vht_info_apmode_bf_cap(padapter, psta);
++#endif
++
++ /* B23 B24 B25 Maximum A-MPDU Length Exponent */
++ pvhtpriv_sta->ampdu_len = GET_VHT_CAPABILITY_ELE_MAX_RXAMPDU_FACTOR(pvhtpriv_sta->vht_cap);
++
++ pcap_mcs = GET_VHT_CAPABILITY_ELE_RX_MCS(pvhtpriv_sta->vht_cap);
++ _rtw_memcpy(pvhtpriv_sta->vht_mcs_map, pcap_mcs, 2);
++ pvhtpriv_sta->vht_highest_rate = rtw_get_vht_highest_rate(pvhtpriv_sta->vht_mcs_map);
++}
++
++void update_hw_vht_param(_adapter *padapter)
++{
++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++ struct vht_priv *pvhtpriv = &pmlmepriv->vhtpriv;
++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++ u8 ht_AMPDU_len;
++
++ ht_AMPDU_len = pmlmeinfo->HT_caps.u.HT_cap_element.AMPDU_para & 0x03;
++
++ if (pvhtpriv->ampdu_len > ht_AMPDU_len)
++ rtw_hal_set_hwreg(padapter, HW_VAR_AMPDU_FACTOR, (u8 *)(&pvhtpriv->ampdu_len));
++}
++
++#ifdef ROKU_PRIVATE
++u8 VHT_get_ss_from_map(u8 *vht_mcs_map)
++{
++ u8 i, j;
++ u8 ss = 0;
++
++ for (i = 0; i < 2; i++) {
++ if (vht_mcs_map[i] != 0xff) {
++ for (j = 0; j < 8; j += 2) {
++ if (((vht_mcs_map[i] >> j) & 0x03) == 0x03)
++ break;
++ ss++;
++ }
++ }
++
++ }
++
++return ss;
++}
++
++void VHT_caps_handler_infra_ap(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE)
++{
++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++ struct vht_priv_infra_ap *pvhtpriv = &pmlmepriv->vhtpriv_infra_ap;
++ u8 cur_stbc_cap_infra_ap = 0;
++ u16 cur_beamform_cap_infra_ap = 0;
++ u8 *pcap_mcs;
++ u8 *pcap_mcs_tx;
++ u8 Rx_ss = 0, Tx_ss = 0;
++
++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++
++ if (pIE == NULL)
++ return;
++
++ pmlmeinfo->ht_vht_received |= BIT(1);
++
++ pvhtpriv->ldpc_cap_infra_ap = GET_VHT_CAPABILITY_ELE_RX_LDPC(pIE->data);
++
++ if (GET_VHT_CAPABILITY_ELE_RX_STBC(pIE->data))
++ SET_FLAG(cur_stbc_cap_infra_ap, STBC_VHT_ENABLE_RX);
++ if (GET_VHT_CAPABILITY_ELE_TX_STBC(pIE->data))
++ SET_FLAG(cur_stbc_cap_infra_ap, STBC_VHT_ENABLE_TX);
++ pvhtpriv->stbc_cap_infra_ap = cur_stbc_cap_infra_ap;
++
++ /*store ap info for channel bandwidth*/
++ pvhtpriv->channel_width_infra_ap = GET_VHT_CAPABILITY_ELE_CHL_WIDTH(pIE->data);
++
++ /*check B11: SU Beamformer Capable and B12: SU Beamformee B19: MU Beamformer B20:MU Beamformee*/
++ if (GET_VHT_CAPABILITY_ELE_SU_BFER(pIE->data))
++ SET_FLAG(cur_beamform_cap_infra_ap, BEAMFORMING_VHT_BEAMFORMER_ENABLE);
++ if (GET_VHT_CAPABILITY_ELE_SU_BFEE(pIE->data))
++ SET_FLAG(cur_beamform_cap_infra_ap, BEAMFORMING_VHT_BEAMFORMEE_ENABLE);
++ if (GET_VHT_CAPABILITY_ELE_MU_BFER(pIE->data))
++ SET_FLAG(cur_beamform_cap_infra_ap, BEAMFORMING_VHT_MU_MIMO_AP_ENABLE);
++ if (GET_VHT_CAPABILITY_ELE_MU_BFEE(pIE->data))
++ SET_FLAG(cur_beamform_cap_infra_ap, BEAMFORMING_VHT_MU_MIMO_STA_ENABLE);
++ pvhtpriv->beamform_cap_infra_ap = cur_beamform_cap_infra_ap;
++
++ /*store information about vht_mcs_set*/
++ pcap_mcs = GET_VHT_CAPABILITY_ELE_RX_MCS(pIE->data);
++ pcap_mcs_tx = GET_VHT_CAPABILITY_ELE_TX_MCS(pIE->data);
++ _rtw_memcpy(pvhtpriv->vht_mcs_map_infra_ap, pcap_mcs, 2);
++ _rtw_memcpy(pvhtpriv->vht_mcs_map_tx_infra_ap, pcap_mcs_tx, 2);
++
++ Rx_ss = VHT_get_ss_from_map(pvhtpriv->vht_mcs_map_infra_ap);
++ Tx_ss = VHT_get_ss_from_map(pvhtpriv->vht_mcs_map_tx_infra_ap);
++ if (Rx_ss >= Tx_ss) {
++ pvhtpriv->number_of_streams_infra_ap = Rx_ss;
++ } else{
++ pvhtpriv->number_of_streams_infra_ap = Tx_ss;
++ }
++
++}
++#endif /* ROKU_PRIVATE */
++
++void VHT_caps_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE)
++{
++ struct hal_spec_t *hal_spec = GET_HAL_SPEC(padapter);
++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++ struct vht_priv *pvhtpriv = &pmlmepriv->vhtpriv;
++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++ u8 cur_ldpc_cap = 0, cur_stbc_cap = 0, rf_type = RF_1T1R, tx_nss = 0;
++ u16 cur_beamform_cap = 0;
++ u8 *pcap_mcs;
++
++ if (pIE == NULL)
++ return;
++
++ if (pvhtpriv->vht_option == _FALSE)
++ return;
++
++ pmlmeinfo->VHT_enable = 1;
++
++ /* B4 Rx LDPC */
++ if (TEST_FLAG(pvhtpriv->ldpc_cap, LDPC_VHT_ENABLE_TX) &&
++ GET_VHT_CAPABILITY_ELE_RX_LDPC(pIE->data)) {
++ SET_FLAG(cur_ldpc_cap, (LDPC_VHT_ENABLE_TX | LDPC_VHT_CAP_TX));
++ RTW_INFO("Current VHT LDPC Setting = %02X\n", cur_ldpc_cap);
++ }
++ pvhtpriv->ldpc_cap = cur_ldpc_cap;
++
++ /* B5 Short GI for 80 MHz */
++ pvhtpriv->sgi_80m = (GET_VHT_CAPABILITY_ELE_SHORT_GI80M(pIE->data) & pvhtpriv->sgi_80m) ? _TRUE : _FALSE;
++ /* RTW_INFO("Current ShortGI80MHz = %d\n", pvhtpriv->sgi_80m); */
++
++ /* B8 B9 B10 Rx STBC */
++ if (TEST_FLAG(pvhtpriv->stbc_cap, STBC_VHT_ENABLE_TX) &&
++ GET_VHT_CAPABILITY_ELE_RX_STBC(pIE->data)) {
++ SET_FLAG(cur_stbc_cap, (STBC_VHT_ENABLE_TX | STBC_VHT_CAP_TX));
++ RTW_INFO("Current VHT STBC Setting = %02X\n", cur_stbc_cap);
++ }
++ pvhtpriv->stbc_cap = cur_stbc_cap;
++#ifdef CONFIG_BEAMFORMING
++#ifdef RTW_BEAMFORMING_VERSION_2
++ /*
++ * B11 SU Beamformer Capable,
++ * the target supports Beamformer and we are Beamformee
++ */
++ if (TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_BEAMFORMEE_ENABLE)
++ && GET_VHT_CAPABILITY_ELE_SU_BFER(pIE->data)) {
++ SET_FLAG(cur_beamform_cap, BEAMFORMING_VHT_BEAMFORMEE_ENABLE);
++
++ /* Shift to BEAMFORMING_VHT_BEAMFORMEE_STS_CAP */
++ SET_FLAG(cur_beamform_cap, GET_VHT_CAPABILITY_ELE_SU_BFEE_STS_CAP(pIE->data) << 8);
++
++ /*
++ * B19 MU Beamformer Capable,
++ * the target supports Beamformer and we are Beamformee
++ */
++ if (TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_MU_MIMO_STA_ENABLE)
++ && GET_VHT_CAPABILITY_ELE_MU_BFER(pIE->data))
++ SET_FLAG(cur_beamform_cap, BEAMFORMING_VHT_MU_MIMO_STA_ENABLE);
++ }
++
++ /*
++ * B12 SU Beamformee Capable,
++ * the target supports Beamformee and we are Beamformer
++ */
++ if (TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_BEAMFORMER_ENABLE)
++ && GET_VHT_CAPABILITY_ELE_SU_BFEE(pIE->data)) {
++ SET_FLAG(cur_beamform_cap, BEAMFORMING_VHT_BEAMFORMER_ENABLE);
++
++ /* Shit to BEAMFORMING_VHT_BEAMFORMER_SOUND_DIM */
++ SET_FLAG(cur_beamform_cap, GET_VHT_CAPABILITY_ELE_SU_BFER_SOUND_DIM_NUM(pIE->data) << 12);
++
++ /*
++ * B20 MU Beamformee Capable,
++ * the target supports Beamformee and we are Beamformer
++ */
++ if (TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_MU_MIMO_AP_ENABLE)
++ && GET_VHT_CAPABILITY_ELE_MU_BFEE(pIE->data))
++ SET_FLAG(cur_beamform_cap, BEAMFORMING_VHT_MU_MIMO_AP_ENABLE);
++ }
++
++ pvhtpriv->beamform_cap = cur_beamform_cap;
++ RTW_INFO("Current VHT Beamforming Setting=0x%04X\n", cur_beamform_cap);
++#else /* !RTW_BEAMFORMING_VERSION_2 */
++ /* B11 SU Beamformer Capable, the target supports Beamformer and we are Beamformee */
++ if (TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_BEAMFORMER_ENABLE) &&
++ GET_VHT_CAPABILITY_ELE_SU_BFEE(pIE->data)) {
++ SET_FLAG(cur_beamform_cap, BEAMFORMING_VHT_BEAMFORMEE_ENABLE);
++ /*Shift to BEAMFORMING_VHT_BEAMFORMER_STS_CAP*/
++ SET_FLAG(cur_beamform_cap, GET_VHT_CAPABILITY_ELE_SU_BFEE_STS_CAP(pIE->data) << 8);
++ }
++
++ /* B12 SU Beamformee Capable, the target supports Beamformee and we are Beamformer */
++ if (TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_BEAMFORMEE_ENABLE) &&
++ GET_VHT_CAPABILITY_ELE_SU_BFER(pIE->data)) {
++ SET_FLAG(cur_beamform_cap, BEAMFORMING_VHT_BEAMFORMER_ENABLE);
++ /*Shit to BEAMFORMING_VHT_BEAMFORMEE_SOUND_DIM*/
++ SET_FLAG(cur_beamform_cap, GET_VHT_CAPABILITY_ELE_SU_BFER_SOUND_DIM_NUM(pIE->data) << 12);
++
++ }
++ pvhtpriv->beamform_cap = cur_beamform_cap;
++ if (cur_beamform_cap)
++ RTW_INFO("Current VHT Beamforming Setting = %02X\n", cur_beamform_cap);
++#endif /* !RTW_BEAMFORMING_VERSION_2 */
++#endif /* CONFIG_BEAMFORMING */
++ /* B23 B24 B25 Maximum A-MPDU Length Exponent */
++ pvhtpriv->ampdu_len = GET_VHT_CAPABILITY_ELE_MAX_RXAMPDU_FACTOR(pIE->data);
++
++ pcap_mcs = GET_VHT_CAPABILITY_ELE_RX_MCS(pIE->data);
++ rtw_hal_get_hwreg(padapter, HW_VAR_RF_TYPE, (u8 *)(&rf_type));
++ tx_nss = rtw_min(rf_type_to_rf_tx_cnt(rf_type), hal_spec->tx_nss_num);
++ rtw_vht_nss_to_mcsmap(tx_nss, pvhtpriv->vht_mcs_map, pcap_mcs);
++ pvhtpriv->vht_highest_rate = rtw_get_vht_highest_rate(pvhtpriv->vht_mcs_map);
++}
++
++void VHT_operation_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE)
++{
++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++ struct vht_priv *pvhtpriv = &pmlmepriv->vhtpriv;
++
++ if (pIE == NULL)
++ return;
++
++ if (pvhtpriv->vht_option == _FALSE)
++ return;
++}
++
++void rtw_process_vht_op_mode_notify(_adapter *padapter, u8 *pframe, PVOID sta)
++{
++ struct sta_info *psta = (struct sta_info *)sta;
++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++ struct vht_priv *pvhtpriv = &pmlmepriv->vhtpriv;
++ struct registry_priv *regsty = adapter_to_regsty(padapter);
++ u8 target_bw;
++ u8 target_rxss, current_rxss;
++ u8 update_ra = _FALSE;
++ u8 tx_nss = 0, rf_type = RF_1T1R;
++ struct hal_spec_t *hal_spec = GET_HAL_SPEC(padapter);
++
++ if (pvhtpriv->vht_option == _FALSE)
++ return;
++
++ target_bw = GET_VHT_OPERATING_MODE_FIELD_CHNL_WIDTH(pframe);
++
++ rtw_hal_get_hwreg(padapter, HW_VAR_RF_TYPE, (u8 *)(&rf_type));
++ tx_nss = rtw_min(rf_type_to_rf_tx_cnt(rf_type), hal_spec->tx_nss_num);
++ target_rxss = rtw_min(tx_nss, (GET_VHT_OPERATING_MODE_FIELD_RX_NSS(pframe) + 1));
++
++ if (target_bw != psta->cmn.bw_mode) {
++ if (hal_is_bw_support(padapter, target_bw)
++ && REGSTY_IS_BW_5G_SUPPORT(regsty, target_bw)
++ ) {
++ update_ra = _TRUE;
++ psta->cmn.bw_mode = target_bw;
++ }
++ }
++
++ current_rxss = rtw_vht_mcsmap_to_nss(psta->vhtpriv.vht_mcs_map);
++ if (target_rxss != current_rxss) {
++ u8 vht_mcs_map[2] = {};
++
++ update_ra = _TRUE;
++
++ rtw_vht_nss_to_mcsmap(target_rxss, vht_mcs_map, psta->vhtpriv.vht_mcs_map);
++ _rtw_memcpy(psta->vhtpriv.vht_mcs_map, vht_mcs_map, 2);
++
++ rtw_hal_update_sta_ra_info(padapter, psta);
++ }
++
++ if (update_ra)
++ rtw_dm_ra_mask_wk_cmd(padapter, (u8 *)psta);
++}
++
++u32 rtw_build_vht_operation_ie(_adapter *padapter, u8 *pbuf, u8 channel)
++{
++ struct registry_priv *pregistrypriv = &padapter->registrypriv;
++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++ struct vht_priv *pvhtpriv = &pmlmepriv->vhtpriv;
++ /* struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; */
++ u8 ChnlWidth, center_freq, bw_mode;
++ u32 len = 0;
++ u8 operation[5];
++
++ _rtw_memset(operation, 0, 5);
++
++ bw_mode = REGSTY_BW_5G(pregistrypriv); /* TODO: control op bw with other info */
++
++ if (hal_chk_bw_cap(padapter, BW_CAP_80M | BW_CAP_160M)
++ && REGSTY_BW_5G(pregistrypriv) >= CHANNEL_WIDTH_80
++ ) {
++ center_freq = rtw_get_center_ch(channel, bw_mode, HAL_PRIME_CHNL_OFFSET_LOWER);
++ ChnlWidth = 1;
++ } else {
++ center_freq = 0;
++ ChnlWidth = 0;
++ }
++
++
++ SET_VHT_OPERATION_ELE_CHL_WIDTH(operation, ChnlWidth);
++ /* center frequency */
++ SET_VHT_OPERATION_ELE_CHL_CENTER_FREQ1(operation, center_freq);/* Todo: need to set correct center channel */
++ SET_VHT_OPERATION_ELE_CHL_CENTER_FREQ2(operation, 0);
++
++ _rtw_memcpy(operation + 3, pvhtpriv->vht_mcs_map, 2);
++
++ rtw_set_ie(pbuf, EID_VHTOperation, 5, operation, &len);
++
++ return len;
++}
++
++u32 rtw_build_vht_op_mode_notify_ie(_adapter *padapter, u8 *pbuf, u8 bw)
++{
++ /* struct registry_priv *pregistrypriv = &padapter->registrypriv; */
++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++ struct vht_priv *pvhtpriv = &pmlmepriv->vhtpriv;
++ u32 len = 0;
++ u8 opmode = 0;
++ u8 chnl_width, rx_nss;
++
++ chnl_width = bw;
++ rx_nss = rtw_vht_mcsmap_to_nss(pvhtpriv->vht_mcs_map);
++
++ SET_VHT_OPERATING_MODE_FIELD_CHNL_WIDTH(&opmode, chnl_width);
++ SET_VHT_OPERATING_MODE_FIELD_RX_NSS(&opmode, (rx_nss - 1));
++ SET_VHT_OPERATING_MODE_FIELD_RX_NSS_TYPE(&opmode, 0); /* Todo */
++
++ pvhtpriv->vht_op_mode_notify = opmode;
++
++ pbuf = rtw_set_ie(pbuf, EID_OpModeNotification, 1, &opmode, &len);
++
++ return len;
++}
++
++u32 rtw_build_vht_cap_ie(_adapter *padapter, u8 *pbuf)
++{
++ u8 bw, rf_num, rx_stbc_nss = 0;
++ u16 HighestRate;
++ u8 *pcap, *pcap_mcs;
++ u32 len = 0;
++ u32 rx_packet_offset, max_recvbuf_sz;
++ struct registry_priv *pregistrypriv = &padapter->registrypriv;
++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++ struct vht_priv *pvhtpriv = &pmlmepriv->vhtpriv;
++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++
++ pcap = pvhtpriv->vht_cap;
++ _rtw_memset(pcap, 0, 32);
++
++ /* B0 B1 Maximum MPDU Length */
++ rtw_hal_get_def_var(padapter, HAL_DEF_RX_PACKET_OFFSET, &rx_packet_offset);
++ rtw_hal_get_def_var(padapter, HAL_DEF_MAX_RECVBUF_SZ, &max_recvbuf_sz);
++
++ RTW_DBG("%s, line%d, Available RX buf size = %d bytes\n", __FUNCTION__, __LINE__, max_recvbuf_sz - rx_packet_offset);
++
++ if ((max_recvbuf_sz - rx_packet_offset) >= 11454) {
++ SET_VHT_CAPABILITY_ELE_MAX_MPDU_LENGTH(pcap, 2);
++ RTW_INFO("%s, line%d, Set MAX MPDU len = 11454 bytes\n", __FUNCTION__, __LINE__);
++ } else if ((max_recvbuf_sz - rx_packet_offset) >= 7991) {
++ SET_VHT_CAPABILITY_ELE_MAX_MPDU_LENGTH(pcap, 1);
++ RTW_INFO("%s, line%d, Set MAX MPDU len = 7991 bytes\n", __FUNCTION__, __LINE__);
++ } else if ((max_recvbuf_sz - rx_packet_offset) >= 3895) {
++ SET_VHT_CAPABILITY_ELE_MAX_MPDU_LENGTH(pcap, 0);
++ RTW_INFO("%s, line%d, Set MAX MPDU len = 3895 bytes\n", __FUNCTION__, __LINE__);
++ } else
++ RTW_ERR("%s, line%d, Error!! Available RX buf size < 3895 bytes\n", __FUNCTION__, __LINE__);
++
++ /* B2 B3 Supported Channel Width Set */
++ if (hal_chk_bw_cap(padapter, BW_CAP_160M) && REGSTY_IS_BW_5G_SUPPORT(pregistrypriv, CHANNEL_WIDTH_160)) {
++ if (hal_chk_bw_cap(padapter, BW_CAP_80_80M) && REGSTY_IS_BW_5G_SUPPORT(pregistrypriv, CHANNEL_WIDTH_80_80))
++ SET_VHT_CAPABILITY_ELE_CHL_WIDTH(pcap, 2);
++ else
++ SET_VHT_CAPABILITY_ELE_CHL_WIDTH(pcap, 1);
++ } else
++ SET_VHT_CAPABILITY_ELE_CHL_WIDTH(pcap, 0);
++
++ /* B4 Rx LDPC */
++ if (TEST_FLAG(pvhtpriv->ldpc_cap, LDPC_VHT_ENABLE_RX)) {
++ SET_VHT_CAPABILITY_ELE_RX_LDPC(pcap, 1);
++ RTW_INFO("[VHT] Declare supporting RX LDPC\n");
++ }
++
++ /* B5 ShortGI for 80MHz */
++ SET_VHT_CAPABILITY_ELE_SHORT_GI80M(pcap, pvhtpriv->sgi_80m ? 1 : 0); /* We can receive Short GI of 80M */
++ if (pvhtpriv->sgi_80m)
++ RTW_INFO("[VHT] Declare supporting SGI 80MHz\n");
++
++ /* B6 ShortGI for 160MHz */
++ /* SET_VHT_CAPABILITY_ELE_SHORT_GI160M(pcap, pvhtpriv->sgi_80m? 1 : 0); */
++
++ /* B7 Tx STBC */
++ if (TEST_FLAG(pvhtpriv->stbc_cap, STBC_VHT_ENABLE_TX)) {
++ SET_VHT_CAPABILITY_ELE_TX_STBC(pcap, 1);
++ RTW_INFO("[VHT] Declare supporting TX STBC\n");
++ }
++
++ /* B8 B9 B10 Rx STBC */
++ if (TEST_FLAG(pvhtpriv->stbc_cap, STBC_VHT_ENABLE_RX)) {
++ rtw_hal_get_def_var(padapter, HAL_DEF_RX_STBC, (u8 *)(&rx_stbc_nss));
++
++ SET_VHT_CAPABILITY_ELE_RX_STBC(pcap, rx_stbc_nss);
++ RTW_INFO("[VHT] Declare supporting RX STBC = %d\n", rx_stbc_nss);
++ }
++ #ifdef CONFIG_BEAMFORMING
++ /* B11 SU Beamformer Capable */
++ if (TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_BEAMFORMER_ENABLE)) {
++ SET_VHT_CAPABILITY_ELE_SU_BFER(pcap, 1);
++ RTW_INFO("[VHT] Declare supporting SU Bfer\n");
++ /* B16 17 18 Number of Sounding Dimensions */
++ rtw_hal_get_def_var(padapter, HAL_DEF_BEAMFORMER_CAP, (u8 *)&rf_num);
++ SET_VHT_CAPABILITY_ELE_SOUNDING_DIMENSIONS(pcap, rf_num);
++ /* B19 MU Beamformer Capable */
++ if (TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_MU_MIMO_AP_ENABLE)) {
++ SET_VHT_CAPABILITY_ELE_MU_BFER(pcap, 1);
++ RTW_INFO("[VHT] Declare supporting MU Bfer\n");
++ }
++ }
++
++ /* B12 SU Beamformee Capable */
++ if (TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_BEAMFORMEE_ENABLE)) {
++ SET_VHT_CAPABILITY_ELE_SU_BFEE(pcap, 1);
++ RTW_INFO("[VHT] Declare supporting SU Bfee\n");
++
++ rtw_hal_get_def_var(padapter, HAL_DEF_BEAMFORMEE_CAP, (u8 *)&rf_num);
++
++ /* IOT action suggested by Yu Chen 2017/3/3 */
++#ifdef CONFIG_80211AC_VHT
++ if ((pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_BROADCOM) &&
++ !pvhtpriv->ap_is_mu_bfer)
++ rf_num = (rf_num >= 2 ? 2 : rf_num);
++#endif
++ /* B13 14 15 Compressed Steering Number of Beamformer Antennas Supported */
++ SET_VHT_CAPABILITY_ELE_BFER_ANT_SUPP(pcap, rf_num);
++ /* B20 SU Beamformee Capable */
++ if (TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_MU_MIMO_STA_ENABLE)) {
++ SET_VHT_CAPABILITY_ELE_MU_BFEE(pcap, 1);
++ RTW_INFO("[VHT] Declare supporting MU Bfee\n");
++ }
++ }
++ #endif/*CONFIG_BEAMFORMING*/
++
++ /* B21 VHT TXOP PS */
++ SET_VHT_CAPABILITY_ELE_TXOP_PS(pcap, 0);
++ /* B22 +HTC-VHT Capable */
++ SET_VHT_CAPABILITY_ELE_HTC_VHT(pcap, 1);
++ /* B23 24 25 Maximum A-MPDU Length Exponent */
++ if (pregistrypriv->ampdu_factor != 0xFE)
++ SET_VHT_CAPABILITY_ELE_MAX_RXAMPDU_FACTOR(pcap, pregistrypriv->ampdu_factor);
++ else
++ SET_VHT_CAPABILITY_ELE_MAX_RXAMPDU_FACTOR(pcap, 7);
++ /* B26 27 VHT Link Adaptation Capable */
++ SET_VHT_CAPABILITY_ELE_LINK_ADAPTION(pcap, 0);
++
++ pcap_mcs = GET_VHT_CAPABILITY_ELE_RX_MCS(pcap);
++ _rtw_memcpy(pcap_mcs, pvhtpriv->vht_mcs_map, 2);
++
++ pcap_mcs = GET_VHT_CAPABILITY_ELE_TX_MCS(pcap);
++ _rtw_memcpy(pcap_mcs, pvhtpriv->vht_mcs_map, 2);
++
++ /* find the largest bw supported by both registry and hal */
++ bw = hal_largest_bw(padapter, REGSTY_BW_5G(pregistrypriv));
++
++ HighestRate = VHT_MCS_DATA_RATE[bw][pvhtpriv->sgi_80m][((pvhtpriv->vht_highest_rate - MGN_VHT1SS_MCS0) & 0x3f)];
++ HighestRate = (HighestRate + 1) >> 1;
++
++ SET_VHT_CAPABILITY_ELE_MCS_RX_HIGHEST_RATE(pcap, HighestRate); /* indicate we support highest rx rate is 600Mbps. */
++ SET_VHT_CAPABILITY_ELE_MCS_TX_HIGHEST_RATE(pcap, HighestRate); /* indicate we support highest tx rate is 600Mbps. */
++
++ pbuf = rtw_set_ie(pbuf, EID_VHTCapability, 12, pcap, &len);
++
++ return len;
++}
++
++u32 rtw_restructure_vht_ie(_adapter *padapter, u8 *in_ie, u8 *out_ie, uint in_len, uint *pout_len)
++{
++ struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter);
++ RT_CHANNEL_INFO *chset = rfctl->channel_set;
++ u32 ielen;
++ u8 max_bw;
++ u8 oper_ch, oper_bw = CHANNEL_WIDTH_20, oper_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
++ u8 *out_vht_op_ie, *ht_op_ie, *vht_cap_ie, *vht_op_ie;
++ struct registry_priv *pregistrypriv = &padapter->registrypriv;
++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++ struct vht_priv *pvhtpriv = &pmlmepriv->vhtpriv;
++
++ rtw_vht_use_default_setting(padapter);
++
++ ht_op_ie = rtw_get_ie(in_ie + 12, WLAN_EID_HT_OPERATION, &ielen, in_len - 12);
++ if (!ht_op_ie || ielen != HT_OP_IE_LEN)
++ goto exit;
++ vht_cap_ie = rtw_get_ie(in_ie + 12, EID_VHTCapability, &ielen, in_len - 12);
++ if (!vht_cap_ie || ielen != VHT_CAP_IE_LEN)
++ goto exit;
++ vht_op_ie = rtw_get_ie(in_ie + 12, EID_VHTOperation, &ielen, in_len - 12);
++ if (!vht_op_ie || ielen != VHT_OP_IE_LEN)
++ goto exit;
++
++ /* VHT Capabilities element */
++ *pout_len += rtw_build_vht_cap_ie(padapter, out_ie + *pout_len);
++
++
++ /* VHT Operation element */
++ out_vht_op_ie = out_ie + *pout_len;
++ rtw_set_ie(out_vht_op_ie, EID_VHTOperation, VHT_OP_IE_LEN, vht_op_ie + 2 , pout_len);
++
++ /* get primary channel from HT_OP_IE */
++ oper_ch = GET_HT_OP_ELE_PRI_CHL(ht_op_ie + 2);
++
++ /* find the largest bw supported by both registry and hal */
++ max_bw = hal_largest_bw(padapter, REGSTY_BW_5G(pregistrypriv));
++
++ if (max_bw >= CHANNEL_WIDTH_40) {
++ /* get bw offset form HT_OP_IE */
++ if (GET_HT_OP_ELE_STA_CHL_WIDTH(ht_op_ie + 2)) {
++ switch (GET_HT_OP_ELE_2ND_CHL_OFFSET(ht_op_ie + 2)) {
++ case SCA:
++ oper_bw = CHANNEL_WIDTH_40;
++ oper_offset = HAL_PRIME_CHNL_OFFSET_LOWER;
++ break;
++ case SCB:
++ oper_bw = CHANNEL_WIDTH_40;
++ oper_offset = HAL_PRIME_CHNL_OFFSET_UPPER;
++ break;
++ }
++ }
++
++ if (oper_bw == CHANNEL_WIDTH_40) {
++ switch (GET_VHT_OPERATION_ELE_CHL_WIDTH(vht_op_ie + 2)) {
++ case 1: /* 80MHz */
++ case 2: /* 160MHz */
++ case 3: /* 80+80 */
++ oper_bw = CHANNEL_WIDTH_80; /* only support up to 80MHz for now */
++ break;
++ }
++
++ oper_bw = rtw_min(oper_bw, max_bw);
++
++ /* try downgrage bw to fit in channel plan setting */
++ while (!rtw_chset_is_chbw_valid(chset, oper_ch, oper_bw, oper_offset)
++ || (IS_DFS_SLAVE_WITH_RD(rfctl)
++ && !rtw_odm_dfs_domain_unknown(rfctl_to_dvobj(rfctl))
++ && rtw_chset_is_chbw_non_ocp(chset, oper_ch, oper_bw, oper_offset))
++ ) {
++ oper_bw--;
++ if (oper_bw == CHANNEL_WIDTH_20) {
++ oper_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
++ break;
++ }
++ }
++ }
++ }
++
++ rtw_warn_on(!rtw_chset_is_chbw_valid(chset, oper_ch, oper_bw, oper_offset));
++ if (IS_DFS_SLAVE_WITH_RD(rfctl) && !rtw_odm_dfs_domain_unknown(rfctl_to_dvobj(rfctl)))
++ rtw_warn_on(rtw_chset_is_chbw_non_ocp(chset, oper_ch, oper_bw, oper_offset));
++
++ /* update VHT_OP_IE */
++ if (oper_bw < CHANNEL_WIDTH_80) {
++ SET_VHT_OPERATION_ELE_CHL_WIDTH(out_vht_op_ie + 2, 0);
++ SET_VHT_OPERATION_ELE_CHL_CENTER_FREQ1(out_vht_op_ie + 2, 0);
++ SET_VHT_OPERATION_ELE_CHL_CENTER_FREQ2(out_vht_op_ie + 2, 0);
++ } else if (oper_bw == CHANNEL_WIDTH_80) {
++ u8 cch = rtw_get_center_ch(oper_ch, oper_bw, oper_offset);
++
++ SET_VHT_OPERATION_ELE_CHL_WIDTH(out_vht_op_ie + 2, 1);
++ SET_VHT_OPERATION_ELE_CHL_CENTER_FREQ1(out_vht_op_ie + 2, cch);
++ SET_VHT_OPERATION_ELE_CHL_CENTER_FREQ2(out_vht_op_ie + 2, 0);
++ } else {
++ RTW_ERR(FUNC_ADPT_FMT" unsupported BW:%u\n", FUNC_ADPT_ARG(padapter), oper_bw);
++ rtw_warn_on(1);
++ }
++
++ /* Operating Mode Notification element */
++ *pout_len += rtw_build_vht_op_mode_notify_ie(padapter, out_ie + *pout_len, oper_bw);
++
++ pvhtpriv->vht_option = _TRUE;
++
++exit:
++ return pvhtpriv->vht_option;
++
++}
++
++void VHTOnAssocRsp(_adapter *padapter)
++{
++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
++ struct vht_priv *pvhtpriv = &pmlmepriv->vhtpriv;
++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
++ u8 ht_AMPDU_len;
++
++ RTW_INFO("%s\n", __FUNCTION__);
++
++ if (!pmlmeinfo->HT_enable)
++ return;
++
++ if (!pmlmeinfo->VHT_enable)
++ return;
++
++ ht_AMPDU_len = pmlmeinfo->HT_caps.u.HT_cap_element.AMPDU_para & 0x03;
++
++ if (pvhtpriv->ampdu_len > ht_AMPDU_len)
++ rtw_hal_set_hwreg(padapter, HW_VAR_AMPDU_FACTOR, (u8 *)(&pvhtpriv->ampdu_len));
++
++ rtw_hal_set_hwreg(padapter, HW_VAR_AMPDU_MAX_TIME, (u8 *)(&pvhtpriv->vht_highest_rate));
++}
++
++void rtw_vht_ies_attach(_adapter *padapter, WLAN_BSSID_EX *pnetwork)
++{
++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++ u8 cap_len, operation_len;
++ uint len = 0;
++ sint ie_len = 0;
++ u8 *p = NULL;
++
++ p = rtw_get_ie(pnetwork->IEs + _BEACON_IE_OFFSET_, EID_VHTCapability, &ie_len,
++ (pnetwork->IELength - _BEACON_IE_OFFSET_));
++ if (p && ie_len > 0)
++ return;
++
++ rtw_vht_use_default_setting(padapter);
++
++ /* VHT Operation mode notifiy bit in Extended IE (127) */
++ SET_EXT_CAPABILITY_ELE_OP_MODE_NOTIF(pmlmepriv->ext_capab_ie_data, 1);
++ pmlmepriv->ext_capab_ie_len = 10;
++ rtw_set_ie(pnetwork->IEs + pnetwork->IELength, EID_EXTCapability, 8, pmlmepriv->ext_capab_ie_data, &len);
++ pnetwork->IELength += pmlmepriv->ext_capab_ie_len;
++
++ /* VHT Capabilities element */
++ cap_len = rtw_build_vht_cap_ie(padapter, pnetwork->IEs + pnetwork->IELength);
++ pnetwork->IELength += cap_len;
++
++ /* VHT Operation element */
++ operation_len = rtw_build_vht_operation_ie(padapter, pnetwork->IEs + pnetwork->IELength,
++ pnetwork->Configuration.DSConfig);
++ pnetwork->IELength += operation_len;
++
++ rtw_check_for_vht20(padapter, pnetwork->IEs + _BEACON_IE_OFFSET_, pnetwork->IELength - _BEACON_IE_OFFSET_);
++
++ pmlmepriv->vhtpriv.vht_option = _TRUE;
++}
++
++void rtw_vht_ies_detach(_adapter *padapter, WLAN_BSSID_EX *pnetwork)
++{
++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
++
++ rtw_remove_bcn_ie(padapter, pnetwork, EID_EXTCapability);
++ rtw_remove_bcn_ie(padapter, pnetwork, EID_VHTCapability);
++ rtw_remove_bcn_ie(padapter, pnetwork, EID_VHTOperation);
++
++ pmlmepriv->vhtpriv.vht_option = _FALSE;
++}
++
++void rtw_check_for_vht20(_adapter *adapter, u8 *ies, int ies_len)
++{
++ u8 ht_ch, ht_bw, ht_offset;
++ u8 vht_ch, vht_bw, vht_offset;
++
++ rtw_ies_get_chbw(ies, ies_len, &ht_ch, &ht_bw, &ht_offset, 1, 0);
++ rtw_ies_get_chbw(ies, ies_len, &vht_ch, &vht_bw, &vht_offset, 1, 1);
++
++ if (ht_bw == CHANNEL_WIDTH_20 && vht_bw >= CHANNEL_WIDTH_80) {
++ u8 *vht_op_ie;
++ int vht_op_ielen;
++
++ RTW_INFO(FUNC_ADPT_FMT" vht80 is not allowed without ht40\n", FUNC_ADPT_ARG(adapter));
++ vht_op_ie = rtw_get_ie(ies, EID_VHTOperation, &vht_op_ielen, ies_len);
++ if (vht_op_ie && vht_op_ielen) {
++ RTW_INFO(FUNC_ADPT_FMT" switch to vht20\n", FUNC_ADPT_ARG(adapter));
++ SET_VHT_OPERATION_ELE_CHL_WIDTH(vht_op_ie + 2, 0);
++ SET_VHT_OPERATION_ELE_CHL_CENTER_FREQ1(vht_op_ie + 2, 0);
++ SET_VHT_OPERATION_ELE_CHL_CENTER_FREQ2(vht_op_ie + 2, 0);
++ }
++ }
++}
++#endif /* CONFIG_80211AC_VHT */
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/core/rtw_wlan_util.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/core/rtw_wlan_util.c
+--- linux-5.11.4/3rdparty/rtl8812au/core/rtw_wlan_util.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/core/rtw_wlan_util.c 2021-03-07 18:16:17.027954777 +0200
+@@ -0,0 +1,4972 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
@@ -110536,7 +107555,6 @@ index 000000000..b4cecd116
+ RTW_INFO("[%s] ch = %d, offset = %d, bwmode = %d\n", __func__, channel, channel_offset, bwmode);
+
+ center_ch = rtw_get_center_ch(channel, bwmode, channel_offset);
-+
+ if (bwmode == CHANNEL_WIDTH_80) {
+ if (center_ch > channel)
+ chnl_offset80 = HAL_PRIME_CHNL_OFFSET_LOWER;
@@ -114685,7 +111703,9 @@ index 000000000..b4cecd116
+
+ int i = 0;
+ struct file *fp;
++#ifdef set_fs
+ mm_segment_t fs;
++#endif
+ loff_t pos = 0;
+ u8 *source = NULL;
+ long len = 0;
@@ -114721,10 +111741,10 @@ index 000000000..b4cecd116
+ RTW_INFO("Error, cipher array using default value.\n");
+ return 0;
+ }
-+
++#ifdef set_fs
+ fs = get_fs();
+ set_fs(KERNEL_DS);
-+
++#endif
+ source = rtw_zmalloc(2048);
+
+ if (source != NULL) {
@@ -114732,10 +111752,10 @@ index 000000000..b4cecd116
+ rtw_parse_cipher_list(nlo_info, source);
+ rtw_mfree(source, 2048);
+ }
-+
++#ifdef set_fs
+ set_fs(fs);
++#endif
+ filp_close(fp, NULL);
-+
+ RTW_INFO("-%s-\n", __func__);
+ return 0;
+}
@@ -114910,12 +111930,10 @@ index 000000000..b4cecd116
+ /*TODO get offset of bcn's timestamp*/
+ /*pmlmeext->bcn_timestamp;*/
+}
-diff --git linux-5.8/3rdparty/rtl8812au/core/rtw_xmit.c linux-5.8/3rdparty/rtl8812au/core/rtw_xmit.c
-new file mode 100644
-index 000000000..90e215385
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/core/rtw_xmit.c
-@@ -0,0 +1,5900 @@
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/core/rtw_xmit.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/core/rtw_xmit.c
+--- linux-5.11.4/3rdparty/rtl8812au/core/rtw_xmit.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/core/rtw_xmit.c 2021-03-07 18:16:17.028954824 +0200
+@@ -0,0 +1,6097 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
@@ -119319,7 +116337,6 @@ index 000000000..90e215385
+s32 rtw_monitor_xmit_entry(struct sk_buff *skb, struct net_device *ndev)
+{
+ u16 frame_ctl;
-+ struct ieee80211_radiotap_header rtap_hdr;
+ _adapter *padapter = (_adapter *)rtw_netdev_priv(ndev);
+ struct pkt_file pktfile;
+ struct rtw_ieee80211_hdr *pwlanhdr;
@@ -119329,37 +116346,49 @@ index 000000000..90e215385
+ struct xmit_priv *pxmitpriv = &(padapter->xmitpriv);
+ struct registry_priv *pregpriv = &(padapter->registrypriv);
+ unsigned char *pframe;
-+ u8 dummybuf[32];
-+ int len = skb->len, rtap_len, consume;
++ int len = skb->len;
++
++ int rtap_len, rtap_remain, ret;
++ struct ieee80211_radiotap_header *rtap_hdr; // net/ieee80211_radiotap.h
++ struct ieee80211_radiotap_iterator iterator; // net/cfg80211.h
++ u8 rtap_buf[256];
+
+ int alloc_tries, alloc_delay;
+
+ rtw_mstat_update(MSTAT_TYPE_SKB, MSTAT_ALLOC_SUCCESS, skb->truesize);
+
-+#ifndef CONFIG_CUSTOMER_ALIBABA_GENERAL
+ if (unlikely(skb->len < sizeof(struct ieee80211_radiotap_header)))
+ goto fail;
+
+ _rtw_open_pktfile((_pkt *)skb, &pktfile);
-+ _rtw_pktfile_read(&pktfile, (u8 *)(&rtap_hdr), sizeof(struct ieee80211_radiotap_header));
-+ rtap_len = ieee80211_get_radiotap_len((u8 *)(&rtap_hdr));
-+ if (unlikely(rtap_hdr.it_version))
++ // Read in radiotap header and sanity check length
++ _rtw_pktfile_read(&pktfile, rtap_buf, sizeof(struct ieee80211_radiotap_header));
++ rtap_hdr = (struct ieee80211_radiotap_header*)(rtap_buf);
++ rtap_len = ieee80211_get_radiotap_len(rtap_buf);
++
++ if (unlikely(rtap_hdr->it_version))
+ goto fail;
+
+ if (unlikely(skb->len < rtap_len))
+ goto fail;
+
++ if (unlikely(rtap_len < sizeof(struct ieee80211_radiotap_header)))
++ goto fail;
++
+ len -= sizeof(struct ieee80211_radiotap_header);
-+ rtap_len -= sizeof(struct ieee80211_radiotap_header);
++ rtap_remain = rtap_len - sizeof(struct ieee80211_radiotap_header);
+
-+ while(rtap_len) {
-+ consume = rtap_len > sizeof(dummybuf) ? sizeof(dummybuf) : rtap_len;
-+ _rtw_pktfile_read(&pktfile, dummybuf, consume);
-+ rtap_len -= consume;
-+ len -= consume;
++ // Read in rest of radiotap body
++ if (rtap_remain) {
++ _rtw_pktfile_read(&pktfile, &rtap_buf[sizeof(struct ieee80211_radiotap_header)], rtap_remain);
++ len -= rtap_remain;
+ }
-+#endif
+
++ // NOTE: we process the radiotap header after we update the frame attribs below,
++ // so we can directly apply overrides rather than cache all the values into
++ // variables and apply them later.
++
++ // Process rest of frame
+ alloc_delay = 100;
+ for (alloc_tries=3; alloc_tries > 0; alloc_tries--) {
+ pmgntframe = alloc_mgtxmitframe(pxmitpriv);
@@ -119377,7 +116406,7 @@ index 000000000..90e215385
+ _rtw_pktfile_read(&pktfile, pframe, len);
+
+
-+ /* Check DATA/MGNT frames */
++ // Setup attribs for default Mgmt vs Data frame
+ pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
+ pattrib = &pmgntframe->attrib;
+ pattrib->injected = _TRUE;
@@ -119411,11 +116440,197 @@ index 000000000..90e215385
+ else
+ pattrib->retry_ctrl = _FALSE;
+ pattrib->pktlen = len;
-+ pmlmeext->mgnt_seq = GetSequence(pwlanhdr);
-+ pattrib->seqnum = pmlmeext->mgnt_seq;
-+ pmlmeext->mgnt_seq++;
++
+ pattrib->last_txcmdsz = pattrib->pktlen;
+
++ /*
++ ANALYSIS: most other xmit/frame generation flows:
++ - take next seqnum from pmlmeext->mgnt_seq
++ - call SetSeqNum to write it into the packet
++ - increment pmlmext->mgnt_seq
++ - and set it into pattrib->seqnum
++ Then in HAL, update_txdesc will either use hardware seq number if !pattrib_qos_en,
++ otherwise SET_TX_DESC_SEQ_8812 w/ pattrib->seqnum.
++ Also worth noting is prior update_monitor_frame_attrib/update_mgntframe_attrib call
++ merely set pattrib->seqnum to pmlmeext->mgnt_seq, but do NOT increment mgnt_seq.
++ Also they both set qos_en=_FALSE, which induce HW seq numbers.
++ The code below, however, appears to read the seq num out of the injected packet,
++ update the global pmlmeext->mgnt_seq with the injected seqnum, and then set
++ global pmlmeext to next seq. IMHO it appears to be doing the wrong thing, since
++ it is both updating pmlmeext from data in the packet, and all those values
++ are ignored because qos_en=_FALSE and thus HW seq is just used.
++ Ideally it would be nice to be able to control the sequence number, but the
++ strong coupling to qos_en makes that difficult right now. So we will just
++ use the default HW mode. However, we are going to skip some of the extraneous
++ steps this original code did by simply accepting:
++ - update_*_attrib called prior already set seqnum from pmlmeext
++ - so all we need to do is mgnt_seq++ just in case
++ - (and it seems we can avoid the SetSeqNum call)
++ pmlmeext->mgnt_seq = GetSequence(pwlanhdr);
++ pattrib->seqnum = pmlmeext->mgnt_seq;
++ pmlmeext->mgnt_seq++;
++ */
++ pmlmeext->mgnt_seq++;
++
++ pattrib->retry_ctrl = _FALSE;
++
++ // Parse radiotap for injection items and overwrite attribs as needed
++ ret = ieee80211_radiotap_iterator_init(&iterator, rtap_hdr, rtap_len, NULL);
++ while (!ret) {
++ ret = ieee80211_radiotap_iterator_next(&iterator);
++ if (ret)
++ continue;
++
++ switch (iterator.this_arg_index) {
++ case IEEE80211_RADIOTAP_RATE:
++ // This is basic 802.11b/g rate; use MCS/VHT for higher rates
++ pattrib->rate = *iterator.this_arg;
++#ifdef CONFIG_80211AC_VHT
++ pattrib->raid = RATEID_IDX_BGN_40M_1SS;
++#else
++ if (pattrib->rate == IEEE80211_CCK_RATE_1MB
++ || pattrib->rate == IEEE80211_CCK_RATE_2MB
++ || pattrib->rate == IEEE80211_CCK_RATE_5MB
++ || pattrib->rate == IEEE80211_CCK_RATE_11MB )
++ pattrib->raid = rtw_get_mgntframe_raid(padapter, WIRELESS_11B);
++ else
++ pattrib->raid = rtw_get_mgntframe_raid(padapter, WIRELESS_11G);
++#endif
++
++ // We have to reset other attributes that may have been set prior for MCS/VHT rates
++ pattrib->ht_en = _FALSE;
++ pattrib->ampdu_en = _FALSE;
++ pattrib->sgi = _FALSE;
++ pattrib->ldpc = _FALSE;
++ pattrib->stbc = 0;
++ pattrib->bwmode = CHANNEL_WIDTH_20;
++ pattrib->ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
++
++ break;
++
++ case IEEE80211_RADIOTAP_TX_FLAGS: {
++ u16 txflags = get_unaligned_le16(iterator.this_arg);
++
++ if ((txflags & IEEE80211_RADIOTAP_F_TX_NOACK) == 0)
++ pattrib->retry_ctrl = _TRUE; // Note; already _FALSE by default
++
++ if (txflags & 0x0010) { // Use preconfigured seq num
++ // NOTE: this is currently ignored due to qos_en=_FALSE and HW seq num override
++ pattrib->seqnum = GetSequence(pwlanhdr);
++ }
++
++ break;
++ }
++
++ case IEEE80211_RADIOTAP_MCS: {
++ u8 mcs_have = iterator.this_arg[0];
++
++ // Set up defaults
++ pattrib->rate = MGN_MCS0;
++ pattrib->bwmode = IEEE80211_RADIOTAP_MCS_BW_20;
++ pattrib->ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
++ pattrib->ht_en = _TRUE;
++ pattrib->sgi = _FALSE;
++ pattrib->ldpc = _FALSE;
++ pattrib->stbc = 0;
++
++ if (mcs_have & IEEE80211_RADIOTAP_MCS_HAVE_BW) {
++
++ u8 bw = (iterator.this_arg[1] & IEEE80211_RADIOTAP_MCS_BW_MASK);
++ if (bw == IEEE80211_RADIOTAP_MCS_BW_20L) {
++ bw = IEEE80211_RADIOTAP_MCS_BW_20;
++ pattrib->ch_offset = HAL_PRIME_CHNL_OFFSET_LOWER;
++ }
++ if (bw == IEEE80211_RADIOTAP_MCS_BW_20U) {
++ bw = IEEE80211_RADIOTAP_MCS_BW_20;
++ pattrib->ch_offset = HAL_PRIME_CHNL_OFFSET_UPPER;
++ }
++
++ pattrib->bwmode = bw;
++ }
++
++ if (mcs_have & IEEE80211_RADIOTAP_MCS_HAVE_MCS) {
++ u8 fixed_rate = iterator.this_arg[2] & 0x7f;
++ if(fixed_rate > 31)
++ fixed_rate = 0;
++ fixed_rate += MGN_MCS0;
++ pattrib->rate = fixed_rate;
++ }
++
++ if ((mcs_have & IEEE80211_RADIOTAP_MCS_HAVE_GI) && (iterator.this_arg[1] & IEEE80211_RADIOTAP_MCS_SGI))
++ pattrib->sgi = _TRUE;
++
++ if ((mcs_have & IEEE80211_RADIOTAP_MCS_HAVE_FEC) && (iterator.this_arg[1] & IEEE80211_RADIOTAP_MCS_FEC_LDPC))
++ pattrib->ldpc = _TRUE;
++
++ if (mcs_have & IEEE80211_RADIOTAP_MCS_HAVE_STBC) {
++ u8 stbc = (iterator.this_arg[1] & IEEE80211_RADIOTAP_MCS_STBC_MASK) >> IEEE80211_RADIOTAP_MCS_STBC_SHIFT;
++ pattrib->stbc = stbc;
++ }
++ }
++ break;
++
++#ifdef CONFIG_80211AC_VHT
++ case IEEE80211_RADIOTAP_VHT: {
++ unsigned int mcs, nss;
++
++ u8 known = iterator.this_arg[0];
++ u8 flags = iterator.this_arg[2];
++
++ // Set up defaults
++ pattrib->stbc = 0;
++ pattrib->sgi = _FALSE;
++ pattrib->bwmode = CHANNEL_WIDTH_20;
++ pattrib->ldpc = _FALSE;
++ pattrib->rate = MGN_VHT1SS_MCS0;
++ pattrib->raid = RATEID_IDX_VHT_1SS;
++
++ // NOTE: this code currently only supports 1SS for radiotap defined rates
++
++ if ((known & IEEE80211_RADIOTAP_VHT_KNOWN_STBC) && (flags & IEEE80211_RADIOTAP_VHT_FLAG_STBC))
++ pattrib->stbc = 1;
++
++ if ((known & IEEE80211_RADIOTAP_VHT_KNOWN_GI) && (flags & IEEE80211_RADIOTAP_VHT_FLAG_SGI))
++ pattrib->sgi = _TRUE;
++
++ if (known & IEEE80211_RADIOTAP_VHT_KNOWN_BANDWIDTH) {
++ u8 bw = iterator.this_arg[3] & 0x1F;
++ // NOTE: there are various L and U, but we just use straight 20/40/80
++ // since it's not clear how to set CHNL_OFFSET_LOWER/_UPPER with different
++ // sideband sizes/configurations. TODO.
++ // Also, any 160 is treated as 80 due to lack of WIDTH_160.
++ if (bw == 0)
++ pattrib->bwmode = CHANNEL_WIDTH_20;
++ else if (bw >=1 && bw <= 3)
++ pattrib->bwmode = CHANNEL_WIDTH_40;
++ else if (bw >=4 && bw <= 10)
++ pattrib->bwmode = CHANNEL_WIDTH_80;
++ else if (bw >= 11 && bw <= 25)
++ pattrib->bwmode = CHANNEL_WIDTH_80; // Supposed to be 160Mhz, we use 80Mhz
++ }
++
++ // User 0
++ nss = iterator.this_arg[4] & 0x0F; // Number of spatial streams
++ if (nss > 0) {
++ if (nss > 4) nss = 4;
++ mcs = (iterator.this_arg[4]>>4) & 0x0F; // MCS rate index
++ if (mcs > 8) mcs = 9;
++ pattrib->rate = MGN_VHT1SS_MCS0 + ((nss-1)*10 + mcs);
++
++ if (iterator.this_arg[8] & IEEE80211_RADIOTAP_CODING_LDPC_USER0)
++ pattrib->ldpc = _TRUE;
++ }
++
++ }
++ break;
++#endif
++
++ default:
++ break;
++ }
++ }
++
++ // All set
+ dump_mgntframe(padapter, pmgntframe);
+ pxmitpriv->tx_pkts++;
+ pxmitpriv->tx_bytes += skb->len;
@@ -120816,288 +118031,9 @@ index 000000000..90e215385
+ RTW_INFO("%s ack_tx not set\n", __func__);
+}
+#endif /* CONFIG_XMIT_ACK */
-diff --git linux-5.8/3rdparty/rtl8812au/dkms-install.sh linux-5.8/3rdparty/rtl8812au/dkms-install.sh
-new file mode 100755
-index 000000000..07c476b7d
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/dkms-install.sh
-@@ -0,0 +1,34 @@
-+#!/bin/bash
-+
-+if [[ $EUID -ne 0 ]]; then
-+ echo "You must run this with superuser priviliges. Try \"sudo ./dkms-install.sh\"" 2>&1
-+ exit 1
-+else
-+ echo "About to run dkms install steps..."
-+fi
-+
-+DRV_DIR="$(pwd)"
-+DRV_NAME=rtl8812au
-+DRV_VERSION=5.6.4.2
-+
-+cp -r $(pwd) /usr/src/${DRV_NAME}-${DRV_VERSION}
-+
-+dkms add -m ${DRV_NAME} -v ${DRV_VERSION}
-+dkms build -m ${DRV_NAME} -v ${DRV_VERSION}
-+dkms install -m ${DRV_NAME} -v ${DRV_VERSION}
-+RESULT=$?
-+
-+echo "Finished running dkms install steps."
-+
-+if grep -q -e "^CONFIG_DISABLE_IPV6 = y$" "$DRV_DIR/Makefile" ; then
-+ if echo "net.ipv6.conf.all.disable_ipv6 = 1
-+ net.ipv6.conf.default.disable_ipv6 = 1
-+ net.ipv6.conf.lo.disable_ipv6 = 1" >> /etc/sysctl.conf; then
-+ echo "Disabled IPv6 Successfuly "
-+ sysctl -p
-+ else
-+ echo "Could not disable IPv6"
-+ fi
-+fi
-+
-+exit $RESULT
-diff --git linux-5.8/3rdparty/rtl8812au/dkms-remove.sh linux-5.8/3rdparty/rtl8812au/dkms-remove.sh
-new file mode 100755
-index 000000000..6a8d6d604
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/dkms-remove.sh
-@@ -0,0 +1,24 @@
-+#!/bin/bash
-+
-+if [[ $EUID -ne 0 ]]; then
-+ echo "You must run this with superuser priviliges. Try \"sudo ./dkms-remove.sh\"" 2>&1
-+ exit 1
-+else
-+ echo "About to run dkms removal steps..."
-+fi
-+
-+DRV_DIR="$(pwd)"
-+DRV_NAME=rtl8812au
-+DRV_VERSION=5.6.4.2
-+
-+dkms remove ${DRV_NAME}/${DRV_VERSION} --all
-+rm -rf /usr/src/${DRV_NAME}-${DRV_VERSION}
-+
-+RESULT=$?
-+if [[ "$RESULT" != "0" ]]; then
-+ echo "Error occurred while running dkms remove." 2>&1
-+else
-+ echo "Finished running dkms removal steps."
-+fi
-+
-+exit $RESULT
-diff --git linux-5.8/3rdparty/rtl8812au/dkms.conf linux-5.8/3rdparty/rtl8812au/dkms.conf
-new file mode 100644
-index 000000000..4c3c3b7ec
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/dkms.conf
-@@ -0,0 +1,10 @@
-+PACKAGE_NAME="realtek-rtl88xxau"
-+PACKAGE_VERSION="5.6.4.2~20200816"
-+CLEAN="'make' clean"
-+BUILT_MODULE_NAME[0]=88XXau
-+PROCS_NUM=`nproc`
-+[ $PROCS_NUM -gt 16 ] && PROCS_NUM=16
-+DEST_MODULE_LOCATION[0]="/updates"
-+MAKE="'make' -j$PROCS_NUM KVER=${kernelver} KSRC=/lib/modules/${kernelver}/build"
-+AUTOINSTALL="yes"
-+REMAKE_INITRD=no
-diff --git linux-5.8/3rdparty/rtl8812au/hal/HalPwrSeqCmd.c linux-5.8/3rdparty/rtl8812au/hal/HalPwrSeqCmd.c
-new file mode 100644
-index 000000000..389785c2b
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/HalPwrSeqCmd.c
-@@ -0,0 +1,185 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+/*++
-+Copyright (c) Realtek Semiconductor Corp. All rights reserved.
-+
-+Module Name:
-+ HalPwrSeqCmd.c
-+
-+Abstract:
-+ Implement HW Power sequence configuration CMD handling routine for Realtek devices.
-+
-+Major Change History:
-+ When Who What
-+ ---------- --------------- -------------------------------
-+ 2011-10-26 Lucas Modify to be compatible with SD4-CE driver.
-+ 2011-07-07 Roger Create.
-+
-+--*/
-+#include
-+
-+
-+/*
-+ * Description:
-+ * This routine deal with the Power Configuration CMDs parsing for RTL8723/RTL8188E Series IC.
-+ *
-+ * Assumption:
-+ * We should follow specific format which was released from HW SD.
-+ *
-+ * 2011.07.07, added by Roger.
-+ * */
-+u8 HalPwrSeqCmdParsing(
-+ PADAPTER padapter,
-+ u8 CutVersion,
-+ u8 FabVersion,
-+ u8 InterfaceType,
-+ WLAN_PWR_CFG PwrSeqCmd[])
-+{
-+ WLAN_PWR_CFG PwrCfgCmd = {0};
-+ u8 bPollingBit = _FALSE;
-+ u8 bHWICSupport = _FALSE;
-+ u32 AryIdx = 0;
-+ u8 value = 0;
-+ u32 offset = 0;
-+ u8 flag = 0;
-+ u32 pollingCount = 0; /* polling autoload done. */
-+ u32 maxPollingCnt = 5000;
-+
-+ do {
-+ PwrCfgCmd = PwrSeqCmd[AryIdx];
-+
-+
-+ /* 2 Only Handle the command whose FAB, CUT, and Interface are matched */
-+ if ((GET_PWR_CFG_FAB_MASK(PwrCfgCmd) & FabVersion) &&
-+ (GET_PWR_CFG_CUT_MASK(PwrCfgCmd) & CutVersion) &&
-+ (GET_PWR_CFG_INTF_MASK(PwrCfgCmd) & InterfaceType)) {
-+ switch (GET_PWR_CFG_CMD(PwrCfgCmd)) {
-+ case PWR_CMD_READ:
-+ break;
-+
-+ case PWR_CMD_WRITE:
-+ offset = GET_PWR_CFG_OFFSET(PwrCfgCmd);
-+
-+#ifdef CONFIG_SDIO_HCI
-+ /* */
-+ /* We should deal with interface specific address mapping for some interfaces, e.g., SDIO interface */
-+ /* 2011.07.07. */
-+ /* */
-+ if (GET_PWR_CFG_BASE(PwrCfgCmd) == PWR_BASEADDR_SDIO) {
-+ /* Read Back SDIO Local value */
-+ value = SdioLocalCmd52Read1Byte(padapter, offset);
-+
-+ value &= ~(GET_PWR_CFG_MASK(PwrCfgCmd));
-+ value |= (GET_PWR_CFG_VALUE(PwrCfgCmd) & GET_PWR_CFG_MASK(PwrCfgCmd));
-+
-+ /* Write Back SDIO Local value */
-+ SdioLocalCmd52Write1Byte(padapter, offset, value);
-+ } else
-+#endif
-+ {
-+#ifdef CONFIG_GSPI_HCI
-+ if (GET_PWR_CFG_BASE(PwrCfgCmd) == PWR_BASEADDR_SDIO)
-+ offset = SPI_LOCAL_OFFSET | offset;
-+#endif
-+ /* Read the value from system register */
-+ value = rtw_read8(padapter, offset);
-+
-+ value = value & (~(GET_PWR_CFG_MASK(PwrCfgCmd)));
-+ value = value | (GET_PWR_CFG_VALUE(PwrCfgCmd) & GET_PWR_CFG_MASK(PwrCfgCmd));
-+
-+ /* Write the value back to sytem register */
-+ rtw_write8(padapter, offset, value);
-+ }
-+ break;
-+
-+ case PWR_CMD_POLLING:
-+
-+ bPollingBit = _FALSE;
-+ offset = GET_PWR_CFG_OFFSET(PwrCfgCmd);
-+
-+ rtw_hal_get_hwreg(padapter, HW_VAR_PWR_CMD, &bHWICSupport);
-+ if (bHWICSupport && offset == 0x06) {
-+ flag = 0;
-+ maxPollingCnt = 100000;
-+ } else
-+ maxPollingCnt = 5000;
-+
-+#ifdef CONFIG_GSPI_HCI
-+ if (GET_PWR_CFG_BASE(PwrCfgCmd) == PWR_BASEADDR_SDIO)
-+ offset = SPI_LOCAL_OFFSET | offset;
-+#endif
-+ do {
-+#ifdef CONFIG_SDIO_HCI
-+ if (GET_PWR_CFG_BASE(PwrCfgCmd) == PWR_BASEADDR_SDIO)
-+ value = SdioLocalCmd52Read1Byte(padapter, offset);
-+ else
-+#endif
-+ value = rtw_read8(padapter, offset);
-+
-+ value = value & GET_PWR_CFG_MASK(PwrCfgCmd);
-+ if (value == (GET_PWR_CFG_VALUE(PwrCfgCmd) & GET_PWR_CFG_MASK(PwrCfgCmd)))
-+ bPollingBit = _TRUE;
-+ else
-+ rtw_udelay_os(10);
-+
-+ if (pollingCount++ > maxPollingCnt) {
-+ RTW_ERR("HalPwrSeqCmdParsing: Fail to polling Offset[%#x]=%02x\n", offset, value);
-+
-+ /* For PCIE + USB package poll power bit timeout issue only modify 8821AE and 8723BE */
-+ if (bHWICSupport && offset == 0x06 && flag == 0) {
-+
-+ RTW_ERR("[WARNING] PCIE polling(0x%X) timeout(%d), Toggle 0x04[3] and try again.\n", offset, maxPollingCnt);
-+ if (IS_HARDWARE_TYPE_8723DE(padapter))
-+ PlatformEFIOWrite1Byte(padapter, 0x40, (PlatformEFIORead1Byte(padapter, 0x40)) & (~BIT3));
-+
-+ PlatformEFIOWrite1Byte(padapter, 0x04, PlatformEFIORead1Byte(padapter, 0x04) | BIT3);
-+ PlatformEFIOWrite1Byte(padapter, 0x04, PlatformEFIORead1Byte(padapter, 0x04) & ~BIT3);
-+
-+ if (IS_HARDWARE_TYPE_8723DE(padapter))
-+ PlatformEFIOWrite1Byte(padapter, 0x40, PlatformEFIORead1Byte(padapter, 0x40)|BIT3);
-+
-+ /* Retry Polling Process one more time */
-+ pollingCount = 0;
-+ flag = 1;
-+ } else {
-+ return _FALSE;
-+ }
-+ }
-+ } while (!bPollingBit);
-+
-+ break;
-+
-+ case PWR_CMD_DELAY:
-+ if (GET_PWR_CFG_VALUE(PwrCfgCmd) == PWRSEQ_DELAY_US)
-+ rtw_udelay_os(GET_PWR_CFG_OFFSET(PwrCfgCmd));
-+ else
-+ rtw_udelay_os(GET_PWR_CFG_OFFSET(PwrCfgCmd) * 1000);
-+ break;
-+
-+ case PWR_CMD_END:
-+ /* When this command is parsed, end the process */
-+ return _TRUE;
-+ break;
-+
-+ default:
-+ break;
-+ }
-+ }
-+
-+ AryIdx++;/* Add Array Index */
-+ } while (1);
-+
-+ return _TRUE;
-+}
-diff --git linux-5.8/3rdparty/rtl8812au/hal/efuse/efuse_mask.h linux-5.8/3rdparty/rtl8812au/hal/efuse/efuse_mask.h
-new file mode 100644
-index 000000000..f6059e4ec
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/efuse/efuse_mask.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/efuse/efuse_mask.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/efuse/efuse_mask.h
+--- linux-5.11.4/3rdparty/rtl8812au/hal/efuse/efuse_mask.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/efuse/efuse_mask.h 2021-03-07 18:16:17.049955817 +0200
@@ -0,0 +1,164 @@
+/******************************************************************************
+ *
@@ -121263,11 +118199,9 @@ index 000000000..f6059e4ec
+ #endif
+
+#endif /*CONFIG_SDIO_HCI*/
-diff --git linux-5.8/3rdparty/rtl8812au/hal/efuse/rtl8812a/HalEfuseMask8812A_PCIE.c linux-5.8/3rdparty/rtl8812au/hal/efuse/rtl8812a/HalEfuseMask8812A_PCIE.c
-new file mode 100644
-index 000000000..2b4d32648
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/efuse/rtl8812a/HalEfuseMask8812A_PCIE.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/efuse/rtl8812a/HalEfuseMask8812A_PCIE.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/efuse/rtl8812a/HalEfuseMask8812A_PCIE.c
+--- linux-5.11.4/3rdparty/rtl8812au/hal/efuse/rtl8812a/HalEfuseMask8812A_PCIE.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/efuse/rtl8812a/HalEfuseMask8812A_PCIE.c 2021-03-07 18:16:17.049955817 +0200
@@ -0,0 +1,94 @@
+/******************************************************************************
+ *
@@ -121363,11 +118297,9 @@ index 000000000..2b4d32648
+
+ return (result > 0) ? 0 : 1;
+}
-diff --git linux-5.8/3rdparty/rtl8812au/hal/efuse/rtl8812a/HalEfuseMask8812A_PCIE.h linux-5.8/3rdparty/rtl8812au/hal/efuse/rtl8812a/HalEfuseMask8812A_PCIE.h
-new file mode 100644
-index 000000000..085b2054c
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/efuse/rtl8812a/HalEfuseMask8812A_PCIE.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/efuse/rtl8812a/HalEfuseMask8812A_PCIE.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/efuse/rtl8812a/HalEfuseMask8812A_PCIE.h
+--- linux-5.11.4/3rdparty/rtl8812au/hal/efuse/rtl8812a/HalEfuseMask8812A_PCIE.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/efuse/rtl8812a/HalEfuseMask8812A_PCIE.h 2021-03-07 18:16:17.049955817 +0200
@@ -0,0 +1,33 @@
+/******************************************************************************
+ *
@@ -121402,11 +118334,9 @@ index 000000000..085b2054c
+EFUSE_IsAddressMasked_MP_8812A_MPCIE(/* TC: Test Chip, MP: MP Chip */
+ IN u2Byte Offset
+);
-diff --git linux-5.8/3rdparty/rtl8812au/hal/efuse/rtl8812a/HalEfuseMask8812A_USB.c linux-5.8/3rdparty/rtl8812au/hal/efuse/rtl8812a/HalEfuseMask8812A_USB.c
-new file mode 100644
-index 000000000..fd66e88e3
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/efuse/rtl8812a/HalEfuseMask8812A_USB.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/efuse/rtl8812a/HalEfuseMask8812A_USB.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/efuse/rtl8812a/HalEfuseMask8812A_USB.c
+--- linux-5.11.4/3rdparty/rtl8812au/hal/efuse/rtl8812a/HalEfuseMask8812A_USB.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/efuse/rtl8812a/HalEfuseMask8812A_USB.c 2021-03-07 18:16:17.049955817 +0200
@@ -0,0 +1,94 @@
+/******************************************************************************
+ *
@@ -121502,11 +118432,9 @@ index 000000000..fd66e88e3
+
+ return (result > 0) ? 0 : 1;
+}
-diff --git linux-5.8/3rdparty/rtl8812au/hal/efuse/rtl8812a/HalEfuseMask8812A_USB.h linux-5.8/3rdparty/rtl8812au/hal/efuse/rtl8812a/HalEfuseMask8812A_USB.h
-new file mode 100644
-index 000000000..1adfd8189
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/efuse/rtl8812a/HalEfuseMask8812A_USB.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/efuse/rtl8812a/HalEfuseMask8812A_USB.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/efuse/rtl8812a/HalEfuseMask8812A_USB.h
+--- linux-5.11.4/3rdparty/rtl8812au/hal/efuse/rtl8812a/HalEfuseMask8812A_USB.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/efuse/rtl8812a/HalEfuseMask8812A_USB.h 2021-03-07 18:16:17.049955817 +0200
@@ -0,0 +1,34 @@
+/******************************************************************************
+ *
@@ -121542,11 +118470,9 @@ index 000000000..1adfd8189
+EFUSE_IsAddressMasked_MP_8812A_MUSB(/* TC: Test Chip, MP: MP Chip */
+ IN u2Byte Offset
+);
-diff --git linux-5.8/3rdparty/rtl8812au/hal/efuse/rtl8812a/HalEfuseMask8821A_PCIE.c linux-5.8/3rdparty/rtl8812au/hal/efuse/rtl8812a/HalEfuseMask8821A_PCIE.c
-new file mode 100644
-index 000000000..608f35ec9
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/efuse/rtl8812a/HalEfuseMask8821A_PCIE.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/efuse/rtl8812a/HalEfuseMask8821A_PCIE.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/efuse/rtl8812a/HalEfuseMask8821A_PCIE.c
+--- linux-5.11.4/3rdparty/rtl8812au/hal/efuse/rtl8812a/HalEfuseMask8821A_PCIE.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/efuse/rtl8812a/HalEfuseMask8821A_PCIE.c 2021-03-07 18:16:17.049955817 +0200
@@ -0,0 +1,93 @@
+/******************************************************************************
+ *
@@ -121641,11 +118567,9 @@ index 000000000..608f35ec9
+
+ return (result > 0) ? 0 : 1;
+}
-diff --git linux-5.8/3rdparty/rtl8812au/hal/efuse/rtl8812a/HalEfuseMask8821A_PCIE.h linux-5.8/3rdparty/rtl8812au/hal/efuse/rtl8812a/HalEfuseMask8821A_PCIE.h
-new file mode 100644
-index 000000000..7e46d8e3c
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/efuse/rtl8812a/HalEfuseMask8821A_PCIE.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/efuse/rtl8812a/HalEfuseMask8821A_PCIE.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/efuse/rtl8812a/HalEfuseMask8821A_PCIE.h
+--- linux-5.11.4/3rdparty/rtl8812au/hal/efuse/rtl8812a/HalEfuseMask8821A_PCIE.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/efuse/rtl8812a/HalEfuseMask8821A_PCIE.h 2021-03-07 18:16:17.049955817 +0200
@@ -0,0 +1,33 @@
+/******************************************************************************
+ *
@@ -121680,11 +118604,9 @@ index 000000000..7e46d8e3c
+EFUSE_IsAddressMasked_MP_8821A_MPCIE(/* TC: Test Chip, MP: MP Chip */
+ IN u2Byte Offset
+);
-diff --git linux-5.8/3rdparty/rtl8812au/hal/efuse/rtl8812a/HalEfuseMask8821A_SDIO.c linux-5.8/3rdparty/rtl8812au/hal/efuse/rtl8812a/HalEfuseMask8821A_SDIO.c
-new file mode 100644
-index 000000000..bc9a28d18
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/efuse/rtl8812a/HalEfuseMask8821A_SDIO.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/efuse/rtl8812a/HalEfuseMask8821A_SDIO.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/efuse/rtl8812a/HalEfuseMask8821A_SDIO.c
+--- linux-5.11.4/3rdparty/rtl8812au/hal/efuse/rtl8812a/HalEfuseMask8821A_SDIO.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/efuse/rtl8812a/HalEfuseMask8821A_SDIO.c 2021-03-07 18:16:17.049955817 +0200
@@ -0,0 +1,96 @@
+/******************************************************************************
+ *
@@ -121782,11 +118704,9 @@ index 000000000..bc9a28d18
+
+ return (result > 0) ? 0 : 1;
+}
-diff --git linux-5.8/3rdparty/rtl8812au/hal/efuse/rtl8812a/HalEfuseMask8821A_SDIO.h linux-5.8/3rdparty/rtl8812au/hal/efuse/rtl8812a/HalEfuseMask8821A_SDIO.h
-new file mode 100644
-index 000000000..d82abe474
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/efuse/rtl8812a/HalEfuseMask8821A_SDIO.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/efuse/rtl8812a/HalEfuseMask8821A_SDIO.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/efuse/rtl8812a/HalEfuseMask8821A_SDIO.h
+--- linux-5.11.4/3rdparty/rtl8812au/hal/efuse/rtl8812a/HalEfuseMask8821A_SDIO.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/efuse/rtl8812a/HalEfuseMask8821A_SDIO.h 2021-03-07 18:16:17.049955817 +0200
@@ -0,0 +1,31 @@
+/******************************************************************************
+ *
@@ -121819,11 +118739,9 @@ index 000000000..d82abe474
+EFUSE_IsAddressMasked_MP_8821A_MSDIO(/* TC: Test Chip, MP: MP Chip */
+ IN u2Byte Offset
+);
-diff --git linux-5.8/3rdparty/rtl8812au/hal/efuse/rtl8812a/HalEfuseMask8821A_USB.c linux-5.8/3rdparty/rtl8812au/hal/efuse/rtl8812a/HalEfuseMask8821A_USB.c
-new file mode 100644
-index 000000000..36af57559
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/efuse/rtl8812a/HalEfuseMask8821A_USB.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/efuse/rtl8812a/HalEfuseMask8821A_USB.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/efuse/rtl8812a/HalEfuseMask8821A_USB.c
+--- linux-5.11.4/3rdparty/rtl8812au/hal/efuse/rtl8812a/HalEfuseMask8821A_USB.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/efuse/rtl8812a/HalEfuseMask8821A_USB.c 2021-03-07 18:16:17.049955817 +0200
@@ -0,0 +1,95 @@
+/******************************************************************************
+ *
@@ -121920,11 +118838,9 @@ index 000000000..36af57559
+
+ return (result > 0) ? 0 : 1;
+}
-diff --git linux-5.8/3rdparty/rtl8812au/hal/efuse/rtl8812a/HalEfuseMask8821A_USB.h linux-5.8/3rdparty/rtl8812au/hal/efuse/rtl8812a/HalEfuseMask8821A_USB.h
-new file mode 100644
-index 000000000..728f2d5a3
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/efuse/rtl8812a/HalEfuseMask8821A_USB.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/efuse/rtl8812a/HalEfuseMask8821A_USB.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/efuse/rtl8812a/HalEfuseMask8821A_USB.h
+--- linux-5.11.4/3rdparty/rtl8812au/hal/efuse/rtl8812a/HalEfuseMask8821A_USB.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/efuse/rtl8812a/HalEfuseMask8821A_USB.h 2021-03-07 18:16:17.049955817 +0200
@@ -0,0 +1,31 @@
+/******************************************************************************
+ *
@@ -121957,11 +118873,9 @@ index 000000000..728f2d5a3
+EFUSE_IsAddressMasked_MP_8821A_MUSB(/* TC: Test Chip, MP: MP Chip */
+ IN u2Byte Offset
+);
-diff --git linux-5.8/3rdparty/rtl8812au/hal/efuse/rtl8814a/HalEfuseMask8814A_PCIE.c linux-5.8/3rdparty/rtl8812au/hal/efuse/rtl8814a/HalEfuseMask8814A_PCIE.c
-new file mode 100644
-index 000000000..22f793cc3
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/efuse/rtl8814a/HalEfuseMask8814A_PCIE.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/efuse/rtl8814a/HalEfuseMask8814A_PCIE.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/efuse/rtl8814a/HalEfuseMask8814A_PCIE.c
+--- linux-5.11.4/3rdparty/rtl8812au/hal/efuse/rtl8814a/HalEfuseMask8814A_PCIE.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/efuse/rtl8814a/HalEfuseMask8814A_PCIE.c 2021-03-07 18:16:17.049955817 +0200
@@ -0,0 +1,93 @@
+/******************************************************************************
+*
@@ -122056,11 +118970,9 @@ index 000000000..22f793cc3
+ return (result > 0) ? 0 : 1;
+}
+
-diff --git linux-5.8/3rdparty/rtl8812au/hal/efuse/rtl8814a/HalEfuseMask8814A_PCIE.h linux-5.8/3rdparty/rtl8812au/hal/efuse/rtl8814a/HalEfuseMask8814A_PCIE.h
-new file mode 100644
-index 000000000..8b51c1b4a
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/efuse/rtl8814a/HalEfuseMask8814A_PCIE.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/efuse/rtl8814a/HalEfuseMask8814A_PCIE.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/efuse/rtl8814a/HalEfuseMask8814A_PCIE.h
+--- linux-5.11.4/3rdparty/rtl8812au/hal/efuse/rtl8814a/HalEfuseMask8814A_PCIE.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/efuse/rtl8814a/HalEfuseMask8814A_PCIE.h 2021-03-07 18:16:17.049955817 +0200
@@ -0,0 +1,33 @@
+/******************************************************************************
+*
@@ -122095,11 +119007,9 @@ index 000000000..8b51c1b4a
+BOOLEAN EFUSE_IsAddressMasked_MP_8814A_MPCIE(u2Byte Offset);
+
+
-diff --git linux-5.8/3rdparty/rtl8812au/hal/efuse/rtl8814a/HalEfuseMask8814A_USB.c linux-5.8/3rdparty/rtl8812au/hal/efuse/rtl8814a/HalEfuseMask8814A_USB.c
-new file mode 100644
-index 000000000..cd80e9294
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/efuse/rtl8814a/HalEfuseMask8814A_USB.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/efuse/rtl8814a/HalEfuseMask8814A_USB.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/efuse/rtl8814a/HalEfuseMask8814A_USB.c
+--- linux-5.11.4/3rdparty/rtl8812au/hal/efuse/rtl8814a/HalEfuseMask8814A_USB.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/efuse/rtl8814a/HalEfuseMask8814A_USB.c 2021-03-07 18:16:17.049955817 +0200
@@ -0,0 +1,90 @@
+/******************************************************************************
+*
@@ -122191,11 +119101,9 @@ index 000000000..cd80e9294
+ return (result > 0) ? 0 : 1;
+}
+
-diff --git linux-5.8/3rdparty/rtl8812au/hal/efuse/rtl8814a/HalEfuseMask8814A_USB.h linux-5.8/3rdparty/rtl8812au/hal/efuse/rtl8814a/HalEfuseMask8814A_USB.h
-new file mode 100644
-index 000000000..4262400d7
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/efuse/rtl8814a/HalEfuseMask8814A_USB.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/efuse/rtl8814a/HalEfuseMask8814A_USB.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/efuse/rtl8814a/HalEfuseMask8814A_USB.h
+--- linux-5.11.4/3rdparty/rtl8812au/hal/efuse/rtl8814a/HalEfuseMask8814A_USB.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/efuse/rtl8814a/HalEfuseMask8814A_USB.h 2021-03-07 18:16:17.049955817 +0200
@@ -0,0 +1,33 @@
+/******************************************************************************
+*
@@ -122230,11 +119138,9 @@ index 000000000..4262400d7
+
+BOOLEAN EFUSE_IsAddressMasked_MP_8814A_MUSB(u2Byte Offset);
+
-diff --git linux-5.8/3rdparty/rtl8812au/hal/hal_btcoex.c linux-5.8/3rdparty/rtl8812au/hal/hal_btcoex.c
-new file mode 100644
-index 000000000..bb0c3dc1a
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/hal_btcoex.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/hal_btcoex.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/hal_btcoex.c
+--- linux-5.11.4/3rdparty/rtl8812au/hal/hal_btcoex.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/hal_btcoex.c 2021-03-07 18:16:17.049955817 +0200
@@ -0,0 +1,5706 @@
+/******************************************************************************
+ *
@@ -127942,11 +124848,9 @@ index 000000000..bb0c3dc1a
+ EXhalbtcoutsrc_rx_rate_change_notify(&GLBtCoexist, is_data_frame, EXhalbtcoutsrc_rate_id_to_btc_rate_id(rate_id));
+}
+#endif /* CONFIG_BT_COEXIST */
-diff --git linux-5.8/3rdparty/rtl8812au/hal/hal_btcoex_wifionly.c linux-5.8/3rdparty/rtl8812au/hal/hal_btcoex_wifionly.c
-new file mode 100644
-index 000000000..0f82bbbb8
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/hal_btcoex_wifionly.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/hal_btcoex_wifionly.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/hal_btcoex_wifionly.c
+--- linux-5.11.4/3rdparty/rtl8812au/hal/hal_btcoex_wifionly.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/hal_btcoex_wifionly.c 2021-03-07 18:16:17.049955817 +0200
@@ -0,0 +1,224 @@
+/******************************************************************************
+ *
@@ -128172,11 +125076,9 @@ index 000000000..0f82bbbb8
+
+#endif
+
-diff --git linux-5.8/3rdparty/rtl8812au/hal/hal_com.c linux-5.8/3rdparty/rtl8812au/hal/hal_com.c
-new file mode 100644
-index 000000000..dcf8edf4a
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/hal_com.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/hal_com.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/hal_com.c
+--- linux-5.11.4/3rdparty/rtl8812au/hal/hal_com.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/hal_com.c 2021-03-07 18:16:17.051955911 +0200
@@ -0,0 +1,14640 @@
+/******************************************************************************
+ *
@@ -142818,11 +139720,9 @@ index 000000000..dcf8edf4a
+}
+#endif /*CONFIG_RTL8812A*/
+
-diff --git linux-5.8/3rdparty/rtl8812au/hal/hal_com_c2h.h linux-5.8/3rdparty/rtl8812au/hal/hal_com_c2h.h
-new file mode 100644
-index 000000000..1efabc9dc
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/hal_com_c2h.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/hal_com_c2h.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/hal_com_c2h.h
+--- linux-5.11.4/3rdparty/rtl8812au/hal/hal_com_c2h.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/hal_com_c2h.h 2021-03-07 18:16:17.051955911 +0200
@@ -0,0 +1,123 @@
+/******************************************************************************
+ *
@@ -142947,11 +139847,9 @@ index 000000000..1efabc9dc
+#endif
+
+#endif /* __COMMON_C2H_H__ */
-diff --git linux-5.8/3rdparty/rtl8812au/hal/hal_com_phycfg.c linux-5.8/3rdparty/rtl8812au/hal/hal_com_phycfg.c
-new file mode 100644
-index 000000000..ada38b221
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/hal_com_phycfg.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/hal_com_phycfg.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/hal_com_phycfg.c
+--- linux-5.11.4/3rdparty/rtl8812au/hal/hal_com_phycfg.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/hal_com_phycfg.c 2021-03-07 18:16:17.051955911 +0200
@@ -0,0 +1,5408 @@
+/******************************************************************************
+ *
@@ -148361,11 +145259,740 @@ index 000000000..ada38b221
+}
+
+#endif
-diff --git linux-5.8/3rdparty/rtl8812au/hal/hal_dm.c linux-5.8/3rdparty/rtl8812au/hal/hal_dm.c
-new file mode 100644
-index 000000000..c5fa43e30
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/hal_dm.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/hal_dm_acs.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/hal_dm_acs.c
+--- linux-5.11.4/3rdparty/rtl8812au/hal/hal_dm_acs.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/hal_dm_acs.c 2021-03-07 18:16:17.051955911 +0200
+@@ -0,0 +1,556 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2014 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#include
++#include
++
++
++#if defined(CONFIG_RTW_ACS) || defined(CONFIG_BACKGROUND_NOISE_MONITOR)
++static void _rtw_bss_nums_count(_adapter *adapter, u8 *pbss_nums)
++{
++ struct mlme_priv *pmlmepriv = &(adapter->mlmepriv);
++ _queue *queue = &(pmlmepriv->scanned_queue);
++ struct wlan_network *pnetwork = NULL;
++ HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
++
++ _list *plist, *phead;
++ _irqL irqL;
++ int chan_idx = -1;
++
++ if (pbss_nums == NULL) {
++ RTW_ERR("%s pbss_nums is null pointer\n", __func__);
++ return;
++ }
++ _rtw_memset(pbss_nums, 0, MAX_CHANNEL_NUM);
++
++ _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
++ phead = get_list_head(queue);
++ plist = get_next(phead);
++ while (1) {
++ if (rtw_end_of_queue_search(phead, plist) == _TRUE)
++ break;
++
++ pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list);
++ if (!pnetwork)
++ break;
++ chan_idx = rtw_chset_search_ch(adapter_to_chset(adapter), pnetwork->network.Configuration.DSConfig);
++ if ((chan_idx == -1) || (chan_idx >= MAX_CHANNEL_NUM)) {
++ RTW_ERR("%s can't get chan_idx(CH:%d)\n",
++ __func__, pnetwork->network.Configuration.DSConfig);
++ chan_idx = 0;
++ }
++ /*if (pnetwork->network.Reserved[0] != BSS_TYPE_PROB_REQ)*/
++
++ pbss_nums[chan_idx]++;
++
++ plist = get_next(plist);
++ }
++ _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
++}
++
++u8 rtw_get_ch_num_by_idx(_adapter *adapter, u8 idx)
++{
++ struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
++ RT_CHANNEL_INFO *pch_set = rfctl->channel_set;
++ u8 max_chan_nums = rfctl->max_chan_nums;
++
++ if (idx >= max_chan_nums)
++ return 0;
++ return pch_set[idx].ChannelNum;
++}
++#endif /*defined(CONFIG_RTW_ACS) || defined(CONFIG_BACKGROUND_NOISE_MONITOR)*/
++
++
++#ifdef CONFIG_RTW_ACS
++void rtw_acs_version_dump(void *sel, _adapter *adapter)
++{
++ _RTW_PRINT_SEL(sel, "RTK_ACS VER_%d\n", RTK_ACS_VERSION);
++}
++u8 rtw_phydm_clm_ratio(_adapter *adapter)
++{
++ struct dm_struct *phydm = adapter_to_phydm(adapter);
++
++ return phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_CLM_RATIO);
++}
++u8 rtw_phydm_nhm_ratio(_adapter *adapter)
++{
++ struct dm_struct *phydm = adapter_to_phydm(adapter);
++
++ return phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_NHM_RATIO);
++}
++void rtw_acs_reset(_adapter *adapter)
++{
++ HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
++ struct auto_chan_sel *pacs = &hal_data->acs;
++
++ _rtw_memset(pacs, 0, sizeof(struct auto_chan_sel));
++ #ifdef CONFIG_RTW_ACS_DBG
++ rtw_acs_adv_reset(adapter);
++ #endif /*CONFIG_RTW_ACS_DBG*/
++}
++
++#ifdef CONFIG_RTW_ACS_DBG
++u8 rtw_is_acs_igi_valid(_adapter *adapter)
++{
++ HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
++ struct auto_chan_sel *pacs = &hal_data->acs;
++
++ if ((pacs->igi) && ((pacs->igi >= 0x1E) || (pacs->igi < 0x60)))
++ return _TRUE;
++
++ return _FALSE;
++}
++void rtw_acs_adv_setting(_adapter *adapter, RT_SCAN_TYPE scan_type, u16 scan_time, u8 igi, u8 bw)
++{
++ HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
++ struct auto_chan_sel *pacs = &hal_data->acs;
++ struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv;
++ struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info;
++
++ pacs->scan_type = scan_type;
++ pacs->scan_time = scan_time;
++ pacs->igi = igi;
++ pacs->bw = bw;
++ RTW_INFO("[ACS] ADV setting - scan_type:%c, ch_ms:%d(ms), igi:0x%02x, bw:%d\n",
++ pacs->scan_type ? 'A' : 'P', pacs->scan_time, pacs->igi, pacs->bw);
++}
++void rtw_acs_adv_reset(_adapter *adapter)
++{
++ rtw_acs_adv_setting(adapter, SCAN_ACTIVE, 0, 0, 0);
++}
++#endif /*CONFIG_RTW_ACS_DBG*/
++
++void rtw_acs_trigger(_adapter *adapter, u16 scan_time_ms, u8 scan_chan, enum NHM_PID pid)
++{
++ HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
++ struct dm_struct *phydm = adapter_to_phydm(adapter);
++#if (RTK_ACS_VERSION == 3)
++ struct clm_para_info clm_para;
++ struct nhm_para_info nhm_para;
++ struct env_trig_rpt trig_rpt;
++
++ scan_time_ms -= 10;
++
++ init_acs_clm(clm_para, scan_time_ms);
++
++ if (pid == NHM_PID_IEEE_11K_HIGH)
++ init_11K_high_nhm(nhm_para, scan_time_ms);
++ else if (pid == NHM_PID_IEEE_11K_LOW)
++ init_11K_low_nhm(nhm_para, scan_time_ms);
++ else
++ init_acs_nhm(nhm_para, scan_time_ms);
++
++ hal_data->acs.trig_rst = phydm_env_mntr_trigger(phydm, &nhm_para, &clm_para, &trig_rpt);
++ if (hal_data->acs.trig_rst == (NHM_SUCCESS | CLM_SUCCESS)) {
++ hal_data->acs.trig_rpt.clm_rpt_stamp = trig_rpt.clm_rpt_stamp;
++ hal_data->acs.trig_rpt.nhm_rpt_stamp = trig_rpt.nhm_rpt_stamp;
++ /*RTW_INFO("[ACS] trigger success (rst = 0x%02x, clm_stamp:%d, nhm_stamp:%d)\n",
++ hal_data->acs.trig_rst, hal_data->acs.trig_rpt.clm_rpt_stamp, hal_data->acs.trig_rpt.nhm_rpt_stamp);*/
++ } else
++ RTW_ERR("[ACS] trigger failed (rst = 0x%02x)\n", hal_data->acs.trig_rst);
++#else
++ phydm_ccx_monitor_trigger(phydm, scan_time_ms);
++#endif
++
++ hal_data->acs.trigger_ch = scan_chan;
++ hal_data->acs.triggered = _TRUE;
++
++ #ifdef CONFIG_RTW_ACS_DBG
++ RTW_INFO("[ACS] Trigger CH:%d, Times:%d\n", hal_data->acs.trigger_ch, scan_time_ms);
++ #endif
++}
++void rtw_acs_get_rst(_adapter *adapter)
++{
++ HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
++ struct dm_struct *phydm = adapter_to_phydm(adapter);
++ int chan_idx = -1;
++ u8 cur_chan = hal_data->acs.trigger_ch;
++
++ if (cur_chan == 0)
++ return;
++
++ if (!hal_data->acs.triggered)
++ return;
++
++ chan_idx = rtw_chset_search_ch(adapter_to_chset(adapter), cur_chan);
++ if ((chan_idx == -1) || (chan_idx >= MAX_CHANNEL_NUM)) {
++ RTW_ERR("[ACS] %s can't get chan_idx(CH:%d)\n", __func__, cur_chan);
++ return;
++ }
++#if (RTK_ACS_VERSION == 3)
++ if (!(hal_data->acs.trig_rst == (NHM_SUCCESS | CLM_SUCCESS))) {
++ RTW_ERR("[ACS] get_rst return, due to acs trigger failed\n");
++ return;
++ }
++
++ {
++ struct env_mntr_rpt rpt = {0};
++ u8 rst;
++
++ rst = phydm_env_mntr_result(phydm, &rpt);
++ if ((rst == (NHM_SUCCESS | CLM_SUCCESS)) &&
++ (rpt.clm_rpt_stamp == hal_data->acs.trig_rpt.clm_rpt_stamp) &&
++ (rpt.nhm_rpt_stamp == hal_data->acs.trig_rpt.nhm_rpt_stamp)){
++ hal_data->acs.clm_ratio[chan_idx] = rpt.clm_ratio;
++ hal_data->acs.nhm_ratio[chan_idx] = rpt.nhm_ratio;
++ _rtw_memcpy(&hal_data->acs.nhm[chan_idx][0], rpt.nhm_result, NHM_RPT_NUM);
++
++ /*RTW_INFO("[ACS] get_rst success (rst = 0x%02x, clm_stamp:%d:%d, nhm_stamp:%d:%d)\n",
++ rst,
++ hal_data->acs.trig_rpt.clm_rpt_stamp, rpt.clm_rpt_stamp,
++ hal_data->acs.trig_rpt.nhm_rpt_stamp, rpt.nhm_rpt_stamp);*/
++ } else {
++ RTW_ERR("[ACS] get_rst failed (rst = 0x%02x, clm_stamp:%d:%d, nhm_stamp:%d:%d)\n",
++ rst,
++ hal_data->acs.trig_rpt.clm_rpt_stamp, rpt.clm_rpt_stamp,
++ hal_data->acs.trig_rpt.nhm_rpt_stamp, rpt.nhm_rpt_stamp);
++ }
++ }
++
++#else
++ phydm_ccx_monitor_result(phydm);
++
++ hal_data->acs.clm_ratio[chan_idx] = rtw_phydm_clm_ratio(adapter);
++ hal_data->acs.nhm_ratio[chan_idx] = rtw_phydm_nhm_ratio(adapter);
++#endif
++ hal_data->acs.triggered = _FALSE;
++ #ifdef CONFIG_RTW_ACS_DBG
++ RTW_INFO("[ACS] Result CH:%d, CLM:%d NHM:%d\n",
++ cur_chan, hal_data->acs.clm_ratio[chan_idx], hal_data->acs.nhm_ratio[chan_idx]);
++ #endif
++}
++
++void _rtw_phydm_acs_select_best_chan(_adapter *adapter)
++{
++ HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
++ struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
++ u8 ch_idx;
++ u8 ch_idx_24g = 0xFF, ch_idx_5g = 0xFF;
++ u8 min_itf_24g = 0xFF, min_itf_5g = 0xFF;
++ u8 *pbss_nums = hal_data->acs.bss_nums;
++ u8 *pclm_ratio = hal_data->acs.clm_ratio;
++ u8 *pnhm_ratio = hal_data->acs.nhm_ratio;
++ u8 *pinterference_time = hal_data->acs.interference_time;
++ u8 max_chan_nums = rfctl->max_chan_nums;
++
++ for (ch_idx = 0; ch_idx < max_chan_nums; ch_idx++) {
++ if (pbss_nums[ch_idx])
++ pinterference_time[ch_idx] = (pclm_ratio[ch_idx] / 2) + pnhm_ratio[ch_idx];
++ else
++ pinterference_time[ch_idx] = pclm_ratio[ch_idx] + pnhm_ratio[ch_idx];
++
++ if (rtw_get_ch_num_by_idx(adapter, ch_idx) < 14) {
++ if (pinterference_time[ch_idx] < min_itf_24g) {
++ min_itf_24g = pinterference_time[ch_idx];
++ ch_idx_24g = ch_idx;
++ }
++ } else {
++ if (pinterference_time[ch_idx] < min_itf_5g) {
++ min_itf_5g = pinterference_time[ch_idx];
++ ch_idx_5g = ch_idx;
++ }
++ }
++ }
++ if (ch_idx_24g != 0xFF)
++ hal_data->acs.best_chan_24g = rtw_get_ch_num_by_idx(adapter, ch_idx_24g);
++
++ if (ch_idx_5g != 0xFF)
++ hal_data->acs.best_chan_5g = rtw_get_ch_num_by_idx(adapter, ch_idx_5g);
++
++ hal_data->acs.trigger_ch = 0;
++}
++
++void rtw_acs_info_dump(void *sel, _adapter *adapter)
++{
++ HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
++ struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
++ u8 max_chan_nums = rfctl->max_chan_nums;
++ u8 ch_idx, ch_num;
++
++ _RTW_PRINT_SEL(sel, "========== ACS (VER-%d) ==========\n", RTK_ACS_VERSION);
++ _RTW_PRINT_SEL(sel, "Best 24G Channel:%d\n", hal_data->acs.best_chan_24g);
++ _RTW_PRINT_SEL(sel, "Best 5G Channel:%d\n\n", hal_data->acs.best_chan_5g);
++
++ #ifdef CONFIG_RTW_ACS_DBG
++ _RTW_PRINT_SEL(sel, "Advanced setting - scan_type:%c, ch_ms:%d(ms), igi:0x%02x, bw:%d\n",
++ hal_data->acs.scan_type ? 'A' : 'P', hal_data->acs.scan_time, hal_data->acs.igi, hal_data->acs.bw);
++
++ _RTW_PRINT_SEL(sel, "BW 20MHz\n");
++ _RTW_PRINT_SEL(sel, "%5s %3s %3s %3s(%%) %3s(%%) %3s\n",
++ "Index", "CH", "BSS", "CLM", "NHM", "ITF");
++
++ for (ch_idx = 0; ch_idx < max_chan_nums; ch_idx++) {
++ ch_num = rtw_get_ch_num_by_idx(adapter, ch_idx);
++ _RTW_PRINT_SEL(sel, "%5d %3d %3d %6d %6d %3d\n",
++ ch_idx, ch_num, hal_data->acs.bss_nums[ch_idx],
++ hal_data->acs.clm_ratio[ch_idx],
++ hal_data->acs.nhm_ratio[ch_idx],
++ hal_data->acs.interference_time[ch_idx]);
++ }
++ #endif
++}
++void rtw_acs_select_best_chan(_adapter *adapter)
++{
++ HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
++
++ _rtw_bss_nums_count(adapter, hal_data->acs.bss_nums);
++ _rtw_phydm_acs_select_best_chan(adapter);
++ rtw_acs_info_dump(RTW_DBGDUMP, adapter);
++}
++
++void rtw_acs_start(_adapter *adapter)
++{
++ rtw_acs_reset(adapter);
++ if (GET_ACS_STATE(adapter) != ACS_ENABLE)
++ SET_ACS_STATE(adapter, ACS_ENABLE);
++}
++void rtw_acs_stop(_adapter *adapter)
++{
++ SET_ACS_STATE(adapter, ACS_DISABLE);
++}
++
++
++u8 rtw_acs_get_clm_ratio_by_ch_num(_adapter *adapter, u8 chan)
++{
++ HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
++ int chan_idx = -1;
++
++ chan_idx = rtw_chset_search_ch(adapter_to_chset(adapter), chan);
++ if ((chan_idx == -1) || (chan_idx >= MAX_CHANNEL_NUM)) {
++ RTW_ERR("[ACS] Get CLM fail, can't get chan_idx(CH:%d)\n", chan);
++ return 0;
++ }
++
++ return hal_data->acs.clm_ratio[chan_idx];
++}
++u8 rtw_acs_get_clm_ratio_by_ch_idx(_adapter *adapter, u8 ch_idx)
++{
++ HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
++
++ if (ch_idx >= MAX_CHANNEL_NUM) {
++ RTW_ERR("%s [ACS] ch_idx(%d) is invalid\n", __func__, ch_idx);
++ return 0;
++ }
++
++ return hal_data->acs.clm_ratio[ch_idx];
++}
++u8 rtw_acs_get_nhm_ratio_by_ch_num(_adapter *adapter, u8 chan)
++{
++ HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
++ int chan_idx = -1;
++
++ chan_idx = rtw_chset_search_ch(adapter_to_chset(adapter), chan);
++ if ((chan_idx == -1) || (chan_idx >= MAX_CHANNEL_NUM)) {
++ RTW_ERR("[ACS] Get NHM fail, can't get chan_idx(CH:%d)\n", chan);
++ return 0;
++ }
++
++ return hal_data->acs.nhm_ratio[chan_idx];
++}
++u8 rtw_acs_get_num_ratio_by_ch_idx(_adapter *adapter, u8 ch_idx)
++{
++ HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
++
++ if (ch_idx >= MAX_CHANNEL_NUM) {
++ RTW_ERR("%s [ACS] ch_idx(%d) is invalid\n", __func__, ch_idx);
++ return 0;
++ }
++
++ return hal_data->acs.nhm_ratio[ch_idx];
++}
++void rtw_acs_chan_info_dump(void *sel, _adapter *adapter)
++{
++ HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
++ struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
++ u8 max_chan_nums = rfctl->max_chan_nums;
++ u8 ch_idx, ch_num;
++ u8 utilization;
++
++ _RTW_PRINT_SEL(sel, "BW 20MHz\n");
++ _RTW_PRINT_SEL(sel, "%5s %3s %7s(%%) %12s(%%) %11s(%%) %9s(%%) %8s(%%)\n",
++ "Index", "CH", "Quality", "Availability", "Utilization",
++ "WIFI Util", "Interference Util");
++
++ for (ch_idx = 0; ch_idx < max_chan_nums; ch_idx++) {
++ ch_num = rtw_get_ch_num_by_idx(adapter, ch_idx);
++ utilization = hal_data->acs.clm_ratio[ch_idx] + hal_data->acs.nhm_ratio[ch_idx];
++ _RTW_PRINT_SEL(sel, "%5d %3d %7d %12d %12d %12d %12d\n",
++ ch_idx, ch_num,
++ (100-hal_data->acs.interference_time[ch_idx]),
++ (100-utilization),
++ utilization,
++ hal_data->acs.clm_ratio[ch_idx],
++ hal_data->acs.nhm_ratio[ch_idx]);
++ }
++}
++void rtw_acs_current_info_dump(void *sel, _adapter *adapter)
++{
++ HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
++ u8 ch, cen_ch, bw, offset;
++
++ _RTW_PRINT_SEL(sel, "========== ACS (VER-%d) ==========\n", RTK_ACS_VERSION);
++
++ ch = rtw_get_oper_ch(adapter);
++ bw = rtw_get_oper_bw(adapter);
++ offset = rtw_get_oper_choffset(adapter);
++
++ _RTW_PRINT_SEL(sel, "Current Channel:%d\n", ch);
++ if ((bw == CHANNEL_WIDTH_80) ||(bw == CHANNEL_WIDTH_40)) {
++ cen_ch = rtw_get_center_ch(ch, bw, offset);
++ _RTW_PRINT_SEL(sel, "Center Channel:%d\n", cen_ch);
++ }
++
++ _RTW_PRINT_SEL(sel, "Current BW %s\n", ch_width_str(bw));
++ if (0)
++ _RTW_PRINT_SEL(sel, "Current IGI 0x%02x\n", rtw_phydm_get_cur_igi(adapter));
++ _RTW_PRINT_SEL(sel, "CLM:%d, NHM:%d\n\n",
++ hal_data->acs.cur_ch_clm_ratio, hal_data->acs.cur_ch_nhm_ratio);
++}
++
++void rtw_acs_update_current_info(_adapter *adapter)
++{
++ HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
++
++ hal_data->acs.cur_ch_clm_ratio = rtw_phydm_clm_ratio(adapter);
++ hal_data->acs.cur_ch_nhm_ratio = rtw_phydm_nhm_ratio(adapter);
++
++ #ifdef CONFIG_RTW_ACS_DBG
++ rtw_acs_current_info_dump(RTW_DBGDUMP, adapter);
++ #endif
++}
++#endif /*CONFIG_RTW_ACS*/
++
++#ifdef CONFIG_BACKGROUND_NOISE_MONITOR
++void rtw_noise_monitor_version_dump(void *sel, _adapter *adapter)
++{
++ _RTW_PRINT_SEL(sel, "RTK_NOISE_MONITOR VER_%d\n", RTK_NOISE_MONITOR_VERSION);
++}
++void rtw_nm_enable(_adapter *adapter)
++{
++ SET_NM_STATE(adapter, NM_ENABLE);
++}
++void rtw_nm_disable(_adapter *adapter)
++{
++ SET_NM_STATE(adapter, NM_DISABLE);
++}
++void rtw_noise_info_dump(void *sel, _adapter *adapter)
++{
++ HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
++ struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
++ u8 max_chan_nums = rfctl->max_chan_nums;
++ u8 ch_idx, ch_num;
++
++ _RTW_PRINT_SEL(sel, "========== NM (VER-%d) ==========\n", RTK_NOISE_MONITOR_VERSION);
++
++ _RTW_PRINT_SEL(sel, "%5s %3s %3s %10s", "Index", "CH", "BSS", "Noise(dBm)\n");
++
++ _rtw_bss_nums_count(adapter, hal_data->nm.bss_nums);
++
++ for (ch_idx = 0; ch_idx < max_chan_nums; ch_idx++) {
++ ch_num = rtw_get_ch_num_by_idx(adapter, ch_idx);
++ _RTW_PRINT_SEL(sel, "%5d %3d %3d %10d\n",
++ ch_idx, ch_num, hal_data->nm.bss_nums[ch_idx],
++ hal_data->nm.noise[ch_idx]);
++ }
++}
++
++void rtw_noise_measure(_adapter *adapter, u8 chan, u8 is_pause_dig, u8 igi_value, u32 max_time)
++{
++ HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
++ struct dm_struct *phydm = &hal_data->odmpriv;
++ int chan_idx = -1;
++ s16 noise = 0;
++
++ #ifdef DBG_NOISE_MONITOR
++ RTW_INFO("[NM] chan(%d)-PauseDIG:%s, IGIValue:0x%02x, max_time:%d (ms)\n",
++ chan, (is_pause_dig) ? "Y" : "N", igi_value, max_time);
++ #endif
++
++ chan_idx = rtw_chset_search_ch(adapter_to_chset(adapter), chan);
++ if ((chan_idx == -1) || (chan_idx >= MAX_CHANNEL_NUM)) {
++ RTW_ERR("[NM] Get noise fail, can't get chan_idx(CH:%d)\n", chan);
++ return;
++ }
++ noise = odm_inband_noise_monitor(phydm, is_pause_dig, igi_value, max_time); /*dBm*/
++
++ hal_data->nm.noise[chan_idx] = noise;
++
++ #ifdef DBG_NOISE_MONITOR
++ RTW_INFO("[NM] %s chan_%d, noise = %d (dBm)\n", __func__, chan, hal_data->nm.noise[chan_idx]);
++
++ RTW_INFO("[NM] noise_a = %d, noise_b = %d noise_all:%d\n",
++ phydm->noise_level.noise[RF_PATH_A],
++ phydm->noise_level.noise[RF_PATH_B],
++ phydm->noise_level.noise_all);
++ #endif /*DBG_NOISE_MONITOR*/
++}
++
++s16 rtw_noise_query_by_chan_num(_adapter *adapter, u8 chan)
++{
++ HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
++ s16 noise = 0;
++ int chan_idx = -1;
++
++ chan_idx = rtw_chset_search_ch(adapter_to_chset(adapter), chan);
++ if ((chan_idx == -1) || (chan_idx >= MAX_CHANNEL_NUM)) {
++ RTW_ERR("[NM] Get noise fail, can't get chan_idx(CH:%d)\n", chan);
++ return noise;
++ }
++ noise = hal_data->nm.noise[chan_idx];
++
++ #ifdef DBG_NOISE_MONITOR
++ RTW_INFO("[NM] %s chan_%d, noise = %d (dBm)\n", __func__, chan, noise);
++ #endif/*DBG_NOISE_MONITOR*/
++ return noise;
++}
++s16 rtw_noise_query_by_chan_idx(_adapter *adapter, u8 ch_idx)
++{
++ HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
++ s16 noise = 0;
++
++ if (ch_idx >= MAX_CHANNEL_NUM) {
++ RTW_ERR("[NM] %s ch_idx(%d) is invalid\n", __func__, ch_idx);
++ return noise;
++ }
++ noise = hal_data->nm.noise[ch_idx];
++
++ #ifdef DBG_NOISE_MONITOR
++ RTW_INFO("[NM] %s ch_idx %d, noise = %d (dBm)\n", __func__, ch_idx, noise);
++ #endif/*DBG_NOISE_MONITOR*/
++ return noise;
++}
++
++s16 rtw_noise_measure_curchan(_adapter *padapter)
++{
++ s16 noise = 0;
++ u8 igi_value = 0x1E;
++ u32 max_time = 100;/* ms */
++ u8 is_pause_dig = _TRUE;
++ u8 cur_chan = rtw_get_oper_ch(padapter);
++
++#ifndef CONFIG_ALLOW_UNLINKED_NOISE_MONITOR
++ if (rtw_linked_check(padapter) == _FALSE)
++ return noise;
++#endif
++
++ rtw_ps_deny(padapter, PS_DENY_IOCTL);
++ LeaveAllPowerSaveModeDirect(padapter);
++ rtw_noise_measure(padapter, cur_chan, is_pause_dig, igi_value, max_time);
++ noise = rtw_noise_query_by_chan_num(padapter, cur_chan);
++ rtw_ps_deny_cancel(padapter, PS_DENY_IOCTL);
++
++ return noise;
++}
++#endif /*CONFIG_BACKGROUND_NOISE_MONITOR*/
++
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/hal_dm_acs.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/hal_dm_acs.h
+--- linux-5.11.4/3rdparty/rtl8812au/hal/hal_dm_acs.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/hal_dm_acs.h 2021-03-07 18:16:17.051955911 +0200
+@@ -0,0 +1,167 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __HAL_DM_ACS_H__
++#define __HAL_DM_ACS_H__
++#ifdef CONFIG_RTW_ACS
++#define RTK_ACS_VERSION 3
++
++#if (RTK_ACS_VERSION == 3)
++enum NHM_PID {
++ NHM_PID_ACS,
++ NHM_PID_IEEE_11K_HIGH,
++ NHM_PID_IEEE_11K_LOW,
++};
++
++#define init_clm_param(clm, app, lv, time) \
++ do {\
++ clm.clm_app = app;\
++ clm.clm_lv = lv;\
++ clm.mntr_time = time;\
++ } while (0)
++
++#define init_nhm_param(nhm, txon, cca, cnt_opt, app, lv, time) \
++ do {\
++ nhm.incld_txon = txon;\
++ nhm.incld_cca = cca;\
++ nhm.div_opt = cnt_opt;\
++ nhm.nhm_app = app;\
++ nhm.nhm_lv = lv;\
++ nhm.mntr_time = time;\
++ } while (0)
++
++
++#define init_acs_clm(clm, time) \
++ init_clm_param(clm, CLM_ACS, CLM_LV_2, time)
++
++#define init_acs_nhm(nhm, time) \
++ init_nhm_param(nhm, NHM_EXCLUDE_TXON, NHM_EXCLUDE_CCA, NHM_CNT_ALL, NHM_ACS, NHM_LV_2, time)
++
++#define init_11K_high_nhm(nhm, time) \
++ init_nhm_param(nhm, NHM_EXCLUDE_TXON, NHM_EXCLUDE_CCA, NHM_CNT_ALL, IEEE_11K_HIGH, NHM_LV_2, time)
++
++#define init_11K_low_nhm(nhm, time) \
++ init_nhm_param(nhm, NHM_EXCLUDE_TXON, NHM_EXCLUDE_CCA, NHM_CNT_ALL, IEEE_11K_LOW, NHM_LV_2, time)
++
++
++#endif /*(RTK_ACS_VERSION == 3)*/
++void rtw_acs_version_dump(void *sel, _adapter *adapter);
++extern void phydm_ccx_monitor_trigger(void *p_dm_void, u16 monitor_time);
++extern void phydm_ccx_monitor_result(void *p_dm_void);
++
++#define GET_ACS_STATE(padapter) (ATOMIC_READ(&GET_HAL_DATA(padapter)->acs.state))
++#define SET_ACS_STATE(padapter, set_state) (ATOMIC_SET(&GET_HAL_DATA(padapter)->acs.state, set_state))
++#define IS_ACS_ENABLE(padapter) ((GET_ACS_STATE(padapter) == ACS_ENABLE) ? _TRUE : _FALSE)
++
++enum ACS_STATE {
++ ACS_DISABLE,
++ ACS_ENABLE,
++};
++
++#define ACS_BW_20M BIT(0)
++#define ACS_BW_40M BIT(1)
++#define ACS_BW_80M BIT(2)
++#define ACS_BW_160M BIT(3)
++
++struct auto_chan_sel {
++ ATOMIC_T state;
++ u8 trigger_ch;
++ bool triggered;
++ u8 clm_ratio[MAX_CHANNEL_NUM];
++ u8 nhm_ratio[MAX_CHANNEL_NUM];
++ #if (RTK_ACS_VERSION == 3)
++ u8 nhm[MAX_CHANNEL_NUM][NHM_RPT_NUM];
++ #endif
++ u8 bss_nums[MAX_CHANNEL_NUM];
++ u8 interference_time[MAX_CHANNEL_NUM];
++ u8 cur_ch_clm_ratio;
++ u8 cur_ch_nhm_ratio;
++ u8 best_chan_5g;
++ u8 best_chan_24g;
++
++ #if (RTK_ACS_VERSION == 3)
++ u8 trig_rst;
++ struct env_trig_rpt trig_rpt;
++ #endif
++
++ #ifdef CONFIG_RTW_ACS_DBG
++ RT_SCAN_TYPE scan_type;
++ u16 scan_time;
++ u8 igi;
++ u8 bw;
++ #endif
++};
++
++#define rtw_acs_get_best_chan_24g(adapter) (GET_HAL_DATA(adapter)->acs.best_chan_24g)
++#define rtw_acs_get_best_chan_5g(adapter) (GET_HAL_DATA(adapter)->acs.best_chan_5g)
++
++#ifdef CONFIG_RTW_ACS_DBG
++#define rtw_is_acs_passiv_scan(adapter) (((GET_HAL_DATA(adapter)->acs.scan_type) == SCAN_PASSIVE) ? _TRUE : _FALSE)
++
++#define rtw_acs_get_adv_st(adapter) (GET_HAL_DATA(adapter)->acs.scan_time)
++#define rtw_is_acs_st_valid(adapter) ((GET_HAL_DATA(adapter)->acs.scan_time) ? _TRUE : _FALSE)
++
++#define rtw_acs_get_adv_igi(adapter) (GET_HAL_DATA(adapter)->acs.igi)
++u8 rtw_is_acs_igi_valid(_adapter *adapter);
++
++#define rtw_acs_get_adv_bw(adapter) (GET_HAL_DATA(adapter)->acs.bw)
++
++void rtw_acs_adv_setting(_adapter *adapter, RT_SCAN_TYPE scan_type, u16 scan_time, u8 igi, u8 bw);
++void rtw_acs_adv_reset(_adapter *adapter);
++#endif
++
++u8 rtw_acs_get_clm_ratio_by_ch_num(_adapter *adapter, u8 chan);
++u8 rtw_acs_get_clm_ratio_by_ch_idx(_adapter *adapter, u8 ch_idx);
++u8 rtw_acs_get_nhm_ratio_by_ch_num(_adapter *adapter, u8 chan);
++u8 rtw_acs_get_num_ratio_by_ch_idx(_adapter *adapter, u8 ch_idx);
++
++void rtw_acs_reset(_adapter *adapter);
++void rtw_acs_trigger(_adapter *adapter, u16 scan_time_ms, u8 scan_chan, enum NHM_PID pid);
++void rtw_acs_get_rst(_adapter *adapter);
++void rtw_acs_select_best_chan(_adapter *adapter);
++void rtw_acs_info_dump(void *sel, _adapter *adapter);
++void rtw_acs_update_current_info(_adapter *adapter);
++void rtw_acs_chan_info_dump(void *sel, _adapter *adapter);
++void rtw_acs_current_info_dump(void *sel, _adapter *adapter);
++
++void rtw_acs_start(_adapter *adapter);
++void rtw_acs_stop(_adapter *adapter);
++
++#endif /*CONFIG_RTW_ACS*/
++
++#ifdef CONFIG_BACKGROUND_NOISE_MONITOR
++#define RTK_NOISE_MONITOR_VERSION 3
++#define GET_NM_STATE(padapter) (ATOMIC_READ(&GET_HAL_DATA(padapter)->nm.state))
++#define SET_NM_STATE(padapter, set_state) (ATOMIC_SET(&GET_HAL_DATA(padapter)->nm.state, set_state))
++#define IS_NM_ENABLE(padapter) ((GET_NM_STATE(padapter) == NM_ENABLE) ? _TRUE : _FALSE)
++
++enum NM_STATE {
++ NM_DISABLE,
++ NM_ENABLE,
++};
++
++struct noise_monitor {
++ ATOMIC_T state;
++ s16 noise[MAX_CHANNEL_NUM];
++ u8 bss_nums[MAX_CHANNEL_NUM];
++};
++void rtw_nm_enable(_adapter *adapter);
++void rtw_nm_disable(_adapter *adapter);
++void rtw_noise_measure(_adapter *adapter, u8 chan, u8 is_pause_dig, u8 igi_value, u32 max_time);
++s16 rtw_noise_query_by_chan_num(_adapter *adapter, u8 chan);
++s16 rtw_noise_query_by_chan_idx(_adapter *adapter, u8 ch_idx);
++s16 rtw_noise_measure_curchan(_adapter *padapter);
++void rtw_noise_info_dump(void *sel, _adapter *adapter);
++#endif
++#endif /* __HAL_DM_ACS_H__ */
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/hal_dm.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/hal_dm.c
+--- linux-5.11.4/3rdparty/rtl8812au/hal/hal_dm.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/hal_dm.c 2021-03-07 18:16:17.051955911 +0200
@@ -0,0 +1,1616 @@
+/******************************************************************************
+ *
@@ -149983,11 +147610,9 @@ index 000000000..c5fa43e30
+ return;
+}
+
-diff --git linux-5.8/3rdparty/rtl8812au/hal/hal_dm.h linux-5.8/3rdparty/rtl8812au/hal/hal_dm.h
-new file mode 100644
-index 000000000..625021230
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/hal_dm.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/hal_dm.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/hal_dm.h
+--- linux-5.11.4/3rdparty/rtl8812au/hal/hal_dm.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/hal_dm.h 2021-03-07 18:16:17.051955911 +0200
@@ -0,0 +1,111 @@
+/******************************************************************************
+ *
@@ -150100,746 +147725,9 @@ index 000000000..625021230
+#endif
+
+#endif /* __HAL_DM_H__ */
-diff --git linux-5.8/3rdparty/rtl8812au/hal/hal_dm_acs.c linux-5.8/3rdparty/rtl8812au/hal/hal_dm_acs.c
-new file mode 100644
-index 000000000..49fc8a060
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/hal_dm_acs.c
-@@ -0,0 +1,556 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2014 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#include
-+#include
-+
-+
-+#if defined(CONFIG_RTW_ACS) || defined(CONFIG_BACKGROUND_NOISE_MONITOR)
-+static void _rtw_bss_nums_count(_adapter *adapter, u8 *pbss_nums)
-+{
-+ struct mlme_priv *pmlmepriv = &(adapter->mlmepriv);
-+ _queue *queue = &(pmlmepriv->scanned_queue);
-+ struct wlan_network *pnetwork = NULL;
-+ HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
-+
-+ _list *plist, *phead;
-+ _irqL irqL;
-+ int chan_idx = -1;
-+
-+ if (pbss_nums == NULL) {
-+ RTW_ERR("%s pbss_nums is null pointer\n", __func__);
-+ return;
-+ }
-+ _rtw_memset(pbss_nums, 0, MAX_CHANNEL_NUM);
-+
-+ _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
-+ phead = get_list_head(queue);
-+ plist = get_next(phead);
-+ while (1) {
-+ if (rtw_end_of_queue_search(phead, plist) == _TRUE)
-+ break;
-+
-+ pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list);
-+ if (!pnetwork)
-+ break;
-+ chan_idx = rtw_chset_search_ch(adapter_to_chset(adapter), pnetwork->network.Configuration.DSConfig);
-+ if ((chan_idx == -1) || (chan_idx >= MAX_CHANNEL_NUM)) {
-+ RTW_ERR("%s can't get chan_idx(CH:%d)\n",
-+ __func__, pnetwork->network.Configuration.DSConfig);
-+ chan_idx = 0;
-+ }
-+ /*if (pnetwork->network.Reserved[0] != BSS_TYPE_PROB_REQ)*/
-+
-+ pbss_nums[chan_idx]++;
-+
-+ plist = get_next(plist);
-+ }
-+ _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
-+}
-+
-+u8 rtw_get_ch_num_by_idx(_adapter *adapter, u8 idx)
-+{
-+ struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
-+ RT_CHANNEL_INFO *pch_set = rfctl->channel_set;
-+ u8 max_chan_nums = rfctl->max_chan_nums;
-+
-+ if (idx >= max_chan_nums)
-+ return 0;
-+ return pch_set[idx].ChannelNum;
-+}
-+#endif /*defined(CONFIG_RTW_ACS) || defined(CONFIG_BACKGROUND_NOISE_MONITOR)*/
-+
-+
-+#ifdef CONFIG_RTW_ACS
-+void rtw_acs_version_dump(void *sel, _adapter *adapter)
-+{
-+ _RTW_PRINT_SEL(sel, "RTK_ACS VER_%d\n", RTK_ACS_VERSION);
-+}
-+u8 rtw_phydm_clm_ratio(_adapter *adapter)
-+{
-+ struct dm_struct *phydm = adapter_to_phydm(adapter);
-+
-+ return phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_CLM_RATIO);
-+}
-+u8 rtw_phydm_nhm_ratio(_adapter *adapter)
-+{
-+ struct dm_struct *phydm = adapter_to_phydm(adapter);
-+
-+ return phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_NHM_RATIO);
-+}
-+void rtw_acs_reset(_adapter *adapter)
-+{
-+ HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
-+ struct auto_chan_sel *pacs = &hal_data->acs;
-+
-+ _rtw_memset(pacs, 0, sizeof(struct auto_chan_sel));
-+ #ifdef CONFIG_RTW_ACS_DBG
-+ rtw_acs_adv_reset(adapter);
-+ #endif /*CONFIG_RTW_ACS_DBG*/
-+}
-+
-+#ifdef CONFIG_RTW_ACS_DBG
-+u8 rtw_is_acs_igi_valid(_adapter *adapter)
-+{
-+ HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
-+ struct auto_chan_sel *pacs = &hal_data->acs;
-+
-+ if ((pacs->igi) && ((pacs->igi >= 0x1E) || (pacs->igi < 0x60)))
-+ return _TRUE;
-+
-+ return _FALSE;
-+}
-+void rtw_acs_adv_setting(_adapter *adapter, RT_SCAN_TYPE scan_type, u16 scan_time, u8 igi, u8 bw)
-+{
-+ HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
-+ struct auto_chan_sel *pacs = &hal_data->acs;
-+ struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv;
-+ struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info;
-+
-+ pacs->scan_type = scan_type;
-+ pacs->scan_time = scan_time;
-+ pacs->igi = igi;
-+ pacs->bw = bw;
-+ RTW_INFO("[ACS] ADV setting - scan_type:%c, ch_ms:%d(ms), igi:0x%02x, bw:%d\n",
-+ pacs->scan_type ? 'A' : 'P', pacs->scan_time, pacs->igi, pacs->bw);
-+}
-+void rtw_acs_adv_reset(_adapter *adapter)
-+{
-+ rtw_acs_adv_setting(adapter, SCAN_ACTIVE, 0, 0, 0);
-+}
-+#endif /*CONFIG_RTW_ACS_DBG*/
-+
-+void rtw_acs_trigger(_adapter *adapter, u16 scan_time_ms, u8 scan_chan, enum NHM_PID pid)
-+{
-+ HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
-+ struct dm_struct *phydm = adapter_to_phydm(adapter);
-+#if (RTK_ACS_VERSION == 3)
-+ struct clm_para_info clm_para;
-+ struct nhm_para_info nhm_para;
-+ struct env_trig_rpt trig_rpt;
-+
-+ scan_time_ms -= 10;
-+
-+ init_acs_clm(clm_para, scan_time_ms);
-+
-+ if (pid == NHM_PID_IEEE_11K_HIGH)
-+ init_11K_high_nhm(nhm_para, scan_time_ms);
-+ else if (pid == NHM_PID_IEEE_11K_LOW)
-+ init_11K_low_nhm(nhm_para, scan_time_ms);
-+ else
-+ init_acs_nhm(nhm_para, scan_time_ms);
-+
-+ hal_data->acs.trig_rst = phydm_env_mntr_trigger(phydm, &nhm_para, &clm_para, &trig_rpt);
-+ if (hal_data->acs.trig_rst == (NHM_SUCCESS | CLM_SUCCESS)) {
-+ hal_data->acs.trig_rpt.clm_rpt_stamp = trig_rpt.clm_rpt_stamp;
-+ hal_data->acs.trig_rpt.nhm_rpt_stamp = trig_rpt.nhm_rpt_stamp;
-+ /*RTW_INFO("[ACS] trigger success (rst = 0x%02x, clm_stamp:%d, nhm_stamp:%d)\n",
-+ hal_data->acs.trig_rst, hal_data->acs.trig_rpt.clm_rpt_stamp, hal_data->acs.trig_rpt.nhm_rpt_stamp);*/
-+ } else
-+ RTW_ERR("[ACS] trigger failed (rst = 0x%02x)\n", hal_data->acs.trig_rst);
-+#else
-+ phydm_ccx_monitor_trigger(phydm, scan_time_ms);
-+#endif
-+
-+ hal_data->acs.trigger_ch = scan_chan;
-+ hal_data->acs.triggered = _TRUE;
-+
-+ #ifdef CONFIG_RTW_ACS_DBG
-+ RTW_INFO("[ACS] Trigger CH:%d, Times:%d\n", hal_data->acs.trigger_ch, scan_time_ms);
-+ #endif
-+}
-+void rtw_acs_get_rst(_adapter *adapter)
-+{
-+ HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
-+ struct dm_struct *phydm = adapter_to_phydm(adapter);
-+ int chan_idx = -1;
-+ u8 cur_chan = hal_data->acs.trigger_ch;
-+
-+ if (cur_chan == 0)
-+ return;
-+
-+ if (!hal_data->acs.triggered)
-+ return;
-+
-+ chan_idx = rtw_chset_search_ch(adapter_to_chset(adapter), cur_chan);
-+ if ((chan_idx == -1) || (chan_idx >= MAX_CHANNEL_NUM)) {
-+ RTW_ERR("[ACS] %s can't get chan_idx(CH:%d)\n", __func__, cur_chan);
-+ return;
-+ }
-+#if (RTK_ACS_VERSION == 3)
-+ if (!(hal_data->acs.trig_rst == (NHM_SUCCESS | CLM_SUCCESS))) {
-+ RTW_ERR("[ACS] get_rst return, due to acs trigger failed\n");
-+ return;
-+ }
-+
-+ {
-+ struct env_mntr_rpt rpt = {0};
-+ u8 rst;
-+
-+ rst = phydm_env_mntr_result(phydm, &rpt);
-+ if ((rst == (NHM_SUCCESS | CLM_SUCCESS)) &&
-+ (rpt.clm_rpt_stamp == hal_data->acs.trig_rpt.clm_rpt_stamp) &&
-+ (rpt.nhm_rpt_stamp == hal_data->acs.trig_rpt.nhm_rpt_stamp)){
-+ hal_data->acs.clm_ratio[chan_idx] = rpt.clm_ratio;
-+ hal_data->acs.nhm_ratio[chan_idx] = rpt.nhm_ratio;
-+ _rtw_memcpy(&hal_data->acs.nhm[chan_idx][0], rpt.nhm_result, NHM_RPT_NUM);
-+
-+ /*RTW_INFO("[ACS] get_rst success (rst = 0x%02x, clm_stamp:%d:%d, nhm_stamp:%d:%d)\n",
-+ rst,
-+ hal_data->acs.trig_rpt.clm_rpt_stamp, rpt.clm_rpt_stamp,
-+ hal_data->acs.trig_rpt.nhm_rpt_stamp, rpt.nhm_rpt_stamp);*/
-+ } else {
-+ RTW_ERR("[ACS] get_rst failed (rst = 0x%02x, clm_stamp:%d:%d, nhm_stamp:%d:%d)\n",
-+ rst,
-+ hal_data->acs.trig_rpt.clm_rpt_stamp, rpt.clm_rpt_stamp,
-+ hal_data->acs.trig_rpt.nhm_rpt_stamp, rpt.nhm_rpt_stamp);
-+ }
-+ }
-+
-+#else
-+ phydm_ccx_monitor_result(phydm);
-+
-+ hal_data->acs.clm_ratio[chan_idx] = rtw_phydm_clm_ratio(adapter);
-+ hal_data->acs.nhm_ratio[chan_idx] = rtw_phydm_nhm_ratio(adapter);
-+#endif
-+ hal_data->acs.triggered = _FALSE;
-+ #ifdef CONFIG_RTW_ACS_DBG
-+ RTW_INFO("[ACS] Result CH:%d, CLM:%d NHM:%d\n",
-+ cur_chan, hal_data->acs.clm_ratio[chan_idx], hal_data->acs.nhm_ratio[chan_idx]);
-+ #endif
-+}
-+
-+void _rtw_phydm_acs_select_best_chan(_adapter *adapter)
-+{
-+ HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
-+ struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
-+ u8 ch_idx;
-+ u8 ch_idx_24g = 0xFF, ch_idx_5g = 0xFF;
-+ u8 min_itf_24g = 0xFF, min_itf_5g = 0xFF;
-+ u8 *pbss_nums = hal_data->acs.bss_nums;
-+ u8 *pclm_ratio = hal_data->acs.clm_ratio;
-+ u8 *pnhm_ratio = hal_data->acs.nhm_ratio;
-+ u8 *pinterference_time = hal_data->acs.interference_time;
-+ u8 max_chan_nums = rfctl->max_chan_nums;
-+
-+ for (ch_idx = 0; ch_idx < max_chan_nums; ch_idx++) {
-+ if (pbss_nums[ch_idx])
-+ pinterference_time[ch_idx] = (pclm_ratio[ch_idx] / 2) + pnhm_ratio[ch_idx];
-+ else
-+ pinterference_time[ch_idx] = pclm_ratio[ch_idx] + pnhm_ratio[ch_idx];
-+
-+ if (rtw_get_ch_num_by_idx(adapter, ch_idx) < 14) {
-+ if (pinterference_time[ch_idx] < min_itf_24g) {
-+ min_itf_24g = pinterference_time[ch_idx];
-+ ch_idx_24g = ch_idx;
-+ }
-+ } else {
-+ if (pinterference_time[ch_idx] < min_itf_5g) {
-+ min_itf_5g = pinterference_time[ch_idx];
-+ ch_idx_5g = ch_idx;
-+ }
-+ }
-+ }
-+ if (ch_idx_24g != 0xFF)
-+ hal_data->acs.best_chan_24g = rtw_get_ch_num_by_idx(adapter, ch_idx_24g);
-+
-+ if (ch_idx_5g != 0xFF)
-+ hal_data->acs.best_chan_5g = rtw_get_ch_num_by_idx(adapter, ch_idx_5g);
-+
-+ hal_data->acs.trigger_ch = 0;
-+}
-+
-+void rtw_acs_info_dump(void *sel, _adapter *adapter)
-+{
-+ HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
-+ struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
-+ u8 max_chan_nums = rfctl->max_chan_nums;
-+ u8 ch_idx, ch_num;
-+
-+ _RTW_PRINT_SEL(sel, "========== ACS (VER-%d) ==========\n", RTK_ACS_VERSION);
-+ _RTW_PRINT_SEL(sel, "Best 24G Channel:%d\n", hal_data->acs.best_chan_24g);
-+ _RTW_PRINT_SEL(sel, "Best 5G Channel:%d\n\n", hal_data->acs.best_chan_5g);
-+
-+ #ifdef CONFIG_RTW_ACS_DBG
-+ _RTW_PRINT_SEL(sel, "Advanced setting - scan_type:%c, ch_ms:%d(ms), igi:0x%02x, bw:%d\n",
-+ hal_data->acs.scan_type ? 'A' : 'P', hal_data->acs.scan_time, hal_data->acs.igi, hal_data->acs.bw);
-+
-+ _RTW_PRINT_SEL(sel, "BW 20MHz\n");
-+ _RTW_PRINT_SEL(sel, "%5s %3s %3s %3s(%%) %3s(%%) %3s\n",
-+ "Index", "CH", "BSS", "CLM", "NHM", "ITF");
-+
-+ for (ch_idx = 0; ch_idx < max_chan_nums; ch_idx++) {
-+ ch_num = rtw_get_ch_num_by_idx(adapter, ch_idx);
-+ _RTW_PRINT_SEL(sel, "%5d %3d %3d %6d %6d %3d\n",
-+ ch_idx, ch_num, hal_data->acs.bss_nums[ch_idx],
-+ hal_data->acs.clm_ratio[ch_idx],
-+ hal_data->acs.nhm_ratio[ch_idx],
-+ hal_data->acs.interference_time[ch_idx]);
-+ }
-+ #endif
-+}
-+void rtw_acs_select_best_chan(_adapter *adapter)
-+{
-+ HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
-+
-+ _rtw_bss_nums_count(adapter, hal_data->acs.bss_nums);
-+ _rtw_phydm_acs_select_best_chan(adapter);
-+ rtw_acs_info_dump(RTW_DBGDUMP, adapter);
-+}
-+
-+void rtw_acs_start(_adapter *adapter)
-+{
-+ rtw_acs_reset(adapter);
-+ if (GET_ACS_STATE(adapter) != ACS_ENABLE)
-+ SET_ACS_STATE(adapter, ACS_ENABLE);
-+}
-+void rtw_acs_stop(_adapter *adapter)
-+{
-+ SET_ACS_STATE(adapter, ACS_DISABLE);
-+}
-+
-+
-+u8 rtw_acs_get_clm_ratio_by_ch_num(_adapter *adapter, u8 chan)
-+{
-+ HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
-+ int chan_idx = -1;
-+
-+ chan_idx = rtw_chset_search_ch(adapter_to_chset(adapter), chan);
-+ if ((chan_idx == -1) || (chan_idx >= MAX_CHANNEL_NUM)) {
-+ RTW_ERR("[ACS] Get CLM fail, can't get chan_idx(CH:%d)\n", chan);
-+ return 0;
-+ }
-+
-+ return hal_data->acs.clm_ratio[chan_idx];
-+}
-+u8 rtw_acs_get_clm_ratio_by_ch_idx(_adapter *adapter, u8 ch_idx)
-+{
-+ HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
-+
-+ if (ch_idx >= MAX_CHANNEL_NUM) {
-+ RTW_ERR("%s [ACS] ch_idx(%d) is invalid\n", __func__, ch_idx);
-+ return 0;
-+ }
-+
-+ return hal_data->acs.clm_ratio[ch_idx];
-+}
-+u8 rtw_acs_get_nhm_ratio_by_ch_num(_adapter *adapter, u8 chan)
-+{
-+ HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
-+ int chan_idx = -1;
-+
-+ chan_idx = rtw_chset_search_ch(adapter_to_chset(adapter), chan);
-+ if ((chan_idx == -1) || (chan_idx >= MAX_CHANNEL_NUM)) {
-+ RTW_ERR("[ACS] Get NHM fail, can't get chan_idx(CH:%d)\n", chan);
-+ return 0;
-+ }
-+
-+ return hal_data->acs.nhm_ratio[chan_idx];
-+}
-+u8 rtw_acs_get_num_ratio_by_ch_idx(_adapter *adapter, u8 ch_idx)
-+{
-+ HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
-+
-+ if (ch_idx >= MAX_CHANNEL_NUM) {
-+ RTW_ERR("%s [ACS] ch_idx(%d) is invalid\n", __func__, ch_idx);
-+ return 0;
-+ }
-+
-+ return hal_data->acs.nhm_ratio[ch_idx];
-+}
-+void rtw_acs_chan_info_dump(void *sel, _adapter *adapter)
-+{
-+ HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
-+ struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
-+ u8 max_chan_nums = rfctl->max_chan_nums;
-+ u8 ch_idx, ch_num;
-+ u8 utilization;
-+
-+ _RTW_PRINT_SEL(sel, "BW 20MHz\n");
-+ _RTW_PRINT_SEL(sel, "%5s %3s %7s(%%) %12s(%%) %11s(%%) %9s(%%) %8s(%%)\n",
-+ "Index", "CH", "Quality", "Availability", "Utilization",
-+ "WIFI Util", "Interference Util");
-+
-+ for (ch_idx = 0; ch_idx < max_chan_nums; ch_idx++) {
-+ ch_num = rtw_get_ch_num_by_idx(adapter, ch_idx);
-+ utilization = hal_data->acs.clm_ratio[ch_idx] + hal_data->acs.nhm_ratio[ch_idx];
-+ _RTW_PRINT_SEL(sel, "%5d %3d %7d %12d %12d %12d %12d\n",
-+ ch_idx, ch_num,
-+ (100-hal_data->acs.interference_time[ch_idx]),
-+ (100-utilization),
-+ utilization,
-+ hal_data->acs.clm_ratio[ch_idx],
-+ hal_data->acs.nhm_ratio[ch_idx]);
-+ }
-+}
-+void rtw_acs_current_info_dump(void *sel, _adapter *adapter)
-+{
-+ HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
-+ u8 ch, cen_ch, bw, offset;
-+
-+ _RTW_PRINT_SEL(sel, "========== ACS (VER-%d) ==========\n", RTK_ACS_VERSION);
-+
-+ ch = rtw_get_oper_ch(adapter);
-+ bw = rtw_get_oper_bw(adapter);
-+ offset = rtw_get_oper_choffset(adapter);
-+
-+ _RTW_PRINT_SEL(sel, "Current Channel:%d\n", ch);
-+ if ((bw == CHANNEL_WIDTH_80) ||(bw == CHANNEL_WIDTH_40)) {
-+ cen_ch = rtw_get_center_ch(ch, bw, offset);
-+ _RTW_PRINT_SEL(sel, "Center Channel:%d\n", cen_ch);
-+ }
-+
-+ _RTW_PRINT_SEL(sel, "Current BW %s\n", ch_width_str(bw));
-+ if (0)
-+ _RTW_PRINT_SEL(sel, "Current IGI 0x%02x\n", rtw_phydm_get_cur_igi(adapter));
-+ _RTW_PRINT_SEL(sel, "CLM:%d, NHM:%d\n\n",
-+ hal_data->acs.cur_ch_clm_ratio, hal_data->acs.cur_ch_nhm_ratio);
-+}
-+
-+void rtw_acs_update_current_info(_adapter *adapter)
-+{
-+ HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
-+
-+ hal_data->acs.cur_ch_clm_ratio = rtw_phydm_clm_ratio(adapter);
-+ hal_data->acs.cur_ch_nhm_ratio = rtw_phydm_nhm_ratio(adapter);
-+
-+ #ifdef CONFIG_RTW_ACS_DBG
-+ rtw_acs_current_info_dump(RTW_DBGDUMP, adapter);
-+ #endif
-+}
-+#endif /*CONFIG_RTW_ACS*/
-+
-+#ifdef CONFIG_BACKGROUND_NOISE_MONITOR
-+void rtw_noise_monitor_version_dump(void *sel, _adapter *adapter)
-+{
-+ _RTW_PRINT_SEL(sel, "RTK_NOISE_MONITOR VER_%d\n", RTK_NOISE_MONITOR_VERSION);
-+}
-+void rtw_nm_enable(_adapter *adapter)
-+{
-+ SET_NM_STATE(adapter, NM_ENABLE);
-+}
-+void rtw_nm_disable(_adapter *adapter)
-+{
-+ SET_NM_STATE(adapter, NM_DISABLE);
-+}
-+void rtw_noise_info_dump(void *sel, _adapter *adapter)
-+{
-+ HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
-+ struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
-+ u8 max_chan_nums = rfctl->max_chan_nums;
-+ u8 ch_idx, ch_num;
-+
-+ _RTW_PRINT_SEL(sel, "========== NM (VER-%d) ==========\n", RTK_NOISE_MONITOR_VERSION);
-+
-+ _RTW_PRINT_SEL(sel, "%5s %3s %3s %10s", "Index", "CH", "BSS", "Noise(dBm)\n");
-+
-+ _rtw_bss_nums_count(adapter, hal_data->nm.bss_nums);
-+
-+ for (ch_idx = 0; ch_idx < max_chan_nums; ch_idx++) {
-+ ch_num = rtw_get_ch_num_by_idx(adapter, ch_idx);
-+ _RTW_PRINT_SEL(sel, "%5d %3d %3d %10d\n",
-+ ch_idx, ch_num, hal_data->nm.bss_nums[ch_idx],
-+ hal_data->nm.noise[ch_idx]);
-+ }
-+}
-+
-+void rtw_noise_measure(_adapter *adapter, u8 chan, u8 is_pause_dig, u8 igi_value, u32 max_time)
-+{
-+ HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
-+ struct dm_struct *phydm = &hal_data->odmpriv;
-+ int chan_idx = -1;
-+ s16 noise = 0;
-+
-+ #ifdef DBG_NOISE_MONITOR
-+ RTW_INFO("[NM] chan(%d)-PauseDIG:%s, IGIValue:0x%02x, max_time:%d (ms)\n",
-+ chan, (is_pause_dig) ? "Y" : "N", igi_value, max_time);
-+ #endif
-+
-+ chan_idx = rtw_chset_search_ch(adapter_to_chset(adapter), chan);
-+ if ((chan_idx == -1) || (chan_idx >= MAX_CHANNEL_NUM)) {
-+ RTW_ERR("[NM] Get noise fail, can't get chan_idx(CH:%d)\n", chan);
-+ return;
-+ }
-+ noise = odm_inband_noise_monitor(phydm, is_pause_dig, igi_value, max_time); /*dBm*/
-+
-+ hal_data->nm.noise[chan_idx] = noise;
-+
-+ #ifdef DBG_NOISE_MONITOR
-+ RTW_INFO("[NM] %s chan_%d, noise = %d (dBm)\n", __func__, chan, hal_data->nm.noise[chan_idx]);
-+
-+ RTW_INFO("[NM] noise_a = %d, noise_b = %d noise_all:%d\n",
-+ phydm->noise_level.noise[RF_PATH_A],
-+ phydm->noise_level.noise[RF_PATH_B],
-+ phydm->noise_level.noise_all);
-+ #endif /*DBG_NOISE_MONITOR*/
-+}
-+
-+s16 rtw_noise_query_by_chan_num(_adapter *adapter, u8 chan)
-+{
-+ HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
-+ s16 noise = 0;
-+ int chan_idx = -1;
-+
-+ chan_idx = rtw_chset_search_ch(adapter_to_chset(adapter), chan);
-+ if ((chan_idx == -1) || (chan_idx >= MAX_CHANNEL_NUM)) {
-+ RTW_ERR("[NM] Get noise fail, can't get chan_idx(CH:%d)\n", chan);
-+ return noise;
-+ }
-+ noise = hal_data->nm.noise[chan_idx];
-+
-+ #ifdef DBG_NOISE_MONITOR
-+ RTW_INFO("[NM] %s chan_%d, noise = %d (dBm)\n", __func__, chan, noise);
-+ #endif/*DBG_NOISE_MONITOR*/
-+ return noise;
-+}
-+s16 rtw_noise_query_by_chan_idx(_adapter *adapter, u8 ch_idx)
-+{
-+ HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
-+ s16 noise = 0;
-+
-+ if (ch_idx >= MAX_CHANNEL_NUM) {
-+ RTW_ERR("[NM] %s ch_idx(%d) is invalid\n", __func__, ch_idx);
-+ return noise;
-+ }
-+ noise = hal_data->nm.noise[ch_idx];
-+
-+ #ifdef DBG_NOISE_MONITOR
-+ RTW_INFO("[NM] %s ch_idx %d, noise = %d (dBm)\n", __func__, ch_idx, noise);
-+ #endif/*DBG_NOISE_MONITOR*/
-+ return noise;
-+}
-+
-+s16 rtw_noise_measure_curchan(_adapter *padapter)
-+{
-+ s16 noise = 0;
-+ u8 igi_value = 0x1E;
-+ u32 max_time = 100;/* ms */
-+ u8 is_pause_dig = _TRUE;
-+ u8 cur_chan = rtw_get_oper_ch(padapter);
-+
-+#ifndef CONFIG_ALLOW_UNLINKED_NOISE_MONITOR
-+ if (rtw_linked_check(padapter) == _FALSE)
-+ return noise;
-+#endif
-+
-+ rtw_ps_deny(padapter, PS_DENY_IOCTL);
-+ LeaveAllPowerSaveModeDirect(padapter);
-+ rtw_noise_measure(padapter, cur_chan, is_pause_dig, igi_value, max_time);
-+ noise = rtw_noise_query_by_chan_num(padapter, cur_chan);
-+ rtw_ps_deny_cancel(padapter, PS_DENY_IOCTL);
-+
-+ return noise;
-+}
-+#endif /*CONFIG_BACKGROUND_NOISE_MONITOR*/
-+
-diff --git linux-5.8/3rdparty/rtl8812au/hal/hal_dm_acs.h linux-5.8/3rdparty/rtl8812au/hal/hal_dm_acs.h
-new file mode 100644
-index 000000000..871c14487
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/hal_dm_acs.h
-@@ -0,0 +1,167 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __HAL_DM_ACS_H__
-+#define __HAL_DM_ACS_H__
-+#ifdef CONFIG_RTW_ACS
-+#define RTK_ACS_VERSION 3
-+
-+#if (RTK_ACS_VERSION == 3)
-+enum NHM_PID {
-+ NHM_PID_ACS,
-+ NHM_PID_IEEE_11K_HIGH,
-+ NHM_PID_IEEE_11K_LOW,
-+};
-+
-+#define init_clm_param(clm, app, lv, time) \
-+ do {\
-+ clm.clm_app = app;\
-+ clm.clm_lv = lv;\
-+ clm.mntr_time = time;\
-+ } while (0)
-+
-+#define init_nhm_param(nhm, txon, cca, cnt_opt, app, lv, time) \
-+ do {\
-+ nhm.incld_txon = txon;\
-+ nhm.incld_cca = cca;\
-+ nhm.div_opt = cnt_opt;\
-+ nhm.nhm_app = app;\
-+ nhm.nhm_lv = lv;\
-+ nhm.mntr_time = time;\
-+ } while (0)
-+
-+
-+#define init_acs_clm(clm, time) \
-+ init_clm_param(clm, CLM_ACS, CLM_LV_2, time)
-+
-+#define init_acs_nhm(nhm, time) \
-+ init_nhm_param(nhm, NHM_EXCLUDE_TXON, NHM_EXCLUDE_CCA, NHM_CNT_ALL, NHM_ACS, NHM_LV_2, time)
-+
-+#define init_11K_high_nhm(nhm, time) \
-+ init_nhm_param(nhm, NHM_EXCLUDE_TXON, NHM_EXCLUDE_CCA, NHM_CNT_ALL, IEEE_11K_HIGH, NHM_LV_2, time)
-+
-+#define init_11K_low_nhm(nhm, time) \
-+ init_nhm_param(nhm, NHM_EXCLUDE_TXON, NHM_EXCLUDE_CCA, NHM_CNT_ALL, IEEE_11K_LOW, NHM_LV_2, time)
-+
-+
-+#endif /*(RTK_ACS_VERSION == 3)*/
-+void rtw_acs_version_dump(void *sel, _adapter *adapter);
-+extern void phydm_ccx_monitor_trigger(void *p_dm_void, u16 monitor_time);
-+extern void phydm_ccx_monitor_result(void *p_dm_void);
-+
-+#define GET_ACS_STATE(padapter) (ATOMIC_READ(&GET_HAL_DATA(padapter)->acs.state))
-+#define SET_ACS_STATE(padapter, set_state) (ATOMIC_SET(&GET_HAL_DATA(padapter)->acs.state, set_state))
-+#define IS_ACS_ENABLE(padapter) ((GET_ACS_STATE(padapter) == ACS_ENABLE) ? _TRUE : _FALSE)
-+
-+enum ACS_STATE {
-+ ACS_DISABLE,
-+ ACS_ENABLE,
-+};
-+
-+#define ACS_BW_20M BIT(0)
-+#define ACS_BW_40M BIT(1)
-+#define ACS_BW_80M BIT(2)
-+#define ACS_BW_160M BIT(3)
-+
-+struct auto_chan_sel {
-+ ATOMIC_T state;
-+ u8 trigger_ch;
-+ bool triggered;
-+ u8 clm_ratio[MAX_CHANNEL_NUM];
-+ u8 nhm_ratio[MAX_CHANNEL_NUM];
-+ #if (RTK_ACS_VERSION == 3)
-+ u8 nhm[MAX_CHANNEL_NUM][NHM_RPT_NUM];
-+ #endif
-+ u8 bss_nums[MAX_CHANNEL_NUM];
-+ u8 interference_time[MAX_CHANNEL_NUM];
-+ u8 cur_ch_clm_ratio;
-+ u8 cur_ch_nhm_ratio;
-+ u8 best_chan_5g;
-+ u8 best_chan_24g;
-+
-+ #if (RTK_ACS_VERSION == 3)
-+ u8 trig_rst;
-+ struct env_trig_rpt trig_rpt;
-+ #endif
-+
-+ #ifdef CONFIG_RTW_ACS_DBG
-+ RT_SCAN_TYPE scan_type;
-+ u16 scan_time;
-+ u8 igi;
-+ u8 bw;
-+ #endif
-+};
-+
-+#define rtw_acs_get_best_chan_24g(adapter) (GET_HAL_DATA(adapter)->acs.best_chan_24g)
-+#define rtw_acs_get_best_chan_5g(adapter) (GET_HAL_DATA(adapter)->acs.best_chan_5g)
-+
-+#ifdef CONFIG_RTW_ACS_DBG
-+#define rtw_is_acs_passiv_scan(adapter) (((GET_HAL_DATA(adapter)->acs.scan_type) == SCAN_PASSIVE) ? _TRUE : _FALSE)
-+
-+#define rtw_acs_get_adv_st(adapter) (GET_HAL_DATA(adapter)->acs.scan_time)
-+#define rtw_is_acs_st_valid(adapter) ((GET_HAL_DATA(adapter)->acs.scan_time) ? _TRUE : _FALSE)
-+
-+#define rtw_acs_get_adv_igi(adapter) (GET_HAL_DATA(adapter)->acs.igi)
-+u8 rtw_is_acs_igi_valid(_adapter *adapter);
-+
-+#define rtw_acs_get_adv_bw(adapter) (GET_HAL_DATA(adapter)->acs.bw)
-+
-+void rtw_acs_adv_setting(_adapter *adapter, RT_SCAN_TYPE scan_type, u16 scan_time, u8 igi, u8 bw);
-+void rtw_acs_adv_reset(_adapter *adapter);
-+#endif
-+
-+u8 rtw_acs_get_clm_ratio_by_ch_num(_adapter *adapter, u8 chan);
-+u8 rtw_acs_get_clm_ratio_by_ch_idx(_adapter *adapter, u8 ch_idx);
-+u8 rtw_acs_get_nhm_ratio_by_ch_num(_adapter *adapter, u8 chan);
-+u8 rtw_acs_get_num_ratio_by_ch_idx(_adapter *adapter, u8 ch_idx);
-+
-+void rtw_acs_reset(_adapter *adapter);
-+void rtw_acs_trigger(_adapter *adapter, u16 scan_time_ms, u8 scan_chan, enum NHM_PID pid);
-+void rtw_acs_get_rst(_adapter *adapter);
-+void rtw_acs_select_best_chan(_adapter *adapter);
-+void rtw_acs_info_dump(void *sel, _adapter *adapter);
-+void rtw_acs_update_current_info(_adapter *adapter);
-+void rtw_acs_chan_info_dump(void *sel, _adapter *adapter);
-+void rtw_acs_current_info_dump(void *sel, _adapter *adapter);
-+
-+void rtw_acs_start(_adapter *adapter);
-+void rtw_acs_stop(_adapter *adapter);
-+
-+#endif /*CONFIG_RTW_ACS*/
-+
-+#ifdef CONFIG_BACKGROUND_NOISE_MONITOR
-+#define RTK_NOISE_MONITOR_VERSION 3
-+#define GET_NM_STATE(padapter) (ATOMIC_READ(&GET_HAL_DATA(padapter)->nm.state))
-+#define SET_NM_STATE(padapter, set_state) (ATOMIC_SET(&GET_HAL_DATA(padapter)->nm.state, set_state))
-+#define IS_NM_ENABLE(padapter) ((GET_NM_STATE(padapter) == NM_ENABLE) ? _TRUE : _FALSE)
-+
-+enum NM_STATE {
-+ NM_DISABLE,
-+ NM_ENABLE,
-+};
-+
-+struct noise_monitor {
-+ ATOMIC_T state;
-+ s16 noise[MAX_CHANNEL_NUM];
-+ u8 bss_nums[MAX_CHANNEL_NUM];
-+};
-+void rtw_nm_enable(_adapter *adapter);
-+void rtw_nm_disable(_adapter *adapter);
-+void rtw_noise_measure(_adapter *adapter, u8 chan, u8 is_pause_dig, u8 igi_value, u32 max_time);
-+s16 rtw_noise_query_by_chan_num(_adapter *adapter, u8 chan);
-+s16 rtw_noise_query_by_chan_idx(_adapter *adapter, u8 ch_idx);
-+s16 rtw_noise_measure_curchan(_adapter *padapter);
-+void rtw_noise_info_dump(void *sel, _adapter *adapter);
-+#endif
-+#endif /* __HAL_DM_ACS_H__ */
-diff --git linux-5.8/3rdparty/rtl8812au/hal/hal_halmac.c linux-5.8/3rdparty/rtl8812au/hal/hal_halmac.c
-new file mode 100644
-index 000000000..0b74ecb48
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/hal_halmac.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/hal_halmac.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/hal_halmac.c
+--- linux-5.11.4/3rdparty/rtl8812au/hal/hal_halmac.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/hal_halmac.c 2021-03-07 18:16:17.052955958 +0200
@@ -0,0 +1,5555 @@
+/******************************************************************************
+ *
@@ -156396,11 +153284,9 @@ index 000000000..0b74ecb48
+
+#endif /* RTW_BEAMFORMING_VERSION_2 */
+#endif /* CONFIG_BEAMFORMING */
-diff --git linux-5.8/3rdparty/rtl8812au/hal/hal_halmac.h linux-5.8/3rdparty/rtl8812au/hal/hal_halmac.h
-new file mode 100644
-index 000000000..152a0e83a
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/hal_halmac.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/hal_halmac.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/hal_halmac.h
+--- linux-5.11.4/3rdparty/rtl8812au/hal/hal_halmac.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/hal_halmac.h 2021-03-07 18:16:17.052955958 +0200
@@ -0,0 +1,245 @@
+/******************************************************************************
+ *
@@ -156647,11 +153533,9 @@ index 000000000..152a0e83a
+#endif /* CONFIG_BEAMFORMING */
+
+#endif /* _HAL_HALMAC_H_ */
-diff --git linux-5.8/3rdparty/rtl8812au/hal/hal_hci/hal_usb.c linux-5.8/3rdparty/rtl8812au/hal/hal_hci/hal_usb.c
-new file mode 100644
-index 000000000..20dc07bdf
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/hal_hci/hal_usb.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/hal_hci/hal_usb.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/hal_hci/hal_usb.c
+--- linux-5.11.4/3rdparty/rtl8812au/hal/hal_hci/hal_usb.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/hal_hci/hal_usb.c 2021-03-07 18:16:17.052955958 +0200
@@ -0,0 +1,564 @@
+/******************************************************************************
+ *
@@ -157217,11 +154101,9 @@ index 000000000..20dc07bdf
+#endif
+
+}
-diff --git linux-5.8/3rdparty/rtl8812au/hal/hal_intf.c linux-5.8/3rdparty/rtl8812au/hal/hal_intf.c
-new file mode 100644
-index 000000000..66a2954c5
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/hal_intf.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/hal_intf.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/hal_intf.c
+--- linux-5.11.4/3rdparty/rtl8812au/hal/hal_intf.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/hal_intf.c 2021-03-07 18:16:17.052955958 +0200
@@ -0,0 +1,1716 @@
+/******************************************************************************
+ *
@@ -158939,11 +155821,9 @@ index 000000000..66a2954c5
+#endif
+ return ret;
+}
-diff --git linux-5.8/3rdparty/rtl8812au/hal/hal_mcc.c linux-5.8/3rdparty/rtl8812au/hal/hal_mcc.c
-new file mode 100644
-index 000000000..179d4d54b
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/hal_mcc.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/hal_mcc.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/hal_mcc.c
+--- linux-5.11.4/3rdparty/rtl8812au/hal/hal_mcc.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/hal_mcc.c 2021-03-07 18:16:17.052955958 +0200
@@ -0,0 +1,3488 @@
+/******************************************************************************
+ *
@@ -162433,11 +159313,9 @@ index 000000000..179d4d54b
+}
+
+#endif /* CONFIG_MCC_MODE */
-diff --git linux-5.8/3rdparty/rtl8812au/hal/hal_mp.c linux-5.8/3rdparty/rtl8812au/hal/hal_mp.c
-new file mode 100644
-index 000000000..0f084c7e9
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/hal_mp.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/hal_mp.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/hal_mp.c
+--- linux-5.11.4/3rdparty/rtl8812au/hal/hal_mp.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/hal_mp.c 2021-03-07 18:16:17.053956006 +0200
@@ -0,0 +1,2269 @@
+/******************************************************************************
+ *
@@ -163355,7 +160233,7 @@ index 000000000..0f084c7e9
+
+ phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1); /*/ Disable CCA*/
+
-+ for (StartPath; StartPath <= EndPath; StartPath++) {
++ for (; StartPath <= EndPath; StartPath++) {
+ phy_set_rf_reg(pAdapter, StartPath, RF_AC_Jaguar, 0xF0000, 0x2); /*/ Tx mode: RF0x00[19:16]=4'b0010 */
+ phy_set_rf_reg(pAdapter, StartPath, RF_AC_Jaguar, 0x1F, 0x0); /*/ Lowest RF gain index: RF_0x0[4:0] = 0*/
+
@@ -163393,7 +160271,7 @@ index 000000000..0f084c7e9
+ EndPath = RF_PATH_D;
+ break;
+ }
-+ for (StartPath; StartPath <= EndPath; StartPath++)
++ for (; StartPath <= EndPath; StartPath++)
+ phy_set_rf_reg(pAdapter, StartPath, lna_low_gain_3, BIT1, 0x0); /* RF LO disabled */
+
+ phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0); /* Enable CCA*/
@@ -164708,11 +161586,9 @@ index 000000000..0f084c7e9
+}
+
+#endif /* CONFIG_MP_INCLUDE*/
-diff --git linux-5.8/3rdparty/rtl8812au/hal/hal_phy.c linux-5.8/3rdparty/rtl8812au/hal/hal_phy.c
-new file mode 100644
-index 000000000..1504a73ba
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/hal_phy.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/hal_phy.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/hal_phy.c
+--- linux-5.11.4/3rdparty/rtl8812au/hal/hal_phy.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/hal_phy.c 2021-03-07 18:16:17.053956006 +0200
@@ -0,0 +1,257 @@
+/******************************************************************************
+ *
@@ -164971,11 +161847,198 @@ index 000000000..1504a73ba
+
+} /* PHY_RFShadowRead */
+#endif /*CONFIG_RF_SHADOW_RW*/
-diff --git linux-5.8/3rdparty/rtl8812au/hal/led/hal_led.c linux-5.8/3rdparty/rtl8812au/hal/led/hal_led.c
-new file mode 100644
-index 000000000..033d23b4c
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/led/hal_led.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/HalPwrSeqCmd.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/HalPwrSeqCmd.c
+--- linux-5.11.4/3rdparty/rtl8812au/hal/HalPwrSeqCmd.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/HalPwrSeqCmd.c 2021-03-07 18:16:17.049955817 +0200
+@@ -0,0 +1,185 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++/*++
++Copyright (c) Realtek Semiconductor Corp. All rights reserved.
++
++Module Name:
++ HalPwrSeqCmd.c
++
++Abstract:
++ Implement HW Power sequence configuration CMD handling routine for Realtek devices.
++
++Major Change History:
++ When Who What
++ ---------- --------------- -------------------------------
++ 2011-10-26 Lucas Modify to be compatible with SD4-CE driver.
++ 2011-07-07 Roger Create.
++
++--*/
++#include
++
++
++/*
++ * Description:
++ * This routine deal with the Power Configuration CMDs parsing for RTL8723/RTL8188E Series IC.
++ *
++ * Assumption:
++ * We should follow specific format which was released from HW SD.
++ *
++ * 2011.07.07, added by Roger.
++ * */
++u8 HalPwrSeqCmdParsing(
++ PADAPTER padapter,
++ u8 CutVersion,
++ u8 FabVersion,
++ u8 InterfaceType,
++ WLAN_PWR_CFG PwrSeqCmd[])
++{
++ WLAN_PWR_CFG PwrCfgCmd = {0};
++ u8 bPollingBit = _FALSE;
++ u8 bHWICSupport = _FALSE;
++ u32 AryIdx = 0;
++ u8 value = 0;
++ u32 offset = 0;
++ u8 flag = 0;
++ u32 pollingCount = 0; /* polling autoload done. */
++ u32 maxPollingCnt = 5000;
++
++ do {
++ PwrCfgCmd = PwrSeqCmd[AryIdx];
++
++
++ /* 2 Only Handle the command whose FAB, CUT, and Interface are matched */
++ if ((GET_PWR_CFG_FAB_MASK(PwrCfgCmd) & FabVersion) &&
++ (GET_PWR_CFG_CUT_MASK(PwrCfgCmd) & CutVersion) &&
++ (GET_PWR_CFG_INTF_MASK(PwrCfgCmd) & InterfaceType)) {
++ switch (GET_PWR_CFG_CMD(PwrCfgCmd)) {
++ case PWR_CMD_READ:
++ break;
++
++ case PWR_CMD_WRITE:
++ offset = GET_PWR_CFG_OFFSET(PwrCfgCmd);
++
++#ifdef CONFIG_SDIO_HCI
++ /* */
++ /* We should deal with interface specific address mapping for some interfaces, e.g., SDIO interface */
++ /* 2011.07.07. */
++ /* */
++ if (GET_PWR_CFG_BASE(PwrCfgCmd) == PWR_BASEADDR_SDIO) {
++ /* Read Back SDIO Local value */
++ value = SdioLocalCmd52Read1Byte(padapter, offset);
++
++ value &= ~(GET_PWR_CFG_MASK(PwrCfgCmd));
++ value |= (GET_PWR_CFG_VALUE(PwrCfgCmd) & GET_PWR_CFG_MASK(PwrCfgCmd));
++
++ /* Write Back SDIO Local value */
++ SdioLocalCmd52Write1Byte(padapter, offset, value);
++ } else
++#endif
++ {
++#ifdef CONFIG_GSPI_HCI
++ if (GET_PWR_CFG_BASE(PwrCfgCmd) == PWR_BASEADDR_SDIO)
++ offset = SPI_LOCAL_OFFSET | offset;
++#endif
++ /* Read the value from system register */
++ value = rtw_read8(padapter, offset);
++
++ value = value & (~(GET_PWR_CFG_MASK(PwrCfgCmd)));
++ value = value | (GET_PWR_CFG_VALUE(PwrCfgCmd) & GET_PWR_CFG_MASK(PwrCfgCmd));
++
++ /* Write the value back to sytem register */
++ rtw_write8(padapter, offset, value);
++ }
++ break;
++
++ case PWR_CMD_POLLING:
++
++ bPollingBit = _FALSE;
++ offset = GET_PWR_CFG_OFFSET(PwrCfgCmd);
++
++ rtw_hal_get_hwreg(padapter, HW_VAR_PWR_CMD, &bHWICSupport);
++ if (bHWICSupport && offset == 0x06) {
++ flag = 0;
++ maxPollingCnt = 100000;
++ } else
++ maxPollingCnt = 5000;
++
++#ifdef CONFIG_GSPI_HCI
++ if (GET_PWR_CFG_BASE(PwrCfgCmd) == PWR_BASEADDR_SDIO)
++ offset = SPI_LOCAL_OFFSET | offset;
++#endif
++ do {
++#ifdef CONFIG_SDIO_HCI
++ if (GET_PWR_CFG_BASE(PwrCfgCmd) == PWR_BASEADDR_SDIO)
++ value = SdioLocalCmd52Read1Byte(padapter, offset);
++ else
++#endif
++ value = rtw_read8(padapter, offset);
++
++ value = value & GET_PWR_CFG_MASK(PwrCfgCmd);
++ if (value == (GET_PWR_CFG_VALUE(PwrCfgCmd) & GET_PWR_CFG_MASK(PwrCfgCmd)))
++ bPollingBit = _TRUE;
++ else
++ rtw_udelay_os(10);
++
++ if (pollingCount++ > maxPollingCnt) {
++ RTW_ERR("HalPwrSeqCmdParsing: Fail to polling Offset[%#x]=%02x\n", offset, value);
++
++ /* For PCIE + USB package poll power bit timeout issue only modify 8821AE and 8723BE */
++ if (bHWICSupport && offset == 0x06 && flag == 0) {
++
++ RTW_ERR("[WARNING] PCIE polling(0x%X) timeout(%d), Toggle 0x04[3] and try again.\n", offset, maxPollingCnt);
++ if (IS_HARDWARE_TYPE_8723DE(padapter))
++ PlatformEFIOWrite1Byte(padapter, 0x40, (PlatformEFIORead1Byte(padapter, 0x40)) & (~BIT3));
++
++ PlatformEFIOWrite1Byte(padapter, 0x04, PlatformEFIORead1Byte(padapter, 0x04) | BIT3);
++ PlatformEFIOWrite1Byte(padapter, 0x04, PlatformEFIORead1Byte(padapter, 0x04) & ~BIT3);
++
++ if (IS_HARDWARE_TYPE_8723DE(padapter))
++ PlatformEFIOWrite1Byte(padapter, 0x40, PlatformEFIORead1Byte(padapter, 0x40)|BIT3);
++
++ /* Retry Polling Process one more time */
++ pollingCount = 0;
++ flag = 1;
++ } else {
++ return _FALSE;
++ }
++ }
++ } while (!bPollingBit);
++
++ break;
++
++ case PWR_CMD_DELAY:
++ if (GET_PWR_CFG_VALUE(PwrCfgCmd) == PWRSEQ_DELAY_US)
++ rtw_udelay_os(GET_PWR_CFG_OFFSET(PwrCfgCmd));
++ else
++ rtw_udelay_os(GET_PWR_CFG_OFFSET(PwrCfgCmd) * 1000);
++ break;
++
++ case PWR_CMD_END:
++ /* When this command is parsed, end the process */
++ return _TRUE;
++ break;
++
++ default:
++ break;
++ }
++ }
++
++ AryIdx++;/* Add Array Index */
++ } while (1);
++
++ return _TRUE;
++}
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/led/hal_led.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/led/hal_led.c
+--- linux-5.11.4/3rdparty/rtl8812au/hal/led/hal_led.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/led/hal_led.c 2021-03-07 18:16:17.053956006 +0200
@@ -0,0 +1,254 @@
+/******************************************************************************
+ *
@@ -165231,11 +162294,9 @@ index 000000000..033d23b4c
+
+#endif /* CONFIG_RTW_LED */
+
-diff --git linux-5.8/3rdparty/rtl8812au/hal/led/hal_usb_led.c linux-5.8/3rdparty/rtl8812au/hal/led/hal_usb_led.c
-new file mode 100644
-index 000000000..80f7a393c
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/led/hal_usb_led.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/led/hal_usb_led.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/led/hal_usb_led.c
+--- linux-5.11.4/3rdparty/rtl8812au/hal/led/hal_usb_led.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/led/hal_usb_led.c 2021-03-07 18:16:17.053956006 +0200
@@ -0,0 +1,4291 @@
+/******************************************************************************
+ *
@@ -169528,11 +166589,9 @@ index 000000000..80f7a393c
+ ResetLedStatus(pLed);
+}
+#endif
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/ap_makefile.mk linux-5.8/3rdparty/rtl8812au/hal/phydm/ap_makefile.mk
-new file mode 100644
-index 000000000..def4490a1
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/ap_makefile.mk
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/ap_makefile.mk linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/ap_makefile.mk
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/ap_makefile.mk 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/ap_makefile.mk 2021-03-07 18:16:17.053956006 +0200
@@ -0,0 +1,188 @@
+
+_PHYDM_FILES :=\
@@ -169722,11 +166781,9 @@ index 000000000..def4490a1
+
+
+
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/halhwimg.h linux-5.8/3rdparty/rtl8812au/hal/phydm/halhwimg.h
-new file mode 100644
-index 000000000..2ae2aaa18
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/halhwimg.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/halhwimg.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/halhwimg.h
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/halhwimg.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/halhwimg.h 2021-03-07 18:16:17.053956006 +0200
@@ -0,0 +1,96 @@
+/******************************************************************************
+ *
@@ -169824,11 +166881,9 @@ index 000000000..2ae2aaa18
+#endif
+
+#endif /* @__INC_HW_IMG_H */
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/halphyrf_ap.c linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/halphyrf_ap.c
-new file mode 100644
-index 000000000..c4967e264
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/halphyrf_ap.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/halrf/halphyrf_ap.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/halrf/halphyrf_ap.c
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/halrf/halphyrf_ap.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/halrf/halphyrf_ap.c 2021-03-07 18:16:17.053956006 +0200
@@ -0,0 +1,1359 @@
+/******************************************************************************
+ *
@@ -171189,11 +168244,9 @@ index 000000000..c4967e264
+ odm_iq_calibrate(dm);
+#endif
+}
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/halphyrf_ap.h linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/halphyrf_ap.h
-new file mode 100644
-index 000000000..0c1cbb815
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/halphyrf_ap.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/halrf/halphyrf_ap.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/halrf/halphyrf_ap.h
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/halrf/halphyrf_ap.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/halrf/halphyrf_ap.h 2021-03-07 18:16:17.053956006 +0200
@@ -0,0 +1,139 @@
+/******************************************************************************
+ *
@@ -171334,11 +168387,9 @@ index 000000000..0c1cbb815
+void phydm_rf_watchdog(void *dm_void);
+
+#endif /*#ifndef __HALPHYRF_H__*/
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/halphyrf_ce.c linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/halphyrf_ce.c
-new file mode 100644
-index 000000000..c8753e500
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/halphyrf_ce.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/halrf/halphyrf_ce.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/halrf/halphyrf_ce.c
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/halrf/halphyrf_ce.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/halrf/halphyrf_ce.c 2021-03-07 18:16:17.054956052 +0200
@@ -0,0 +1,920 @@
+/******************************************************************************
+ *
@@ -172260,11 +169311,9 @@ index 000000000..c8753e500
+#endif
+#endif
+}
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/halphyrf_ce.h linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/halphyrf_ce.h
-new file mode 100644
-index 000000000..f0c444687
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/halphyrf_ce.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/halrf/halphyrf_ce.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/halrf/halphyrf_ce.h
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/halrf/halphyrf_ce.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/halrf/halphyrf_ce.h 2021-03-07 18:16:17.054956052 +0200
@@ -0,0 +1,114 @@
+/******************************************************************************
+ *
@@ -172380,11 +169429,9 @@ index 000000000..f0c444687
+void phydm_rf_watchdog(void *dm_void);
+
+#endif /*__HALPHYRF_H__*/
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/halphyrf_iot.c linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/halphyrf_iot.c
-new file mode 100644
-index 000000000..8145fc9bc
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/halphyrf_iot.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/halrf/halphyrf_iot.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/halrf/halphyrf_iot.c
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/halrf/halphyrf_iot.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/halrf/halphyrf_iot.c 2021-03-07 18:16:17.054956052 +0200
@@ -0,0 +1,528 @@
+/******************************************************************************
+ *
@@ -172914,11 +169961,9 @@ index 000000000..8145fc9bc
+
+ odm_txpowertracking_check(dm);
+}
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/halphyrf_iot.h linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/halphyrf_iot.h
-new file mode 100644
-index 000000000..7eba821be
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/halphyrf_iot.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/halrf/halphyrf_iot.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/halrf/halphyrf_iot.h
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/halrf/halphyrf_iot.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/halrf/halphyrf_iot.h 2021-03-07 18:16:17.054956052 +0200
@@ -0,0 +1,124 @@
+/******************************************************************************
+ *
@@ -173044,11 +170089,9 @@ index 000000000..7eba821be
+void phydm_rf_watchdog(void *dm_void);
+
+#endif /*#ifndef __HALPHYRF_H__*/
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/halphyrf_win.c linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/halphyrf_win.c
-new file mode 100644
-index 000000000..79702788a
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/halphyrf_win.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/halrf/halphyrf_win.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/halrf/halphyrf_win.c
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/halrf/halphyrf_win.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/halrf/halphyrf_win.c 2021-03-07 18:16:17.054956052 +0200
@@ -0,0 +1,841 @@
+/******************************************************************************
+ *
@@ -173891,11 +170934,9 @@ index 000000000..79702788a
+ odm_iq_calibrate(dm);
+#endif
+}
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/halphyrf_win.h linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/halphyrf_win.h
-new file mode 100644
-index 000000000..873948d45
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/halphyrf_win.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/halrf/halphyrf_win.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/halrf/halphyrf_win.h
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/halrf/halphyrf_win.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/halrf/halphyrf_win.h 2021-03-07 18:16:17.054956052 +0200
@@ -0,0 +1,125 @@
+/******************************************************************************
+ *
@@ -174022,11 +171063,9 @@ index 000000000..873948d45
+void phydm_rf_watchdog(struct dm_struct *dm);
+
+#endif /*#ifndef __HALPHYRF_H__*/
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/halrf.c linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/halrf.c
-new file mode 100644
-index 000000000..32fd1f3db
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/halrf.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/halrf/halrf.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/halrf/halrf.c
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/halrf/halrf.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/halrf/halrf.c 2021-03-07 18:16:17.054956052 +0200
@@ -0,0 +1,2395 @@
+/******************************************************************************
+ *
@@ -176423,11 +173462,544 @@ index 000000000..32fd1f3db
+#endif
+}
+
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/halrf.h linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/halrf.h
-new file mode 100644
-index 000000000..8a45aae32
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/halrf.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/halrf/halrf_debug.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/halrf/halrf_debug.c
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/halrf/halrf_debug.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/halrf/halrf_debug.c 2021-03-07 18:16:17.055956100 +0200
+@@ -0,0 +1,267 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * The full GNU General Public License is included in this distribution in the
++ * file called LICENSE.
++ *
++ * Contact Information:
++ * wlanfae
++ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
++ * Hsinchu 300, Taiwan.
++ *
++ * Larry Finger
++ *
++ *****************************************************************************/
++
++/*@************************************************************
++ * include files
++ * ************************************************************
++ */
++
++#include "mp_precomp.h"
++#include "phydm_precomp.h"
++
++void halrf_basic_profile(void *dm_void, u32 *_used, char *output, u32 *_out_len)
++{
++#ifdef CONFIG_PHYDM_DEBUG_FUNCTION
++ struct dm_struct *dm = (struct dm_struct *)dm_void;
++ u32 used = *_used;
++ u32 out_len = *_out_len;
++
++ /* HAL RF version List */
++ PDM_SNPF(out_len, used, output + used, out_len - used, "%-35s\n",
++ "% HAL RF version %");
++ PDM_SNPF(out_len, used, output + used, out_len - used, " %-35s: %s\n",
++ "Power Tracking", HALRF_POWRTRACKING_VER);
++ PDM_SNPF(out_len, used, output + used, out_len - used,
++ " %-35s: %s %s\n", "IQK",
++ (dm->fw_offload_ability & PHYDM_RF_IQK_OFFLOAD) ? "FW" :
++ HALRF_IQK_VER,
++ (halrf_match_iqk_version(dm_void)) ? "(match)" : "(mismatch)");
++
++ PDM_SNPF(out_len, used, output + used, out_len - used, " %-35s: %s\n",
++ "LCK", HALRF_LCK_VER);
++ PDM_SNPF(out_len, used, output + used, out_len - used, " %-35s: %s\n",
++ "DPK", HALRF_DPK_VER);
++ PDM_SNPF(out_len, used, output + used, out_len - used, " %-35s: %s\n",
++ "KFREE", HALRF_KFREE_VER);
++ PDM_SNPF(out_len, used, output + used, out_len - used, " %-35s: %s\n",
++ "TX 2G Current Calibration", HALRF_PABIASK_VER);
++ PDM_SNPF(out_len, used, output + used, out_len - used, " %-35s: %s\n",
++ "RFK Init. Parameter", HALRF_RFK_INIT_VER);
++
++ *_used = used;
++ *_out_len = out_len;
++#endif
++}
++
++void halrf_debug_trace(void *dm_void, char input[][16], u32 *_used,
++ char *output, u32 *_out_len)
++{
++ struct dm_struct *dm = (struct dm_struct *)dm_void;
++ struct _hal_rf_ *rf = &dm->rf_table;
++ u32 one = 1;
++ u32 used = *_used;
++ u32 out_len = *_out_len;
++ u32 rf_var[10] = {0};
++ u8 i;
++
++ for (i = 0; i < 5; i++)
++ if (input[i + 1])
++ PHYDM_SSCANF(input[i + 2], DCMD_DECIMAL, &rf_var[i]);
++
++ if (rf_var[0] == 100) {
++ PDM_SNPF(out_len, used, output + used, out_len - used,
++ "\n[DBG MSG] RF Selection\n");
++ PDM_SNPF(out_len, used, output + used, out_len - used,
++ "00. (( %s ))TX_PWR_TRACK\n",
++ ((rf->rf_dbg_comp & DBG_RF_TX_PWR_TRACK) ? ("V") :
++ (".")));
++ PDM_SNPF(out_len, used, output + used, out_len - used,
++ "01. (( %s ))IQK\n",
++ ((rf->rf_dbg_comp & DBG_RF_IQK) ? ("V") : (".")));
++ PDM_SNPF(out_len, used, output + used, out_len - used,
++ "02. (( %s ))LCK\n",
++ ((rf->rf_dbg_comp & DBG_RF_LCK) ? ("V") : (".")));
++ PDM_SNPF(out_len, used, output + used, out_len - used,
++ "03. (( %s ))DPK\n",
++ ((rf->rf_dbg_comp & DBG_RF_DPK) ? ("V") : (".")));
++ PDM_SNPF(out_len, used, output + used, out_len - used,
++ "04. (( %s ))TXGAPK\n",
++ ((rf->rf_dbg_comp & DBG_RF_TXGAPK) ? ("V") : (".")));
++ PDM_SNPF(out_len, used, output + used, out_len - used,
++ "29. (( %s ))MP\n",
++ ((rf->rf_dbg_comp & DBG_RF_MP) ? ("V") : (".")));
++ PDM_SNPF(out_len, used, output + used, out_len - used,
++ "30. (( %s ))TMP\n",
++ ((rf->rf_dbg_comp & DBG_RF_TMP) ? ("V") : (".")));
++ PDM_SNPF(out_len, used, output + used, out_len - used,
++ "31. (( %s ))INIT\n",
++ ((rf->rf_dbg_comp & DBG_RF_INIT) ? ("V") : (".")));
++
++ } else if (rf_var[0] == 101) {
++ rf->rf_dbg_comp = 0;
++ PDM_SNPF(out_len, used, output + used, out_len - used,
++ "Disable all DBG COMP\n");
++ } else {
++ if (rf_var[1] == 1) /*enable*/
++ rf->rf_dbg_comp |= (one << rf_var[0]);
++ else if (rf_var[1] == 2) /*disable*/
++ rf->rf_dbg_comp &= ~(one << rf_var[0]);
++ }
++ PDM_SNPF(out_len, used, output + used, out_len - used,
++ "\nCurr-RF_Dbg_Comp = 0x%x\n", rf->rf_dbg_comp);
++
++ *_used = used;
++ *_out_len = out_len;
++}
++
++struct halrf_command {
++ char name[16];
++ u8 id;
++};
++
++enum halrf_CMD_ID {
++ HALRF_HELP,
++ HALRF_SUPPORTABILITY,
++ HALRF_DBG_COMP,
++ HALRF_PROFILE,
++ HALRF_IQK_INFO,
++ HALRF_IQK,
++ HALRF_IQK_DEBUG,
++ HAL_BAND_SHIFT,
++};
++
++struct halrf_command halrf_cmd_ary[] = {
++ {"-h", HALRF_HELP},
++ {"ability", HALRF_SUPPORTABILITY},
++ {"dbg", HALRF_DBG_COMP},
++ {"profile", HALRF_PROFILE},
++ {"iqk_info", HALRF_IQK_INFO},
++ {"iqk", HALRF_IQK},
++ {"iqk_dbg", HALRF_IQK_DEBUG},
++ {"band_shift", HAL_BAND_SHIFT},
++};
++
++void halrf_cmd_parser(void *dm_void, char input[][16], u32 *_used, char *output,
++ u32 *_out_len, u32 input_num)
++{
++ struct dm_struct *dm = (struct dm_struct *)dm_void;
++#ifdef CONFIG_PHYDM_DEBUG_FUNCTION
++ u8 id = 0;
++ u32 rf_var[10] = {0};
++ u32 i, input_idx = 0;
++ u32 halrf_ary_size =
++ sizeof(halrf_cmd_ary) / sizeof(struct halrf_command);
++ u32 used = *_used;
++ u32 out_len = *_out_len;
++
++ /* Parsing Cmd ID */
++ for (i = 0; i < halrf_ary_size; i++) {
++ if (strcmp(halrf_cmd_ary[i].name, input[1]) == 0) {
++ id = halrf_cmd_ary[i].id;
++ break;
++ }
++ }
++
++ if (i == halrf_ary_size) {
++ PDM_SNPF(out_len, used, output + used, out_len - used,
++ "RF Cmd not found\n");
++ return;
++ }
++
++ switch (id) {
++ case HALRF_HELP:
++ PDM_SNPF(out_len, used, output + used, out_len - used,
++ "RF cmd ==>\n");
++
++ for (i = 0; i < halrf_ary_size - 1; i++) {
++ PDM_SNPF(out_len, used, output + used, out_len - used,
++ " %-5d: %s\n", i, halrf_cmd_ary[i + 1].name);
++ }
++ break;
++ case HALRF_SUPPORTABILITY:
++ halrf_support_ability_debug(dm, &input[0], &used, output,
++ &out_len);
++ break;
++ case HAL_BAND_SHIFT:
++ halrf_support_band_shift_debug(dm, &input[0], &used, output,
++ &out_len);
++ break;
++ case HALRF_DBG_COMP:
++ halrf_debug_trace(dm, &input[0], &used, output, &out_len);
++ break;
++ case HALRF_PROFILE:
++ halrf_basic_profile(dm, &used, output, &out_len);
++ break;
++ case HALRF_IQK_INFO:
++#if (RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1)
++ halrf_iqk_info_dump(dm, &used, output, &out_len);
++#endif
++ break;
++ case HALRF_IQK:
++ PDM_SNPF(out_len, used, output + used, out_len - used,
++ "TRX IQK Trigger\n");
++ halrf_iqk_trigger(dm, false);
++#if (RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1)
++ halrf_iqk_info_dump(dm, &used, output, &out_len);
++#endif
++ break;
++ case HALRF_IQK_DEBUG:
++
++ for (i = 0; i < 5; i++) {
++ if (input[i + 1]) {
++ PHYDM_SSCANF(input[i + 2], DCMD_HEX,
++ &rf_var[i]);
++ input_idx++;
++ }
++ }
++
++ if (input_idx >= 1) {
++#if (RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1)
++ if (dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8821C))
++ halrf_iqk_debug(dm, (u32 *)rf_var, &used,
++ output, &out_len);
++#endif
++ }
++ break;
++ default:
++ break;
++ }
++
++ *_used = used;
++ *_out_len = out_len;
++#endif
++}
++
++void halrf_init_debug_setting(void *dm_void)
++{
++ struct dm_struct *dm = (struct dm_struct *)dm_void;
++ struct _hal_rf_ *rf = &dm->rf_table;
++
++ rf->rf_dbg_comp =
++#if DBG
++#if 0
++ /*DBG_RF_TX_PWR_TRACK |*/
++ /*DBG_RF_IQK | */
++ /*DBG_RF_LCK | */
++ /*DBG_RF_DPK | */
++ /*DBG_RF_DACK | */
++ /*DBG_RF_TXGAPK | */
++ /*DBG_RF_MP | */
++ /*DBG_RF_TMP | */
++ /*DBG_RF_INIT | */
++#endif
++#endif
++ 0;
++}
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/halrf/halrf_debug.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/halrf/halrf_debug.h
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/halrf/halrf_debug.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/halrf/halrf_debug.h 2021-03-07 18:16:17.055956100 +0200
+@@ -0,0 +1,123 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * The full GNU General Public License is included in this distribution in the
++ * file called LICENSE.
++ *
++ * Contact Information:
++ * wlanfae
++ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
++ * Hsinchu 300, Taiwan.
++ *
++ * Larry Finger
++ *
++ *****************************************************************************/
++
++#ifndef __HALRF_DEBUG_H__
++#define __HALRF_DEBUG_H__
++
++/*@============================================================*/
++/*@include files*/
++/*@============================================================*/
++
++/*@============================================================*/
++/*@Definition */
++/*@============================================================*/
++
++#if DBG
++
++#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
++#define RF_DBG(dm, comp, fmt, args...) \
++ do { \
++ if ((comp) & dm->rf_table.rf_dbg_comp) { \
++ pr_debug("[RF] "); \
++ RT_PRINTK(fmt, ##args); \
++ } \
++ } while (0)
++
++#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++
++static __inline void RF_DBG(PDM_ODM_T dm, int comp, char *fmt, ...)
++{
++ RT_STATUS rt_status;
++ va_list args;
++ char buf[PRINT_MAX_SIZE] = {0};
++
++ if ((comp & dm->rf_table.rf_dbg_comp) == 0)
++ return;
++
++ if (fmt == NULL)
++ return;
++
++ va_start(args, fmt);
++ rt_status = (RT_STATUS)RtlStringCbVPrintfA(buf, PRINT_MAX_SIZE, fmt, args);
++ va_end(args);
++
++ if (rt_status != RT_STATUS_SUCCESS) {
++ DbgPrint("Failed (%d) to print message to buffer\n", rt_status);
++ return;
++ }
++
++ DbgPrint("[RF] %s", buf);
++}
++
++#elif (DM_ODM_SUPPORT_TYPE == ODM_IOT)
++
++#define RF_DBG(dm, comp, fmt, args...) \
++ do { \
++ if ((comp) & dm->rf_table.rf_dbg_comp) { \
++ RT_DEBUG(COMP_PHYDM, DBG_DMESG, "[RF] " fmt, ##args); \
++ } \
++ } while (0)
++
++#else
++#define RF_DBG(dm, comp, fmt, args...) \
++ do { \
++ struct dm_struct *__dm = dm; \
++ if ((comp) & __dm->rf_table.rf_dbg_comp) { \
++ RT_TRACE(((struct rtl_priv *)__dm->adapter), \
++ COMP_PHYDM, DBG_DMESG, "[RF] " fmt, ##args); \
++ } \
++ } while (0)
++#endif
++
++#else /*#if DBG*/
++
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++static __inline void RF_DBG(struct dm_struct *dm, int comp, char *fmt, ...)
++{
++}
++#else
++#define RF_DBG(dm, comp, fmt, args...)
++#endif
++
++#endif /*#if DBG*/
++
++/*@============================================================*/
++/*@ enumeration */
++/*@============================================================*/
++
++/*@============================================================*/
++/*@ structure */
++/*@============================================================*/
++
++/*@============================================================*/
++/*@ function prototype */
++/*@============================================================*/
++
++void halrf_cmd_parser(void *dm_void, char input[][16], u32 *_used, char *output,
++ u32 *_out_len, u32 input_num);
++
++void halrf_init_debug_setting(void *dm_void);
++
++#endif /*__HALRF_H__*/
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/halrf/halrf_dpk.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/halrf/halrf_dpk.h
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/halrf/halrf_dpk.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/halrf/halrf_dpk.h 2021-03-07 18:16:17.055956100 +0200
+@@ -0,0 +1,86 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * The full GNU General Public License is included in this distribution in the
++ * file called LICENSE.
++ *
++ * Contact Information:
++ * wlanfae
++ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
++ * Hsinchu 300, Taiwan.
++ *
++ * Larry Finger
++ *
++ *****************************************************************************/
++
++#ifndef __HALRF_DPK_H__
++#define __HALRF_DPK_H__
++
++/*@--------------------------Define Parameters-------------------------------*/
++#define GAIN_LOSS 1
++#define DO_DPK 2
++#define DPK_ON 3
++#define DPK_LOK 4
++#define DPK_TXK 5
++
++#define DAGC 4
++#define LOSS_CHK 0
++#define GAIN_CHK 1
++#define PAS_READ 2
++#define AVG_THERMAL_NUM 8
++#define AVG_THERMAL_NUM_DPK 8
++#define THERMAL_DPK_AVG_NUM 4
++
++/*@---------------------------End Define Parameters---------------------------*/
++
++struct dm_dpk_info {
++
++ boolean is_dpk_enable;
++ boolean is_dpk_pwr_on;
++ boolean is_dpk_by_channel;
++ u16 dpk_path_ok;
++ /*@BIT(15)~BIT(12) : 5G reserved, BIT(11)~BIT(8) 5G_S3~5G_S0*/
++ /*@BIT(7)~BIT(4) : 2G reserved, BIT(3)~BIT(0) 2G_S3~2G_S0*/
++ u8 thermal_dpk;
++ u8 thermal_dpk_avg[AVG_THERMAL_NUM_DPK];
++ u8 thermal_dpk_avg_index;
++
++#if (RTL8822C_SUPPORT == 1)
++ u8 result[2][1]; /*path/group*/
++ u8 tx_agc[2][1]; /*path/group*/
++ u32 coef[2][1][20]; /*path/group/MDPD coefficient*/
++#endif
++
++#if (RTL8198F_SUPPORT == 1 || RTL8192F_SUPPORT == 1 || RTL8197F_SUPPORT == 1)
++ /*2G DPK data*/
++ u8 dpk_result[4][3]; /*path/group*/
++ u8 pwsf_2g[4][3]; /*path/group*/
++ u32 lut_2g_even[4][3][64]; /*path/group/LUT data*/
++ u32 lut_2g_odd[4][3][64]; /*path/group/LUT data*/
++#endif
++
++#if (RTL8195B_SUPPORT == 1)
++ /*2G DPK data*/
++ u8 dpk_2g_result[1][3]; /*path/group*/
++ u8 pwsf_2g[1][3]; /*path/group*/
++ u32 lut_2g_even[1][3][16]; /*path/group/LUT data*/
++ u32 lut_2g_odd[1][3][16]; /*path/group/LUT data*/
++ /*5G DPK data*/
++ u8 dpk_5g_result[1][6]; /*path/group*/
++ u8 pwsf_5g[1][6]; /*path/group*/
++ u32 lut_5g_even[1][6][16]; /*path/group/LUT data*/
++ u32 lut_5g_odd[1][6][16]; /*path/group/LUT data*/
++#endif
++};
++
++#endif /*__HALRF_DPK_H__*/
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/halrf/halrf_features.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/halrf/halrf_features.h
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/halrf/halrf_features.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/halrf/halrf_features.h 2021-03-07 18:16:17.055956100 +0200
+@@ -0,0 +1,43 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * The full GNU General Public License is included in this distribution in the
++ * file called LICENSE.
++ *
++ * Contact Information:
++ * wlanfae
++ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
++ * Hsinchu 300, Taiwan.
++ *
++ * Larry Finger
++ *
++ *****************************************************************************/
++
++#ifndef __HALRF_FEATURES_H__
++#define __HALRF_FEATURES_H__
++
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++
++#define CONFIG_HALRF_POWERTRACKING 1
++
++#elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
++
++#define CONFIG_HALRF_POWERTRACKING 1
++
++#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
++
++#define CONFIG_HALRF_POWERTRACKING 1
++
++#endif
++
++#endif /*#ifndef __HALRF_FEATURES_H__*/
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/halrf/halrf.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/halrf/halrf.h
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/halrf/halrf.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/halrf/halrf.h 2021-03-07 18:16:17.054956052 +0200
@@ -0,0 +1,573 @@
+/******************************************************************************
+ *
@@ -177002,554 +174574,9 @@ index 000000000..8a45aae32
+u32 halrf_query_tssi_value(void *dm_void);
+
+#endif /*__HALRF_H__*/
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/halrf_debug.c linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/halrf_debug.c
-new file mode 100644
-index 000000000..85a7cb22b
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/halrf_debug.c
-@@ -0,0 +1,267 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ * The full GNU General Public License is included in this distribution in the
-+ * file called LICENSE.
-+ *
-+ * Contact Information:
-+ * wlanfae
-+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
-+ * Hsinchu 300, Taiwan.
-+ *
-+ * Larry Finger
-+ *
-+ *****************************************************************************/
-+
-+/*@************************************************************
-+ * include files
-+ * ************************************************************
-+ */
-+
-+#include "mp_precomp.h"
-+#include "phydm_precomp.h"
-+
-+void halrf_basic_profile(void *dm_void, u32 *_used, char *output, u32 *_out_len)
-+{
-+#ifdef CONFIG_PHYDM_DEBUG_FUNCTION
-+ struct dm_struct *dm = (struct dm_struct *)dm_void;
-+ u32 used = *_used;
-+ u32 out_len = *_out_len;
-+
-+ /* HAL RF version List */
-+ PDM_SNPF(out_len, used, output + used, out_len - used, "%-35s\n",
-+ "% HAL RF version %");
-+ PDM_SNPF(out_len, used, output + used, out_len - used, " %-35s: %s\n",
-+ "Power Tracking", HALRF_POWRTRACKING_VER);
-+ PDM_SNPF(out_len, used, output + used, out_len - used,
-+ " %-35s: %s %s\n", "IQK",
-+ (dm->fw_offload_ability & PHYDM_RF_IQK_OFFLOAD) ? "FW" :
-+ HALRF_IQK_VER,
-+ (halrf_match_iqk_version(dm_void)) ? "(match)" : "(mismatch)");
-+
-+ PDM_SNPF(out_len, used, output + used, out_len - used, " %-35s: %s\n",
-+ "LCK", HALRF_LCK_VER);
-+ PDM_SNPF(out_len, used, output + used, out_len - used, " %-35s: %s\n",
-+ "DPK", HALRF_DPK_VER);
-+ PDM_SNPF(out_len, used, output + used, out_len - used, " %-35s: %s\n",
-+ "KFREE", HALRF_KFREE_VER);
-+ PDM_SNPF(out_len, used, output + used, out_len - used, " %-35s: %s\n",
-+ "TX 2G Current Calibration", HALRF_PABIASK_VER);
-+ PDM_SNPF(out_len, used, output + used, out_len - used, " %-35s: %s\n",
-+ "RFK Init. Parameter", HALRF_RFK_INIT_VER);
-+
-+ *_used = used;
-+ *_out_len = out_len;
-+#endif
-+}
-+
-+void halrf_debug_trace(void *dm_void, char input[][16], u32 *_used,
-+ char *output, u32 *_out_len)
-+{
-+ struct dm_struct *dm = (struct dm_struct *)dm_void;
-+ struct _hal_rf_ *rf = &dm->rf_table;
-+ u32 one = 1;
-+ u32 used = *_used;
-+ u32 out_len = *_out_len;
-+ u32 rf_var[10] = {0};
-+ u8 i;
-+
-+ for (i = 0; i < 5; i++)
-+ if (input[i + 1])
-+ PHYDM_SSCANF(input[i + 2], DCMD_DECIMAL, &rf_var[i]);
-+
-+ if (rf_var[0] == 100) {
-+ PDM_SNPF(out_len, used, output + used, out_len - used,
-+ "\n[DBG MSG] RF Selection\n");
-+ PDM_SNPF(out_len, used, output + used, out_len - used,
-+ "00. (( %s ))TX_PWR_TRACK\n",
-+ ((rf->rf_dbg_comp & DBG_RF_TX_PWR_TRACK) ? ("V") :
-+ (".")));
-+ PDM_SNPF(out_len, used, output + used, out_len - used,
-+ "01. (( %s ))IQK\n",
-+ ((rf->rf_dbg_comp & DBG_RF_IQK) ? ("V") : (".")));
-+ PDM_SNPF(out_len, used, output + used, out_len - used,
-+ "02. (( %s ))LCK\n",
-+ ((rf->rf_dbg_comp & DBG_RF_LCK) ? ("V") : (".")));
-+ PDM_SNPF(out_len, used, output + used, out_len - used,
-+ "03. (( %s ))DPK\n",
-+ ((rf->rf_dbg_comp & DBG_RF_DPK) ? ("V") : (".")));
-+ PDM_SNPF(out_len, used, output + used, out_len - used,
-+ "04. (( %s ))TXGAPK\n",
-+ ((rf->rf_dbg_comp & DBG_RF_TXGAPK) ? ("V") : (".")));
-+ PDM_SNPF(out_len, used, output + used, out_len - used,
-+ "29. (( %s ))MP\n",
-+ ((rf->rf_dbg_comp & DBG_RF_MP) ? ("V") : (".")));
-+ PDM_SNPF(out_len, used, output + used, out_len - used,
-+ "30. (( %s ))TMP\n",
-+ ((rf->rf_dbg_comp & DBG_RF_TMP) ? ("V") : (".")));
-+ PDM_SNPF(out_len, used, output + used, out_len - used,
-+ "31. (( %s ))INIT\n",
-+ ((rf->rf_dbg_comp & DBG_RF_INIT) ? ("V") : (".")));
-+
-+ } else if (rf_var[0] == 101) {
-+ rf->rf_dbg_comp = 0;
-+ PDM_SNPF(out_len, used, output + used, out_len - used,
-+ "Disable all DBG COMP\n");
-+ } else {
-+ if (rf_var[1] == 1) /*enable*/
-+ rf->rf_dbg_comp |= (one << rf_var[0]);
-+ else if (rf_var[1] == 2) /*disable*/
-+ rf->rf_dbg_comp &= ~(one << rf_var[0]);
-+ }
-+ PDM_SNPF(out_len, used, output + used, out_len - used,
-+ "\nCurr-RF_Dbg_Comp = 0x%x\n", rf->rf_dbg_comp);
-+
-+ *_used = used;
-+ *_out_len = out_len;
-+}
-+
-+struct halrf_command {
-+ char name[16];
-+ u8 id;
-+};
-+
-+enum halrf_CMD_ID {
-+ HALRF_HELP,
-+ HALRF_SUPPORTABILITY,
-+ HALRF_DBG_COMP,
-+ HALRF_PROFILE,
-+ HALRF_IQK_INFO,
-+ HALRF_IQK,
-+ HALRF_IQK_DEBUG,
-+ HAL_BAND_SHIFT,
-+};
-+
-+struct halrf_command halrf_cmd_ary[] = {
-+ {"-h", HALRF_HELP},
-+ {"ability", HALRF_SUPPORTABILITY},
-+ {"dbg", HALRF_DBG_COMP},
-+ {"profile", HALRF_PROFILE},
-+ {"iqk_info", HALRF_IQK_INFO},
-+ {"iqk", HALRF_IQK},
-+ {"iqk_dbg", HALRF_IQK_DEBUG},
-+ {"band_shift", HAL_BAND_SHIFT},
-+};
-+
-+void halrf_cmd_parser(void *dm_void, char input[][16], u32 *_used, char *output,
-+ u32 *_out_len, u32 input_num)
-+{
-+ struct dm_struct *dm = (struct dm_struct *)dm_void;
-+#ifdef CONFIG_PHYDM_DEBUG_FUNCTION
-+ u8 id = 0;
-+ u32 rf_var[10] = {0};
-+ u32 i, input_idx = 0;
-+ u32 halrf_ary_size =
-+ sizeof(halrf_cmd_ary) / sizeof(struct halrf_command);
-+ u32 used = *_used;
-+ u32 out_len = *_out_len;
-+
-+ /* Parsing Cmd ID */
-+ for (i = 0; i < halrf_ary_size; i++) {
-+ if (strcmp(halrf_cmd_ary[i].name, input[1]) == 0) {
-+ id = halrf_cmd_ary[i].id;
-+ break;
-+ }
-+ }
-+
-+ if (i == halrf_ary_size) {
-+ PDM_SNPF(out_len, used, output + used, out_len - used,
-+ "RF Cmd not found\n");
-+ return;
-+ }
-+
-+ switch (id) {
-+ case HALRF_HELP:
-+ PDM_SNPF(out_len, used, output + used, out_len - used,
-+ "RF cmd ==>\n");
-+
-+ for (i = 0; i < halrf_ary_size - 1; i++) {
-+ PDM_SNPF(out_len, used, output + used, out_len - used,
-+ " %-5d: %s\n", i, halrf_cmd_ary[i + 1].name);
-+ }
-+ break;
-+ case HALRF_SUPPORTABILITY:
-+ halrf_support_ability_debug(dm, &input[0], &used, output,
-+ &out_len);
-+ break;
-+ case HAL_BAND_SHIFT:
-+ halrf_support_band_shift_debug(dm, &input[0], &used, output,
-+ &out_len);
-+ break;
-+ case HALRF_DBG_COMP:
-+ halrf_debug_trace(dm, &input[0], &used, output, &out_len);
-+ break;
-+ case HALRF_PROFILE:
-+ halrf_basic_profile(dm, &used, output, &out_len);
-+ break;
-+ case HALRF_IQK_INFO:
-+#if (RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1)
-+ halrf_iqk_info_dump(dm, &used, output, &out_len);
-+#endif
-+ break;
-+ case HALRF_IQK:
-+ PDM_SNPF(out_len, used, output + used, out_len - used,
-+ "TRX IQK Trigger\n");
-+ halrf_iqk_trigger(dm, false);
-+#if (RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1)
-+ halrf_iqk_info_dump(dm, &used, output, &out_len);
-+#endif
-+ break;
-+ case HALRF_IQK_DEBUG:
-+
-+ for (i = 0; i < 5; i++) {
-+ if (input[i + 1]) {
-+ PHYDM_SSCANF(input[i + 2], DCMD_HEX,
-+ &rf_var[i]);
-+ input_idx++;
-+ }
-+ }
-+
-+ if (input_idx >= 1) {
-+#if (RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1)
-+ if (dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8821C))
-+ halrf_iqk_debug(dm, (u32 *)rf_var, &used,
-+ output, &out_len);
-+#endif
-+ }
-+ break;
-+ default:
-+ break;
-+ }
-+
-+ *_used = used;
-+ *_out_len = out_len;
-+#endif
-+}
-+
-+void halrf_init_debug_setting(void *dm_void)
-+{
-+ struct dm_struct *dm = (struct dm_struct *)dm_void;
-+ struct _hal_rf_ *rf = &dm->rf_table;
-+
-+ rf->rf_dbg_comp =
-+#if DBG
-+#if 0
-+ /*DBG_RF_TX_PWR_TRACK |*/
-+ /*DBG_RF_IQK | */
-+ /*DBG_RF_LCK | */
-+ /*DBG_RF_DPK | */
-+ /*DBG_RF_DACK | */
-+ /*DBG_RF_TXGAPK | */
-+ /*DBG_RF_MP | */
-+ /*DBG_RF_TMP | */
-+ /*DBG_RF_INIT | */
-+#endif
-+#endif
-+ 0;
-+}
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/halrf_debug.h linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/halrf_debug.h
-new file mode 100644
-index 000000000..ff1ff96d2
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/halrf_debug.h
-@@ -0,0 +1,123 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ * The full GNU General Public License is included in this distribution in the
-+ * file called LICENSE.
-+ *
-+ * Contact Information:
-+ * wlanfae
-+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
-+ * Hsinchu 300, Taiwan.
-+ *
-+ * Larry Finger
-+ *
-+ *****************************************************************************/
-+
-+#ifndef __HALRF_DEBUG_H__
-+#define __HALRF_DEBUG_H__
-+
-+/*@============================================================*/
-+/*@include files*/
-+/*@============================================================*/
-+
-+/*@============================================================*/
-+/*@Definition */
-+/*@============================================================*/
-+
-+#if DBG
-+
-+#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
-+#define RF_DBG(dm, comp, fmt, args...) \
-+ do { \
-+ if ((comp) & dm->rf_table.rf_dbg_comp) { \
-+ pr_debug("[RF] "); \
-+ RT_PRINTK(fmt, ##args); \
-+ } \
-+ } while (0)
-+
-+#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+
-+static __inline void RF_DBG(PDM_ODM_T dm, int comp, char *fmt, ...)
-+{
-+ RT_STATUS rt_status;
-+ va_list args;
-+ char buf[PRINT_MAX_SIZE] = {0};
-+
-+ if ((comp & dm->rf_table.rf_dbg_comp) == 0)
-+ return;
-+
-+ if (fmt == NULL)
-+ return;
-+
-+ va_start(args, fmt);
-+ rt_status = (RT_STATUS)RtlStringCbVPrintfA(buf, PRINT_MAX_SIZE, fmt, args);
-+ va_end(args);
-+
-+ if (rt_status != RT_STATUS_SUCCESS) {
-+ DbgPrint("Failed (%d) to print message to buffer\n", rt_status);
-+ return;
-+ }
-+
-+ DbgPrint("[RF] %s", buf);
-+}
-+
-+#elif (DM_ODM_SUPPORT_TYPE == ODM_IOT)
-+
-+#define RF_DBG(dm, comp, fmt, args...) \
-+ do { \
-+ if ((comp) & dm->rf_table.rf_dbg_comp) { \
-+ RT_DEBUG(COMP_PHYDM, DBG_DMESG, "[RF] " fmt, ##args); \
-+ } \
-+ } while (0)
-+
-+#else
-+#define RF_DBG(dm, comp, fmt, args...) \
-+ do { \
-+ struct dm_struct *__dm = dm; \
-+ if ((comp) & __dm->rf_table.rf_dbg_comp) { \
-+ RT_TRACE(((struct rtl_priv *)__dm->adapter), \
-+ COMP_PHYDM, DBG_DMESG, "[RF] " fmt, ##args); \
-+ } \
-+ } while (0)
-+#endif
-+
-+#else /*#if DBG*/
-+
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+static __inline void RF_DBG(struct dm_struct *dm, int comp, char *fmt, ...)
-+{
-+}
-+#else
-+#define RF_DBG(dm, comp, fmt, args...)
-+#endif
-+
-+#endif /*#if DBG*/
-+
-+/*@============================================================*/
-+/*@ enumeration */
-+/*@============================================================*/
-+
-+/*@============================================================*/
-+/*@ structure */
-+/*@============================================================*/
-+
-+/*@============================================================*/
-+/*@ function prototype */
-+/*@============================================================*/
-+
-+void halrf_cmd_parser(void *dm_void, char input[][16], u32 *_used, char *output,
-+ u32 *_out_len, u32 input_num);
-+
-+void halrf_init_debug_setting(void *dm_void);
-+
-+#endif /*__HALRF_H__*/
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/halrf_dpk.h linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/halrf_dpk.h
-new file mode 100644
-index 000000000..c9efc7e93
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/halrf_dpk.h
-@@ -0,0 +1,86 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ * The full GNU General Public License is included in this distribution in the
-+ * file called LICENSE.
-+ *
-+ * Contact Information:
-+ * wlanfae
-+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
-+ * Hsinchu 300, Taiwan.
-+ *
-+ * Larry Finger
-+ *
-+ *****************************************************************************/
-+
-+#ifndef __HALRF_DPK_H__
-+#define __HALRF_DPK_H__
-+
-+/*@--------------------------Define Parameters-------------------------------*/
-+#define GAIN_LOSS 1
-+#define DO_DPK 2
-+#define DPK_ON 3
-+#define DPK_LOK 4
-+#define DPK_TXK 5
-+
-+#define DAGC 4
-+#define LOSS_CHK 0
-+#define GAIN_CHK 1
-+#define PAS_READ 2
-+#define AVG_THERMAL_NUM 8
-+#define AVG_THERMAL_NUM_DPK 8
-+#define THERMAL_DPK_AVG_NUM 4
-+
-+/*@---------------------------End Define Parameters---------------------------*/
-+
-+struct dm_dpk_info {
-+
-+ boolean is_dpk_enable;
-+ boolean is_dpk_pwr_on;
-+ boolean is_dpk_by_channel;
-+ u16 dpk_path_ok;
-+ /*@BIT(15)~BIT(12) : 5G reserved, BIT(11)~BIT(8) 5G_S3~5G_S0*/
-+ /*@BIT(7)~BIT(4) : 2G reserved, BIT(3)~BIT(0) 2G_S3~2G_S0*/
-+ u8 thermal_dpk;
-+ u8 thermal_dpk_avg[AVG_THERMAL_NUM_DPK];
-+ u8 thermal_dpk_avg_index;
-+
-+#if (RTL8822C_SUPPORT == 1)
-+ u8 result[2][1]; /*path/group*/
-+ u8 tx_agc[2][1]; /*path/group*/
-+ u32 coef[2][1][20]; /*path/group/MDPD coefficient*/
-+#endif
-+
-+#if (RTL8198F_SUPPORT == 1 || RTL8192F_SUPPORT == 1 || RTL8197F_SUPPORT == 1)
-+ /*2G DPK data*/
-+ u8 dpk_result[4][3]; /*path/group*/
-+ u8 pwsf_2g[4][3]; /*path/group*/
-+ u32 lut_2g_even[4][3][64]; /*path/group/LUT data*/
-+ u32 lut_2g_odd[4][3][64]; /*path/group/LUT data*/
-+#endif
-+
-+#if (RTL8195B_SUPPORT == 1)
-+ /*2G DPK data*/
-+ u8 dpk_2g_result[1][3]; /*path/group*/
-+ u8 pwsf_2g[1][3]; /*path/group*/
-+ u32 lut_2g_even[1][3][16]; /*path/group/LUT data*/
-+ u32 lut_2g_odd[1][3][16]; /*path/group/LUT data*/
-+ /*5G DPK data*/
-+ u8 dpk_5g_result[1][6]; /*path/group*/
-+ u8 pwsf_5g[1][6]; /*path/group*/
-+ u32 lut_5g_even[1][6][16]; /*path/group/LUT data*/
-+ u32 lut_5g_odd[1][6][16]; /*path/group/LUT data*/
-+#endif
-+};
-+
-+#endif /*__HALRF_DPK_H__*/
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/halrf_features.h linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/halrf_features.h
-new file mode 100644
-index 000000000..da97614be
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/halrf_features.h
-@@ -0,0 +1,43 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ * The full GNU General Public License is included in this distribution in the
-+ * file called LICENSE.
-+ *
-+ * Contact Information:
-+ * wlanfae
-+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
-+ * Hsinchu 300, Taiwan.
-+ *
-+ * Larry Finger
-+ *
-+ *****************************************************************************/
-+
-+#ifndef __HALRF_FEATURES_H__
-+#define __HALRF_FEATURES_H__
-+
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+
-+#define CONFIG_HALRF_POWERTRACKING 1
-+
-+#elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
-+
-+#define CONFIG_HALRF_POWERTRACKING 1
-+
-+#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
-+
-+#define CONFIG_HALRF_POWERTRACKING 1
-+
-+#endif
-+
-+#endif /*#ifndef __HALRF_FEATURES_H__*/
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/halrf_iqk.h linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/halrf_iqk.h
-new file mode 100644
-index 000000000..0fa676b90
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/halrf_iqk.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/halrf/halrf_iqk.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/halrf/halrf_iqk.h
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/halrf/halrf_iqk.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/halrf/halrf_iqk.h 2021-03-07 18:16:17.055956100 +0200
@@ -0,0 +1,103 @@
+/******************************************************************************
+ *
@@ -177654,11 +174681,9 @@ index 000000000..0fa676b90
+};
+
+#endif /*__HALRF_IQK_H__*/
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/halrf_kfree.c linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/halrf_kfree.c
-new file mode 100644
-index 000000000..cee13be26
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/halrf_kfree.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/halrf/halrf_kfree.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/halrf/halrf_kfree.c
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/halrf/halrf_kfree.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/halrf/halrf_kfree.c 2021-03-07 18:16:17.055956100 +0200
@@ -0,0 +1,1191 @@
+/******************************************************************************
+ *
@@ -178851,11 +175876,9 @@ index 000000000..cee13be26
+ }
+ RF_DBG(dm, DBG_RF_MP, "<===[kfree] phy_ConfigKFree()\n");
+}
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/halrf_kfree.h linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/halrf_kfree.h
-new file mode 100644
-index 000000000..d57488ae8
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/halrf_kfree.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/halrf/halrf_kfree.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/halrf/halrf_kfree.h
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/halrf/halrf_kfree.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/halrf/halrf_kfree.h 2021-03-07 18:16:17.055956100 +0200
@@ -0,0 +1,119 @@
+/******************************************************************************
+ *
@@ -178976,216 +175999,9 @@ index 000000000..d57488ae8
+void phydm_config_kfree(void *dm_void, u8 channel_to_sw);
+
+#endif /*__HALRF_KFREE_H__*/
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/halrf_powertracking.c linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/halrf_powertracking.c
-new file mode 100644
-index 000000000..eaf53b8ae
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/halrf_powertracking.c
-@@ -0,0 +1,152 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ * The full GNU General Public License is included in this distribution in the
-+ * file called LICENSE.
-+ *
-+ * Contact Information:
-+ * wlanfae
-+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
-+ * Hsinchu 300, Taiwan.
-+ *
-+ * Larry Finger
-+ *
-+ *****************************************************************************/
-+
-+/*@************************************************************
-+ * include files
-+ * ************************************************************
-+ */
-+#include "mp_precomp.h"
-+#include "phydm_precomp.h"
-+
-+boolean
-+odm_check_power_status(void *dm_void)
-+{
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+ struct dm_struct *dm = (struct dm_struct *)dm_void;
-+ PADAPTER *adapter = dm->adapter;
-+
-+ RT_RF_POWER_STATE rt_state;
-+ MGNT_INFO *mgnt_info = &((PADAPTER)adapter)->MgntInfo;
-+
-+ /* 2011/07/27 MH We are not testing ready~~!! We may fail to get correct value when init sequence. */
-+ if (mgnt_info->init_adpt_in_progress == true) {
-+ RF_DBG(dm, DBG_RF_INIT,
-+ "check_pow_status Return true, due to initadapter\n");
-+ return true;
-+ }
-+
-+ /*
-+ * 2011/07/19 MH We can not execute tx pwoer tracking/ LLC calibrate or IQK.
-+ */
-+ ((PADAPTER)adapter)->HalFunc.GetHwRegHandler((PADAPTER)adapter, HW_VAR_RF_STATE, (u8 *)(&rt_state));
-+ if (((PADAPTER)adapter)->bDriverStopped || ((PADAPTER)adapter)->bDriverIsGoingToPnpSetPowerSleep || rt_state == eRfOff) {
-+ RF_DBG(dm, DBG_RF_INIT,
-+ "check_pow_status Return false, due to %d/%d/%d\n",
-+ ((PADAPTER)adapter)->bDriverStopped,
-+ ((PADAPTER)adapter)->bDriverIsGoingToPnpSetPowerSleep,
-+ rt_state);
-+ return false;
-+ }
-+#endif
-+ return true;
-+}
-+
-+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
-+void halrf_update_pwr_track(void *dm_void, u8 rate)
-+{
-+ struct dm_struct *dm = (struct dm_struct *)dm_void;
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+ u8 path_idx = 0;
-+#endif
-+
-+ RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "Pwr Track Get rate=0x%x\n", rate);
-+
-+ dm->tx_rate = rate;
-+
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+#if DEV_BUS_TYPE == RT_PCI_INTERFACE
-+#if USE_WORKITEM
-+ odm_schedule_work_item(&dm->ra_rpt_workitem);
-+#else
-+ if (dm->support_ic_type == ODM_RTL8821) {
-+#if (RTL8821A_SUPPORT == 1)
-+ odm_tx_pwr_track_set_pwr8821a(dm, MIX_MODE, RF_PATH_A, 0);
-+#endif
-+ } else if (dm->support_ic_type == ODM_RTL8812) {
-+ for (path_idx = RF_PATH_A; path_idx < MAX_PATH_NUM_8812A; path_idx++) {
-+#if (RTL8812A_SUPPORT == 1)
-+ odm_tx_pwr_track_set_pwr8812a(dm, MIX_MODE, path_idx, 0);
-+#endif
-+ }
-+ } else if (dm->support_ic_type == ODM_RTL8723B) {
-+#if (RTL8723B_SUPPORT == 1)
-+ odm_tx_pwr_track_set_pwr_8723b(dm, MIX_MODE, RF_PATH_A, 0);
-+#endif
-+ } else if (dm->support_ic_type == ODM_RTL8192E) {
-+ for (path_idx = RF_PATH_A; path_idx < MAX_PATH_NUM_8192E; path_idx++) {
-+#if (RTL8192E_SUPPORT == 1)
-+ odm_tx_pwr_track_set_pwr92_e(dm, MIX_MODE, path_idx, 0);
-+#endif
-+ }
-+ } else if (dm->support_ic_type == ODM_RTL8188E) {
-+#if (RTL8188E_SUPPORT == 1)
-+ odm_tx_pwr_track_set_pwr88_e(dm, MIX_MODE, RF_PATH_A, 0);
-+#endif
-+ }
-+#endif
-+#else
-+ odm_schedule_work_item(&dm->ra_rpt_workitem);
-+#endif
-+#endif
-+}
-+
-+#endif
-+
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+void halrf_update_init_rate_work_item_callback(
-+ void *context)
-+{
-+ void *adapter = (void *)context;
-+ HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
-+ struct dm_struct *dm = &hal_data->DM_OutSrc;
-+ u8 p = 0;
-+
-+ if (dm->support_ic_type == ODM_RTL8821) {
-+#if (RTL8821A_SUPPORT == 1)
-+ odm_tx_pwr_track_set_pwr8821a(dm, MIX_MODE, RF_PATH_A, 0);
-+#endif
-+ } else if (dm->support_ic_type == ODM_RTL8812) {
-+#if (RTL8812A_SUPPORT == 1)
-+ /*Don't know how to include &c*/
-+ for (p = RF_PATH_A; p < MAX_PATH_NUM_8812A; p++)
-+ odm_tx_pwr_track_set_pwr8812a(dm, MIX_MODE, p, 0);
-+#endif
-+ } else if (dm->support_ic_type == ODM_RTL8723B) {
-+#if (RTL8723B_SUPPORT == 1)
-+ odm_tx_pwr_track_set_pwr_8723b(dm, MIX_MODE, RF_PATH_A, 0);
-+#endif
-+ } else if (dm->support_ic_type == ODM_RTL8192E) {
-+#if (RTL8192E_SUPPORT == 1)
-+ /*Don't know how to include &c*/
-+ for (p = RF_PATH_A; p < MAX_PATH_NUM_8192E; p++)
-+ odm_tx_pwr_track_set_pwr92_e(dm, MIX_MODE, p, 0);
-+#endif
-+ } else if (dm->support_ic_type == ODM_RTL8188E) {
-+#if (RTL8188E_SUPPORT == 1)
-+ odm_tx_pwr_track_set_pwr88_e(dm, MIX_MODE, RF_PATH_A, 0);
-+#endif
-+ }
-+}
-+#endif
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/halrf_powertracking.h linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/halrf_powertracking.h
-new file mode 100644
-index 000000000..c45628854
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/halrf_powertracking.h
-@@ -0,0 +1,41 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ * The full GNU General Public License is included in this distribution in the
-+ * file called LICENSE.
-+ *
-+ * Contact Information:
-+ * wlanfae
-+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
-+ * Hsinchu 300, Taiwan.
-+ *
-+ * Larry Finger
-+ *
-+ *****************************************************************************/
-+
-+#ifndef __HALRF_POWER_TRACKING_H__
-+#define __HALRF_POWER_TRACKING_H__
-+
-+boolean
-+odm_check_power_status(void *dm_void);
-+
-+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
-+void halrf_update_pwr_track(void *dm_void, u8 rate);
-+#endif
-+
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+void halrf_update_init_rate_work_item_callback(
-+ void *context);
-+#endif
-+
-+#endif /*#ifndef __HALRF_POWERTRACKING_H__*/
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/halrf_powertracking_ap.c linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/halrf_powertracking_ap.c
-new file mode 100644
-index 000000000..cafd92f8d
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/halrf_powertracking_ap.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/halrf/halrf_powertracking_ap.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/halrf/halrf_powertracking_ap.c
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/halrf/halrf_powertracking_ap.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/halrf/halrf_powertracking_ap.c 2021-03-07 18:16:17.055956100 +0200
@@ -0,0 +1,1220 @@
+/******************************************************************************
+ *
@@ -180407,11 +177223,9 @@ index 000000000..cafd92f8d
+#endif
+
+}
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/halrf_powertracking_ap.h linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/halrf_powertracking_ap.h
-new file mode 100644
-index 000000000..1f960cf46
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/halrf_powertracking_ap.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/halrf/halrf_powertracking_ap.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/halrf/halrf_powertracking_ap.h
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/halrf/halrf_powertracking_ap.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/halrf/halrf_powertracking_ap.h 2021-03-07 18:16:17.055956100 +0200
@@ -0,0 +1,398 @@
+/******************************************************************************
+ *
@@ -180811,11 +177625,165 @@ index 000000000..1f960cf46
+
+
+#endif /*#ifndef __HALRF_POWER_TRACKING_H__*/
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/halrf_powertracking_ce.c linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/halrf_powertracking_ce.c
-new file mode 100644
-index 000000000..55ec7bf16
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/halrf_powertracking_ce.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/halrf/halrf_powertracking.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/halrf/halrf_powertracking.c
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/halrf/halrf_powertracking.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/halrf/halrf_powertracking.c 2021-03-07 18:16:17.055956100 +0200
+@@ -0,0 +1,152 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * The full GNU General Public License is included in this distribution in the
++ * file called LICENSE.
++ *
++ * Contact Information:
++ * wlanfae
++ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
++ * Hsinchu 300, Taiwan.
++ *
++ * Larry Finger
++ *
++ *****************************************************************************/
++
++/*@************************************************************
++ * include files
++ * ************************************************************
++ */
++#include "mp_precomp.h"
++#include "phydm_precomp.h"
++
++boolean
++odm_check_power_status(void *dm_void)
++{
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++ struct dm_struct *dm = (struct dm_struct *)dm_void;
++ PADAPTER *adapter = dm->adapter;
++
++ RT_RF_POWER_STATE rt_state;
++ MGNT_INFO *mgnt_info = &((PADAPTER)adapter)->MgntInfo;
++
++ /* 2011/07/27 MH We are not testing ready~~!! We may fail to get correct value when init sequence. */
++ if (mgnt_info->init_adpt_in_progress == true) {
++ RF_DBG(dm, DBG_RF_INIT,
++ "check_pow_status Return true, due to initadapter\n");
++ return true;
++ }
++
++ /*
++ * 2011/07/19 MH We can not execute tx pwoer tracking/ LLC calibrate or IQK.
++ */
++ ((PADAPTER)adapter)->HalFunc.GetHwRegHandler((PADAPTER)adapter, HW_VAR_RF_STATE, (u8 *)(&rt_state));
++ if (((PADAPTER)adapter)->bDriverStopped || ((PADAPTER)adapter)->bDriverIsGoingToPnpSetPowerSleep || rt_state == eRfOff) {
++ RF_DBG(dm, DBG_RF_INIT,
++ "check_pow_status Return false, due to %d/%d/%d\n",
++ ((PADAPTER)adapter)->bDriverStopped,
++ ((PADAPTER)adapter)->bDriverIsGoingToPnpSetPowerSleep,
++ rt_state);
++ return false;
++ }
++#endif
++ return true;
++}
++
++#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
++void halrf_update_pwr_track(void *dm_void, u8 rate)
++{
++ struct dm_struct *dm = (struct dm_struct *)dm_void;
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++ u8 path_idx = 0;
++#endif
++
++ RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "Pwr Track Get rate=0x%x\n", rate);
++
++ dm->tx_rate = rate;
++
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++#if DEV_BUS_TYPE == RT_PCI_INTERFACE
++#if USE_WORKITEM
++ odm_schedule_work_item(&dm->ra_rpt_workitem);
++#else
++ if (dm->support_ic_type == ODM_RTL8821) {
++#if (RTL8821A_SUPPORT == 1)
++ odm_tx_pwr_track_set_pwr8821a(dm, MIX_MODE, RF_PATH_A, 0);
++#endif
++ } else if (dm->support_ic_type == ODM_RTL8812) {
++ for (path_idx = RF_PATH_A; path_idx < MAX_PATH_NUM_8812A; path_idx++) {
++#if (RTL8812A_SUPPORT == 1)
++ odm_tx_pwr_track_set_pwr8812a(dm, MIX_MODE, path_idx, 0);
++#endif
++ }
++ } else if (dm->support_ic_type == ODM_RTL8723B) {
++#if (RTL8723B_SUPPORT == 1)
++ odm_tx_pwr_track_set_pwr_8723b(dm, MIX_MODE, RF_PATH_A, 0);
++#endif
++ } else if (dm->support_ic_type == ODM_RTL8192E) {
++ for (path_idx = RF_PATH_A; path_idx < MAX_PATH_NUM_8192E; path_idx++) {
++#if (RTL8192E_SUPPORT == 1)
++ odm_tx_pwr_track_set_pwr92_e(dm, MIX_MODE, path_idx, 0);
++#endif
++ }
++ } else if (dm->support_ic_type == ODM_RTL8188E) {
++#if (RTL8188E_SUPPORT == 1)
++ odm_tx_pwr_track_set_pwr88_e(dm, MIX_MODE, RF_PATH_A, 0);
++#endif
++ }
++#endif
++#else
++ odm_schedule_work_item(&dm->ra_rpt_workitem);
++#endif
++#endif
++}
++
++#endif
++
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++void halrf_update_init_rate_work_item_callback(
++ void *context)
++{
++ void *adapter = (void *)context;
++ HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
++ struct dm_struct *dm = &hal_data->DM_OutSrc;
++ u8 p = 0;
++
++ if (dm->support_ic_type == ODM_RTL8821) {
++#if (RTL8821A_SUPPORT == 1)
++ odm_tx_pwr_track_set_pwr8821a(dm, MIX_MODE, RF_PATH_A, 0);
++#endif
++ } else if (dm->support_ic_type == ODM_RTL8812) {
++#if (RTL8812A_SUPPORT == 1)
++ /*Don't know how to include &c*/
++ for (p = RF_PATH_A; p < MAX_PATH_NUM_8812A; p++)
++ odm_tx_pwr_track_set_pwr8812a(dm, MIX_MODE, p, 0);
++#endif
++ } else if (dm->support_ic_type == ODM_RTL8723B) {
++#if (RTL8723B_SUPPORT == 1)
++ odm_tx_pwr_track_set_pwr_8723b(dm, MIX_MODE, RF_PATH_A, 0);
++#endif
++ } else if (dm->support_ic_type == ODM_RTL8192E) {
++#if (RTL8192E_SUPPORT == 1)
++ /*Don't know how to include &c*/
++ for (p = RF_PATH_A; p < MAX_PATH_NUM_8192E; p++)
++ odm_tx_pwr_track_set_pwr92_e(dm, MIX_MODE, p, 0);
++#endif
++ } else if (dm->support_ic_type == ODM_RTL8188E) {
++#if (RTL8188E_SUPPORT == 1)
++ odm_tx_pwr_track_set_pwr88_e(dm, MIX_MODE, RF_PATH_A, 0);
++#endif
++ }
++}
++#endif
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/halrf/halrf_powertracking_ce.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/halrf/halrf_powertracking_ce.c
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/halrf/halrf_powertracking_ce.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/halrf/halrf_powertracking_ce.c 2021-03-07 18:16:17.055956100 +0200
@@ -0,0 +1,869 @@
+/******************************************************************************
+ *
@@ -181686,11 +178654,9 @@ index 000000000..55ec7bf16
+
+#endif
+}
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/halrf_powertracking_ce.h linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/halrf_powertracking_ce.h
-new file mode 100644
-index 000000000..4b96ccc7e
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/halrf_powertracking_ce.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/halrf/halrf_powertracking_ce.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/halrf/halrf_powertracking_ce.h
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/halrf/halrf_powertracking_ce.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/halrf/halrf_powertracking_ce.h 2021-03-07 18:16:17.056956148 +0200
@@ -0,0 +1,327 @@
+/******************************************************************************
+ *
@@ -182019,11 +178985,54 @@ index 000000000..4b96ccc7e
+#endif
+
+#endif /*__HALRF_POWER_TRACKING_H__*/
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/halrf_powertracking_iot.c linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/halrf_powertracking_iot.c
-new file mode 100644
-index 000000000..a0c40dc9d
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/halrf_powertracking_iot.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/halrf/halrf_powertracking.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/halrf/halrf_powertracking.h
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/halrf/halrf_powertracking.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/halrf/halrf_powertracking.h 2021-03-07 18:16:17.055956100 +0200
+@@ -0,0 +1,41 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * The full GNU General Public License is included in this distribution in the
++ * file called LICENSE.
++ *
++ * Contact Information:
++ * wlanfae
++ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
++ * Hsinchu 300, Taiwan.
++ *
++ * Larry Finger
++ *
++ *****************************************************************************/
++
++#ifndef __HALRF_POWER_TRACKING_H__
++#define __HALRF_POWER_TRACKING_H__
++
++boolean
++odm_check_power_status(void *dm_void);
++
++#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
++void halrf_update_pwr_track(void *dm_void, u8 rate);
++#endif
++
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++void halrf_update_init_rate_work_item_callback(
++ void *context);
++#endif
++
++#endif /*#ifndef __HALRF_POWERTRACKING_H__*/
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/halrf/halrf_powertracking_iot.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/halrf/halrf_powertracking_iot.c
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/halrf/halrf_powertracking_iot.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/halrf/halrf_powertracking_iot.c 2021-03-07 18:16:17.056956148 +0200
@@ -0,0 +1,741 @@
+/******************************************************************************
+ *
@@ -182766,11 +179775,9 @@ index 000000000..a0c40dc9d
+
+#endif
+}
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/halrf_powertracking_iot.h linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/halrf_powertracking_iot.h
-new file mode 100644
-index 000000000..55460a62e
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/halrf_powertracking_iot.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/halrf/halrf_powertracking_iot.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/halrf/halrf_powertracking_iot.h
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/halrf/halrf_powertracking_iot.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/halrf/halrf_powertracking_iot.h 2021-03-07 18:16:17.056956148 +0200
@@ -0,0 +1,349 @@
+/******************************************************************************
+ *
@@ -183121,11 +180128,9 @@ index 000000000..55460a62e
+#endif
+
+#endif /*#ifndef __HALRF_POWER_TRACKING_H__*/
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/halrf_powertracking_win.c linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/halrf_powertracking_win.c
-new file mode 100644
-index 000000000..bad28f508
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/halrf_powertracking_win.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/halrf/halrf_powertracking_win.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/halrf/halrf_powertracking_win.c
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/halrf/halrf_powertracking_win.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/halrf/halrf_powertracking_win.c 2021-03-07 18:16:17.056956148 +0200
@@ -0,0 +1,861 @@
+/******************************************************************************
+ *
@@ -183988,11 +180993,9 @@ index 000000000..bad28f508
+}
+
+#endif
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/halrf_powertracking_win.h linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/halrf_powertracking_win.h
-new file mode 100644
-index 000000000..3ecdc1d0f
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/halrf_powertracking_win.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/halrf/halrf_powertracking_win.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/halrf/halrf_powertracking_win.h
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/halrf/halrf_powertracking_win.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/halrf/halrf_powertracking_win.h 2021-03-07 18:16:17.056956148 +0200
@@ -0,0 +1,302 @@
+/******************************************************************************
+ *
@@ -184296,11 +181299,9 @@ index 000000000..3ecdc1d0f
+
+
+#endif /*#ifndef __HALRF_POWER_TRACKING_H__*/
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/halrf_psd.c linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/halrf_psd.c
-new file mode 100644
-index 000000000..8c2f87429
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/halrf_psd.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/halrf/halrf_psd.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/halrf/halrf_psd.c
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/halrf/halrf_psd.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/halrf/halrf_psd.c 2021-03-07 18:16:17.056956148 +0200
@@ -0,0 +1,428 @@
+/******************************************************************************
+ *
@@ -184730,11 +181731,9 @@ index 000000000..8c2f87429
+}
+
+#endif /*#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)*/
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/halrf_psd.h linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/halrf_psd.h
-new file mode 100644
-index 000000000..986ff8815
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/halrf_psd.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/halrf/halrf_psd.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/halrf/halrf_psd.h
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/halrf/halrf_psd.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/halrf/halrf_psd.h 2021-03-07 18:16:17.056956148 +0200
@@ -0,0 +1,52 @@
+/******************************************************************************
+ *
@@ -184788,11 +181787,9 @@ index 000000000..986ff8815
+
+#endif /*#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)*/
+#endif /*#__HALRF_PSD_H__*/
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/halrf_txgapcal.c linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/halrf_txgapcal.c
-new file mode 100644
-index 000000000..0cc44974b
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/halrf_txgapcal.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/halrf/halrf_txgapcal.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/halrf/halrf_txgapcal.c
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/halrf/halrf_txgapcal.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/halrf/halrf_txgapcal.c 2021-03-07 18:16:17.056956148 +0200
@@ -0,0 +1,300 @@
+/******************************************************************************
+ *
@@ -185094,11 +182091,9 @@ index 000000000..0cc44974b
+ odm_tx_gain_gap_calibration_8197f(dm_void);
+#endif
+}
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/halrf_txgapcal.h linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/halrf_txgapcal.h
-new file mode 100644
-index 000000000..09651cbee
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/halrf_txgapcal.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/halrf/halrf_txgapcal.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/halrf/halrf_txgapcal.h
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/halrf/halrf_txgapcal.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/halrf/halrf_txgapcal.h 2021-03-07 18:16:17.056956148 +0200
@@ -0,0 +1,31 @@
+/******************************************************************************
+ *
@@ -185131,11 +182126,9 @@ index 000000000..09651cbee
+void odm_tx_gain_gap_calibration(void *dm_void);
+
+#endif /*__HALRF_TXGAPCAL_H__*/
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/rtl8812a/halrf_8812a_ap.c linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/rtl8812a/halrf_8812a_ap.c
-new file mode 100644
-index 000000000..8861416bf
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/rtl8812a/halrf_8812a_ap.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/halrf/rtl8812a/halrf_8812a_ap.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/halrf/rtl8812a/halrf_8812a_ap.c
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/halrf/rtl8812a/halrf_8812a_ap.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/halrf/rtl8812a/halrf_8812a_ap.c 2021-03-07 18:16:17.056956148 +0200
@@ -0,0 +1,2169 @@
+/******************************************************************************
+ *
@@ -187306,11 +184299,9 @@ index 000000000..8861416bf
+ _phy_set_rf_path_switch_8812a(dm, is_main, false);
+ }
+}
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/rtl8812a/halrf_8812a_ap.h linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/rtl8812a/halrf_8812a_ap.h
-new file mode 100644
-index 000000000..52ad7a59d
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/rtl8812a/halrf_8812a_ap.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/halrf/rtl8812a/halrf_8812a_ap.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/halrf/rtl8812a/halrf_8812a_ap.h
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/halrf/rtl8812a/halrf_8812a_ap.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/halrf/rtl8812a/halrf_8812a_ap.h 2021-03-07 18:16:17.056956148 +0200
@@ -0,0 +1,82 @@
+/******************************************************************************
+ *
@@ -187394,11 +184385,9 @@ index 000000000..52ad7a59d
+
+
+#endif /*#ifndef __HALRF_8812A_H__*/
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/rtl8812a/halrf_8812a_ce.c linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/rtl8812a/halrf_8812a_ce.c
-new file mode 100644
-index 000000000..cebb7265d
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/rtl8812a/halrf_8812a_ce.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/halrf/rtl8812a/halrf_8812a_ce.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/halrf/rtl8812a/halrf_8812a_ce.c
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/halrf/rtl8812a/halrf_8812a_ce.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/halrf/rtl8812a/halrf_8812a_ce.c 2021-03-07 18:16:17.057956195 +0200
@@ -0,0 +1,1975 @@
+/******************************************************************************
+ *
@@ -189375,11 +186364,9 @@ index 000000000..cebb7265d
+ RF_DBG(dm, DBG_RF_IQK, "<=== %s\n", __func__);
+#endif
+}
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/rtl8812a/halrf_8812a_ce.h linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/rtl8812a/halrf_8812a_ce.h
-new file mode 100644
-index 000000000..d02537c1e
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/rtl8812a/halrf_8812a_ce.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/halrf/rtl8812a/halrf_8812a_ce.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/halrf/rtl8812a/halrf_8812a_ce.h
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/halrf/rtl8812a/halrf_8812a_ce.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/halrf/rtl8812a/halrf_8812a_ce.h 2021-03-07 18:16:17.057956195 +0200
@@ -0,0 +1,63 @@
+/******************************************************************************
+ *
@@ -189444,11 +186431,9 @@ index 000000000..d02537c1e
+#endif
+ boolean is_main);
+#endif /*#ifndef __HALRF_8812A_H__*/
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/rtl8812a/halrf_8812a_win.c linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/rtl8812a/halrf_8812a_win.c
-new file mode 100644
-index 000000000..8a08f6b46
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/rtl8812a/halrf_8812a_win.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/halrf/rtl8812a/halrf_8812a_win.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/halrf/rtl8812a/halrf_8812a_win.c
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/halrf/rtl8812a/halrf_8812a_win.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/halrf/rtl8812a/halrf_8812a_win.c 2021-03-07 18:16:17.057956195 +0200
@@ -0,0 +1,2881 @@
+/******************************************************************************
+ *
@@ -192331,11 +189316,9 @@ index 000000000..8a08f6b46
+#endif
+}
+#endif
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/rtl8812a/halrf_8812a_win.h linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/rtl8812a/halrf_8812a_win.h
-new file mode 100644
-index 000000000..28e5c2de9
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/rtl8812a/halrf_8812a_win.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/halrf/rtl8812a/halrf_8812a_win.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/halrf/rtl8812a/halrf_8812a_win.h
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/halrf/rtl8812a/halrf_8812a_win.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/halrf/rtl8812a/halrf_8812a_win.h 2021-03-07 18:16:17.057956195 +0200
@@ -0,0 +1,99 @@
+/******************************************************************************
+ *
@@ -192436,11 +189419,9 @@ index 000000000..28e5c2de9
+
+
+#endif /*#ifndef __HALRF_8812A_H__*/
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/rtl8814a/halrf_8814a_ap.c linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/rtl8814a/halrf_8814a_ap.c
-new file mode 100644
-index 000000000..238df1bf4
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/rtl8814a/halrf_8814a_ap.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/halrf/rtl8814a/halrf_8814a_ap.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/halrf/rtl8814a/halrf_8814a_ap.c
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/halrf/rtl8814a/halrf_8814a_ap.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/halrf/rtl8814a/halrf_8814a_ap.c 2021-03-07 18:16:17.057956195 +0200
@@ -0,0 +1,1754 @@
+/******************************************************************************
+ *
@@ -194196,11 +191177,9 @@ index 000000000..238df1bf4
+#endif
+
+
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/rtl8814a/halrf_8814a_ap.h linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/rtl8814a/halrf_8814a_ap.h
-new file mode 100644
-index 000000000..46eaa801e
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/rtl8814a/halrf_8814a_ap.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/halrf/rtl8814a/halrf_8814a_ap.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/halrf/rtl8814a/halrf_8814a_ap.h
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/halrf/rtl8814a/halrf_8814a_ap.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/halrf/rtl8814a/halrf_8814a_ap.h 2021-03-07 18:16:17.057956195 +0200
@@ -0,0 +1,164 @@
+/******************************************************************************
+ *
@@ -194366,11 +191345,9 @@ index 000000000..46eaa801e
+
+#endif // #ifndef __HAL_PHY_RF_8814A_H__
+
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/rtl8814a/halrf_8814a_ce.c linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/rtl8814a/halrf_8814a_ce.c
-new file mode 100644
-index 000000000..09c65ed3f
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/rtl8814a/halrf_8814a_ce.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/halrf/rtl8814a/halrf_8814a_ce.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/halrf/rtl8814a/halrf_8814a_ce.c
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/halrf/rtl8814a/halrf_8814a_ce.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/halrf/rtl8814a/halrf_8814a_ce.c 2021-03-07 18:16:17.057956195 +0200
@@ -0,0 +1,564 @@
+/******************************************************************************
+ *
@@ -194936,11 +191913,9 @@ index 000000000..09c65ed3f
+
+
+
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/rtl8814a/halrf_8814a_ce.h linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/rtl8814a/halrf_8814a_ce.h
-new file mode 100644
-index 000000000..1f885b32e
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/rtl8814a/halrf_8814a_ce.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/halrf/rtl8814a/halrf_8814a_ce.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/halrf/rtl8814a/halrf_8814a_ce.h
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/halrf/rtl8814a/halrf_8814a_ce.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/halrf/rtl8814a/halrf_8814a_ce.h 2021-03-07 18:16:17.057956195 +0200
@@ -0,0 +1,112 @@
+/******************************************************************************
+ *
@@ -195054,11 +192029,9 @@ index 000000000..1f885b32e
+
+#endif // #ifndef __HAL_PHY_RF_8188E_H__
+
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/rtl8814a/halrf_8814a_win.c linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/rtl8814a/halrf_8814a_win.c
-new file mode 100644
-index 000000000..eb91c4d8a
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/rtl8814a/halrf_8814a_win.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/halrf/rtl8814a/halrf_8814a_win.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/halrf/rtl8814a/halrf_8814a_win.c
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/halrf/rtl8814a/halrf_8814a_win.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/halrf/rtl8814a/halrf_8814a_win.c 2021-03-07 18:16:17.057956195 +0200
@@ -0,0 +1,528 @@
+/******************************************************************************
+ *
@@ -195588,11 +192561,9 @@ index 000000000..eb91c4d8a
+ IN BOOLEAN bReCovery
+ ){}
+#endif /* (RTL8814A_SUPPORT == 0)*/
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/rtl8814a/halrf_8814a_win.h linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/rtl8814a/halrf_8814a_win.h
-new file mode 100644
-index 000000000..658d6f063
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/rtl8814a/halrf_8814a_win.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/halrf/rtl8814a/halrf_8814a_win.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/halrf/rtl8814a/halrf_8814a_win.h
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/halrf/rtl8814a/halrf_8814a_win.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/halrf/rtl8814a/halrf_8814a_win.h 2021-03-07 18:16:17.057956195 +0200
@@ -0,0 +1,106 @@
+/******************************************************************************
+ *
@@ -195700,11 +192671,9 @@ index 000000000..658d6f063
+
+#endif // #ifndef __HAL_PHY_RF_8188E_H__
+
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/rtl8814a/halrf_iqk_8814a.c linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/rtl8814a/halrf_iqk_8814a.c
-new file mode 100644
-index 000000000..e019df35a
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/rtl8814a/halrf_iqk_8814a.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/halrf/rtl8814a/halrf_iqk_8814a.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/halrf/rtl8814a/halrf_iqk_8814a.c
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/halrf/rtl8814a/halrf_iqk_8814a.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/halrf/rtl8814a/halrf_iqk_8814a.c 2021-03-07 18:16:17.057956195 +0200
@@ -0,0 +1,557 @@
+/******************************************************************************
+ *
@@ -196263,11 +193232,9 @@ index 000000000..e019df35a
+ }
+}
+
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/rtl8814a/halrf_iqk_8814a.h linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/rtl8814a/halrf_iqk_8814a.h
-new file mode 100644
-index 000000000..15d9cf037
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/rtl8814a/halrf_iqk_8814a.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/halrf/rtl8814a/halrf_iqk_8814a.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/halrf/rtl8814a/halrf_iqk_8814a.h
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/halrf/rtl8814a/halrf_iqk_8814a.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/halrf/rtl8814a/halrf_iqk_8814a.h 2021-03-07 18:16:17.058956242 +0200
@@ -0,0 +1,58 @@
+/******************************************************************************
+ *
@@ -196327,11 +193294,9 @@ index 000000000..15d9cf037
+ );
+
+ #endif /* #ifndef __PHYDM_IQK_8814A_H__*/
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/rtl8821a/halrf_8821a_ce.c linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/rtl8821a/halrf_8821a_ce.c
-new file mode 100644
-index 000000000..ef0f72c56
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/rtl8821a/halrf_8821a_ce.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/halrf/rtl8821a/halrf_8821a_ce.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/halrf/rtl8821a/halrf_8821a_ce.c
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/halrf/rtl8821a/halrf_8821a_ce.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/halrf/rtl8821a/halrf_8821a_ce.c 2021-03-07 18:16:17.058956242 +0200
@@ -0,0 +1,313 @@
+/******************************************************************************
+ *
@@ -196646,11 +193611,9 @@ index 000000000..ef0f72c56
+
+ phy_lc_calibrate_8812a(dm);
+}
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/rtl8821a/halrf_8821a_ce.h linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/rtl8821a/halrf_8821a_ce.h
-new file mode 100644
-index 000000000..684852a77
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/rtl8821a/halrf_8821a_ce.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/halrf/rtl8821a/halrf_8821a_ce.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/halrf/rtl8821a/halrf_8821a_ce.h
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/halrf/rtl8821a/halrf_8821a_ce.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/halrf/rtl8821a/halrf_8821a_ce.h 2021-03-07 18:16:17.058956242 +0200
@@ -0,0 +1,53 @@
+/******************************************************************************
+ *
@@ -196705,11 +193668,9 @@ index 000000000..684852a77
+);
+
+#endif /* #ifndef __HAL_PHY_RF_8821A_H__ */
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/rtl8821a/halrf_8821a_win.c linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/rtl8821a/halrf_8821a_win.c
-new file mode 100644
-index 000000000..cfb7592db
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/rtl8821a/halrf_8821a_win.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/halrf/rtl8821a/halrf_8821a_win.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/halrf/rtl8821a/halrf_8821a_win.c
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/halrf/rtl8821a/halrf_8821a_win.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/halrf/rtl8821a/halrf_8821a_win.c 2021-03-07 18:16:17.058956242 +0200
@@ -0,0 +1,1046 @@
+/******************************************************************************
+ *
@@ -197757,11 +194718,9 @@ index 000000000..cfb7592db
+
+ phy_lc_calibrate_8812a(dm);
+}
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/rtl8821a/halrf_8821a_win.h linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/rtl8821a/halrf_8821a_win.h
-new file mode 100644
-index 000000000..2f50dac05
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/rtl8821a/halrf_8821a_win.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/halrf/rtl8821a/halrf_8821a_win.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/halrf/rtl8821a/halrf_8821a_win.h
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/halrf/rtl8821a/halrf_8821a_win.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/halrf/rtl8821a/halrf_8821a_win.h 2021-03-07 18:16:17.058956242 +0200
@@ -0,0 +1,72 @@
+/******************************************************************************
+ *
@@ -197835,11 +194794,9 @@ index 000000000..2f50dac05
+);
+
+#endif /* #ifndef __HAL_PHY_RF_8821A_H__ */
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/rtl8821a/halrf_iqk_8821a_ap.c linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/rtl8821a/halrf_iqk_8821a_ap.c
-new file mode 100644
-index 000000000..c98cbc01c
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/rtl8821a/halrf_iqk_8821a_ap.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/halrf/rtl8821a/halrf_iqk_8821a_ap.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/halrf/rtl8821a/halrf_iqk_8821a_ap.c
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/halrf/rtl8821a/halrf_iqk_8821a_ap.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/halrf/rtl8821a/halrf_iqk_8821a_ap.c 2021-03-07 18:16:17.058956242 +0200
@@ -0,0 +1,731 @@
+/******************************************************************************
+ *
@@ -198572,12 +195529,10 @@ index 000000000..c98cbc01c
+
+ _phy_iq_calibrate_8821a(dm);
+}
-\ No newline at end of file
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/rtl8821a/halrf_iqk_8821a_ap.h linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/rtl8821a/halrf_iqk_8821a_ap.h
-new file mode 100644
-index 000000000..82cbf62ff
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/rtl8821a/halrf_iqk_8821a_ap.h
+\ Ingen nyrad vid filslut
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/halrf/rtl8821a/halrf_iqk_8821a_ap.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/halrf/rtl8821a/halrf_iqk_8821a_ap.h
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/halrf/rtl8821a/halrf_iqk_8821a_ap.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/halrf/rtl8821a/halrf_iqk_8821a_ap.h 2021-03-07 18:16:17.058956242 +0200
@@ -0,0 +1,42 @@
+/******************************************************************************
+ *
@@ -198621,11 +195576,9 @@ index 000000000..82cbf62ff
+);
+#endif
+#endif /* #ifndef __PHYDM_IQK_8821A_H__ */
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/rtl8821a/halrf_iqk_8821a_ce.c linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/rtl8821a/halrf_iqk_8821a_ce.c
-new file mode 100644
-index 000000000..b6491baf7
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/rtl8821a/halrf_iqk_8821a_ce.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/halrf/rtl8821a/halrf_iqk_8821a_ce.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/halrf/rtl8821a/halrf_iqk_8821a_ce.c
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/halrf/rtl8821a/halrf_iqk_8821a_ce.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/halrf/rtl8821a/halrf_iqk_8821a_ce.c 2021-03-07 18:16:17.058956242 +0200
@@ -0,0 +1,773 @@
+/******************************************************************************
+ *
@@ -199400,11 +196353,9 @@ index 000000000..b6491baf7
+ _phy_iq_calibrate_8821a(dm);
+}
+#endif
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/rtl8821a/halrf_iqk_8821a_ce.h linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/rtl8821a/halrf_iqk_8821a_ce.h
-new file mode 100644
-index 000000000..23d61e5c7
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/rtl8821a/halrf_iqk_8821a_ce.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/halrf/rtl8821a/halrf_iqk_8821a_ce.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/halrf/rtl8821a/halrf_iqk_8821a_ce.h
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/halrf/rtl8821a/halrf_iqk_8821a_ce.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/halrf/rtl8821a/halrf_iqk_8821a_ce.h 2021-03-07 18:16:17.058956242 +0200
@@ -0,0 +1,41 @@
+/******************************************************************************
+ *
@@ -199447,11 +196398,9 @@ index 000000000..23d61e5c7
+);
+#endif
+#endif /* #ifndef __PHYDM_IQK_8821A_H__ */
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/rtl8821a/halrf_iqk_8821a_win.c linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/rtl8821a/halrf_iqk_8821a_win.c
-new file mode 100644
-index 000000000..e1c267a5f
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/rtl8821a/halrf_iqk_8821a_win.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/halrf/rtl8821a/halrf_iqk_8821a_win.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/halrf/rtl8821a/halrf_iqk_8821a_win.c
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/halrf/rtl8821a/halrf_iqk_8821a_win.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/halrf/rtl8821a/halrf_iqk_8821a_win.c 2021-03-07 18:16:17.058956242 +0200
@@ -0,0 +1,774 @@
+/******************************************************************************
+ *
@@ -200227,11 +197176,9 @@ index 000000000..e1c267a5f
+ _phy_iq_calibrate_8821a(dm);
+}
+#endif
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/rtl8821a/halrf_iqk_8821a_win.h linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/rtl8821a/halrf_iqk_8821a_win.h
-new file mode 100644
-index 000000000..d325102b8
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/halrf/rtl8821a/halrf_iqk_8821a_win.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/halrf/rtl8821a/halrf_iqk_8821a_win.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/halrf/rtl8821a/halrf_iqk_8821a_win.h
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/halrf/rtl8821a/halrf_iqk_8821a_win.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/halrf/rtl8821a/halrf_iqk_8821a_win.h 2021-03-07 18:16:17.058956242 +0200
@@ -0,0 +1,42 @@
+/******************************************************************************
+ *
@@ -200275,11 +197222,9 @@ index 000000000..d325102b8
+);
+#endif
+#endif /* #ifndef __PHYDM_IQK_8821A_H__ */
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/mp_precomp.h linux-5.8/3rdparty/rtl8812au/hal/phydm/mp_precomp.h
-new file mode 100644
-index 000000000..897adc13f
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/mp_precomp.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/mp_precomp.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/mp_precomp.h
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/mp_precomp.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/mp_precomp.h 2021-03-07 18:16:17.058956242 +0200
@@ -0,0 +1,24 @@
+/******************************************************************************
+ *
@@ -200305,4877 +197250,9 @@ index 000000000..897adc13f
+ * Larry Finger
+ *
+ *****************************************************************************/
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm.c linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm.c
-new file mode 100644
-index 000000000..1e980630e
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm.c
-@@ -0,0 +1,3265 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ * The full GNU General Public License is included in this distribution in the
-+ * file called LICENSE.
-+ *
-+ * Contact Information:
-+ * wlanfae
-+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
-+ * Hsinchu 300, Taiwan.
-+ *
-+ * Larry Finger
-+ *
-+ *****************************************************************************/
-+
-+/*@************************************************************
-+ * include files
-+ ************************************************************/
-+
-+#include "mp_precomp.h"
-+#include "phydm_precomp.h"
-+
-+const u16 phy_rate_table[] = {
-+ /*@20M*/
-+ 1, 2, 5, 11,
-+ 6, 9, 12, 18, 24, 36, 48, 54,
-+ 6, 13, 19, 26, 39, 52, 58, 65, /*@MCS0~7*/
-+ 13, 26, 39, 52, 78, 104, 117, 130 /*@MCS8~15*/
-+};
-+
-+void phydm_traffic_load_decision(void *dm_void)
-+{
-+ struct dm_struct *dm = (struct dm_struct *)dm_void;
-+ u8 shift = 0;
-+
-+ /*@---TP & Trafic-load calculation---*/
-+
-+ if (dm->last_tx_ok_cnt > *dm->num_tx_bytes_unicast)
-+ dm->last_tx_ok_cnt = *dm->num_tx_bytes_unicast;
-+
-+ if (dm->last_rx_ok_cnt > *dm->num_rx_bytes_unicast)
-+ dm->last_rx_ok_cnt = *dm->num_rx_bytes_unicast;
-+
-+ dm->cur_tx_ok_cnt = *dm->num_tx_bytes_unicast - dm->last_tx_ok_cnt;
-+ dm->cur_rx_ok_cnt = *dm->num_rx_bytes_unicast - dm->last_rx_ok_cnt;
-+ dm->last_tx_ok_cnt = *dm->num_tx_bytes_unicast;
-+ dm->last_rx_ok_cnt = *dm->num_rx_bytes_unicast;
-+
-+ /*@AP: <<3(8bit), >>20(10^6,M), >>0(1sec)*/
-+ shift = 17 + (PHYDM_WATCH_DOG_PERIOD - 1);
-+ /*@WIN&CE: <<3(8bit), >>20(10^6,M), >>1(2sec)*/
-+
-+ dm->tx_tp = (dm->tx_tp >> 1) + (u32)((dm->cur_tx_ok_cnt >> shift) >> 1);
-+ dm->rx_tp = (dm->rx_tp >> 1) + (u32)((dm->cur_rx_ok_cnt >> shift) >> 1);
-+
-+ dm->total_tp = dm->tx_tp + dm->rx_tp;
-+
-+ /*@[Calculate TX/RX state]*/
-+ if (dm->tx_tp > (dm->rx_tp << 1))
-+ dm->txrx_state_all = TX_STATE;
-+ else if (dm->rx_tp > (dm->tx_tp << 1))
-+ dm->txrx_state_all = RX_STATE;
-+ else
-+ dm->txrx_state_all = BI_DIRECTION_STATE;
-+
-+ /*@[Traffic load decision]*/
-+ dm->pre_traffic_load = dm->traffic_load;
-+
-+ if (dm->cur_tx_ok_cnt > 1875000 || dm->cur_rx_ok_cnt > 1875000) {
-+ /* @( 1.875M * 8bit ) / 2sec= 7.5M bits /sec )*/
-+ dm->traffic_load = TRAFFIC_HIGH;
-+ } else if (dm->cur_tx_ok_cnt > 500000 || dm->cur_rx_ok_cnt > 500000) {
-+ /*@( 0.5M * 8bit ) / 2sec = 2M bits /sec )*/
-+ dm->traffic_load = TRAFFIC_MID;
-+ } else if (dm->cur_tx_ok_cnt > 100000 || dm->cur_rx_ok_cnt > 100000) {
-+ /*@( 0.1M * 8bit ) / 2sec = 0.4M bits /sec )*/
-+ dm->traffic_load = TRAFFIC_LOW;
-+ } else if (dm->cur_tx_ok_cnt > 25000 || dm->cur_rx_ok_cnt > 25000) {
-+ /*@( 0.025M * 8bit ) / 2sec = 0.1M bits /sec )*/
-+ dm->traffic_load = TRAFFIC_ULTRA_LOW;
-+ } else {
-+ dm->traffic_load = TRAFFIC_NO_TP;
-+ }
-+
-+ /*@[Calculate consecutive idlel time]*/
-+ if (dm->traffic_load == 0)
-+ dm->consecutive_idlel_time += PHYDM_WATCH_DOG_PERIOD;
-+ else
-+ dm->consecutive_idlel_time = 0;
-+
-+ #if 0
-+ PHYDM_DBG(dm, DBG_COMMON_FLOW,
-+ "cur_tx_ok_cnt = %d, cur_rx_ok_cnt = %d, last_tx_ok_cnt = %d, last_rx_ok_cnt = %d\n",
-+ dm->cur_tx_ok_cnt, dm->cur_rx_ok_cnt, dm->last_tx_ok_cnt,
-+ dm->last_rx_ok_cnt);
-+
-+ PHYDM_DBG(dm, DBG_COMMON_FLOW, "tx_tp = %d, rx_tp = %d\n", dm->tx_tp,
-+ dm->rx_tp);
-+ #endif
-+}
-+
-+void phydm_cck_new_agc_chk(struct dm_struct *dm)
-+{
-+ dm->cck_new_agc = 0;
-+
-+#if ((RTL8723D_SUPPORT == 1) || (RTL8822B_SUPPORT == 1) || \
-+ (RTL8821C_SUPPORT == 1) || (RTL8197F_SUPPORT == 1) || \
-+ (RTL8710B_SUPPORT == 1) || (RTL8192F_SUPPORT == 1) || \
-+ (RTL8195B_SUPPORT == 1) || (RTL8198F_SUPPORT == 1) || \
-+ (RTL8822C_SUPPORT == 1) || (RTL8721D_SUPPORT == 1))
-+ if (dm->support_ic_type &
-+ (ODM_RTL8723D | ODM_RTL8822B | ODM_RTL8821C | ODM_RTL8197F |
-+ ODM_RTL8710B | ODM_RTL8192F | ODM_RTL8195B | ODM_RTL8721D)) {
-+ /*@1: new agc 0: old agc*/
-+ dm->cck_new_agc = (boolean)odm_get_bb_reg(dm, R_0xa9c, BIT(17));
-+ } else if (dm->support_ic_type & (ODM_RTL8198F | ODM_RTL8822C)) {
-+ /*@1: new agc 0: old agc*/
-+ dm->cck_new_agc = (boolean)odm_get_bb_reg(dm, R_0x1a9c,
-+ BIT(17));
-+ }
-+#endif
-+}
-+
-+/*select 3 or 4 bit LNA */
-+void phydm_cck_lna_bit_num_chk(struct dm_struct *dm)
-+{
-+ boolean report_type = 0;
-+ #if (RTL8192E_SUPPORT == 1)
-+ u32 value_824, value_82c;
-+ #endif
-+
-+ #if (RTL8192E_SUPPORT == 1)
-+ if (dm->support_ic_type & (ODM_RTL8192E)) {
-+ /* @0x824[9] = 0x82C[9] = 0xA80[7] those registers setting
-+ * should be equal or CCK RSSI report may be incorrect
-+ */
-+ value_824 = odm_get_bb_reg(dm, R_0x824, BIT(9));
-+ value_82c = odm_get_bb_reg(dm, R_0x82c, BIT(9));
-+
-+ if (value_824 != value_82c)
-+ odm_set_bb_reg(dm, R_0x82c, BIT(9), value_824);
-+ odm_set_bb_reg(dm, R_0xa80, BIT(7), value_824);
-+ report_type = (boolean)value_824;
-+ }
-+ #endif
-+
-+ #if (RTL8703B_SUPPORT || RTL8723D_SUPPORT || RTL8710B_SUPPORT)
-+ if (dm->support_ic_type &
-+ (ODM_RTL8703B | ODM_RTL8723D | ODM_RTL8710B)) {
-+ report_type = (boolean)odm_get_bb_reg(dm, R_0x950, BIT(11));
-+
-+ if (report_type != 1)
-+ pr_debug("[Warning] CCK should be 4bit LNA\n");
-+ }
-+ #endif
-+
-+ #if (RTL8821C_SUPPORT == 1)
-+ if (dm->support_ic_type & ODM_RTL8821C) {
-+ if (dm->default_rf_set_8821c == SWITCH_TO_BTG)
-+ report_type = 1;
-+ }
-+ #endif
-+
-+ dm->cck_agc_report_type = report_type;
-+
-+ PHYDM_DBG(dm, ODM_COMP_INIT, "cck_agc_report_type=((%d))\n",
-+ dm->cck_agc_report_type);
-+}
-+
-+void phydm_init_cck_setting(struct dm_struct *dm)
-+{
-+ u32 reg_tmp = 0;
-+ u32 mask_tmp = 0;
-+
-+ reg_tmp = ODM_REG(CCK_RPT_FORMAT, dm);
-+ mask_tmp = ODM_BIT(CCK_RPT_FORMAT, dm);
-+ dm->is_cck_high_power = (boolean)odm_get_bb_reg(dm, reg_tmp, mask_tmp);
-+
-+ PHYDM_DBG(dm, ODM_COMP_INIT, "ext_lna_gain=((%d))\n", dm->ext_lna_gain);
-+
-+ phydm_config_cck_rx_antenna_init(dm);
-+
-+ if (dm->support_ic_type & (ODM_RTL8192F))
-+ phydm_config_cck_rx_path(dm, BB_PATH_AB);
-+ else
-+ phydm_config_cck_rx_path(dm, BB_PATH_A);
-+
-+ phydm_cck_new_agc_chk(dm);
-+ phydm_cck_lna_bit_num_chk(dm);
-+ phydm_get_cck_rssi_table_from_reg(dm);
-+}
-+
-+void phydm_init_hw_info_by_rfe(struct dm_struct *dm)
-+{
-+#if (RTL8822B_SUPPORT == 1)
-+ /*@if (dm->support_ic_type & ODM_RTL8822B)*/
-+ /*@phydm_init_hw_info_by_rfe_type_8822b(dm);*/
-+#endif
-+#if (RTL8821C_SUPPORT == 1)
-+ if (dm->support_ic_type & ODM_RTL8821C)
-+ phydm_init_hw_info_by_rfe_type_8821c(dm);
-+#endif
-+#if (RTL8197F_SUPPORT == 1)
-+ if (dm->support_ic_type & ODM_RTL8197F)
-+ phydm_init_hw_info_by_rfe_type_8197f(dm);
-+#endif
-+}
-+
-+void phydm_common_info_self_init(struct dm_struct *dm)
-+{
-+ u32 reg_tmp = 0;
-+ u32 mask_tmp = 0;
-+
-+ /*@BB IP Generation*/
-+ if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
-+ dm->ic_ip_series = PHYDM_IC_JGR3;
-+ else if (dm->support_ic_type & ODM_IC_11AC_SERIES)
-+ dm->ic_ip_series = PHYDM_IC_AC;
-+ else if (dm->support_ic_type & ODM_IC_11N_SERIES)
-+ dm->ic_ip_series = PHYDM_IC_N;
-+
-+ /*@BB phy-status Generation*/
-+ if (dm->support_ic_type & PHYSTS_3RD_TYPE_IC)
-+ dm->ic_phy_sts_type = PHYDM_PHYSTS_TYPE_3;
-+ else if (dm->support_ic_type & PHYSTS_2ND_TYPE_IC)
-+ dm->ic_phy_sts_type = PHYDM_PHYSTS_TYPE_2;
-+ else
-+ dm->ic_phy_sts_type = PHYDM_PHYSTS_TYPE_1;
-+
-+ phydm_init_cck_setting(dm);
-+
-+ reg_tmp = ODM_REG(BB_RX_PATH, dm);
-+ mask_tmp = ODM_BIT(BB_RX_PATH, dm);
-+ dm->rf_path_rx_enable = (u8)odm_get_bb_reg(dm, reg_tmp, mask_tmp);
-+#if (DM_ODM_SUPPORT_TYPE != ODM_CE)
-+ dm->is_net_closed = &dm->BOOLEAN_temp;
-+
-+ phydm_init_debug_setting(dm);
-+#endif
-+ phydm_init_soft_ml_setting(dm);
-+
-+ dm->phydm_sys_up_time = 0;
-+
-+ if (dm->support_ic_type & ODM_IC_1SS)
-+ dm->num_rf_path = 1;
-+ else if (dm->support_ic_type & ODM_IC_2SS)
-+ dm->num_rf_path = 2;
-+ #if 0
-+ /* @RTK do not has IC which is equipped with 3 RF paths,
-+ * so ODM_IC_3SS is an enpty macro and result in coverity check errors
-+ */
-+ else if (dm->support_ic_type & ODM_IC_3SS)
-+ dm->num_rf_path = 3;
-+ #endif
-+ else if (dm->support_ic_type & ODM_IC_4SS)
-+ dm->num_rf_path = 4;
-+ else
-+ dm->num_rf_path = 1;
-+
-+ phydm_trx_antenna_setting_init(dm, dm->num_rf_path);
-+
-+ dm->tx_rate = 0xFF;
-+ dm->rssi_min_by_path = 0xFF;
-+
-+ dm->number_linked_client = 0;
-+ dm->pre_number_linked_client = 0;
-+ dm->number_active_client = 0;
-+ dm->pre_number_active_client = 0;
-+
-+ dm->last_tx_ok_cnt = 0;
-+ dm->last_rx_ok_cnt = 0;
-+ dm->tx_tp = 0;
-+ dm->rx_tp = 0;
-+ dm->total_tp = 0;
-+ dm->traffic_load = TRAFFIC_LOW;
-+
-+ dm->nbi_set_result = 0;
-+ dm->is_init_hw_info_by_rfe = false;
-+ dm->pre_dbg_priority = DBGPORT_RELEASE;
-+ dm->tp_active_th = 5;
-+ dm->disable_phydm_watchdog = 0;
-+
-+ dm->u8_dummy = 0xf;
-+ dm->u16_dummy = 0xffff;
-+ dm->u32_dummy = 0xffffffff;
-+
-+ dm->pause_lv_table.lv_cckpd = PHYDM_PAUSE_RELEASE;
-+ dm->pause_lv_table.lv_dig = PHYDM_PAUSE_RELEASE;
-+}
-+
-+void phydm_cmn_sta_info_update(void *dm_void, u8 macid)
-+{
-+ struct dm_struct *dm = (struct dm_struct *)dm_void;
-+ struct cmn_sta_info *sta = dm->phydm_sta_info[macid];
-+ struct ra_sta_info *ra = NULL;
-+
-+ if (is_sta_active(sta)) {
-+ ra = &sta->ra_info;
-+ } else {
-+ PHYDM_DBG(dm, DBG_RA_MASK, "[Warning] %s invalid sta_info\n",
-+ __func__);
-+ return;
-+ }
-+
-+ PHYDM_DBG(dm, DBG_RA_MASK, "%s ======>\n", __func__);
-+ PHYDM_DBG(dm, DBG_RA_MASK, "MACID=%d\n", sta->mac_id);
-+
-+ /*@[Calculate TX/RX state]*/
-+ if (sta->tx_moving_average_tp > (sta->rx_moving_average_tp << 1))
-+ ra->txrx_state = TX_STATE;
-+ else if (sta->rx_moving_average_tp > (sta->tx_moving_average_tp << 1))
-+ ra->txrx_state = RX_STATE;
-+ else
-+ ra->txrx_state = BI_DIRECTION_STATE;
-+
-+ ra->is_noisy = dm->noisy_decision;
-+}
-+
-+void phydm_common_info_self_update(struct dm_struct *dm)
-+{
-+ u8 sta_cnt = 0, num_active_client = 0;
-+ u32 i, one_entry_macid = 0;
-+ u32 ma_rx_tp = 0;
-+ u32 tp_diff = 0;
-+ struct cmn_sta_info *sta;
-+
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+
-+ PADAPTER adapter = (PADAPTER)dm->adapter;
-+
-+ PMGNT_INFO mgnt_info = &((PADAPTER)adapter)->MgntInfo;
-+
-+ sta = dm->phydm_sta_info[0];
-+ if (mgnt_info->mAssoc) {
-+ sta->dm_ctrl |= STA_DM_CTRL_ACTIVE;
-+ for (i = 0; i < 6; i++)
-+ sta->mac_addr[i] = mgnt_info->Bssid[i];
-+ } else if (GetFirstClientPort(adapter)) {
-+ //void *client_adapter = GetFirstClientPort(adapter);
-+ struct _ADAPTER *client_adapter = GetFirstClientPort(adapter);
-+
-+ sta->dm_ctrl |= STA_DM_CTRL_ACTIVE;
-+ for (i = 0; i < 6; i++)
-+ sta->mac_addr[i] = client_adapter->MgntInfo.Bssid[i];
-+ } else {
-+ sta->dm_ctrl = sta->dm_ctrl & (~STA_DM_CTRL_ACTIVE);
-+ for (i = 0; i < 6; i++)
-+ sta->mac_addr[i] = 0;
-+ }
-+
-+ /* STA mode is linked to AP */
-+ if (is_sta_active(sta) && !ACTING_AS_AP(adapter))
-+ dm->bsta_state = true;
-+ else
-+ dm->bsta_state = false;
-+#endif
-+
-+ for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
-+ sta = dm->phydm_sta_info[i];
-+ if (is_sta_active(sta)) {
-+ sta_cnt++;
-+
-+ if (sta_cnt == 1)
-+ one_entry_macid = i;
-+
-+ phydm_cmn_sta_info_update(dm, (u8)i);
-+ #ifdef PHYDM_BEAMFORMING_SUPPORT
-+ /*@phydm_get_txbf_device_num(dm, (u8)i);*/
-+ #endif
-+
-+ ma_rx_tp = sta->rx_moving_average_tp +
-+ sta->tx_moving_average_tp;
-+
-+ PHYDM_DBG(dm, DBG_COMMON_FLOW,
-+ "TP[%d]: ((%d )) bit/sec\n", i, ma_rx_tp);
-+
-+ if (ma_rx_tp > ACTIVE_TP_THRESHOLD)
-+ num_active_client++;
-+ }
-+ }
-+
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+ dm->is_linked = (sta_cnt != 0) ? true : false;
-+#endif
-+
-+ if (sta_cnt == 1) {
-+ dm->is_one_entry_only = true;
-+ dm->one_entry_macid = one_entry_macid;
-+ dm->one_entry_tp = ma_rx_tp;
-+
-+ dm->tp_active_occur = 0;
-+
-+ PHYDM_DBG(dm, DBG_COMMON_FLOW,
-+ "one_entry_tp=((%d)), pre_one_entry_tp=((%d))\n",
-+ dm->one_entry_tp, dm->pre_one_entry_tp);
-+
-+ if (dm->one_entry_tp > dm->pre_one_entry_tp &&
-+ dm->pre_one_entry_tp <= 2) {
-+ tp_diff = dm->one_entry_tp - dm->pre_one_entry_tp;
-+
-+ if (tp_diff > dm->tp_active_th)
-+ dm->tp_active_occur = 1;
-+ }
-+ dm->pre_one_entry_tp = dm->one_entry_tp;
-+ } else {
-+ dm->is_one_entry_only = false;
-+ }
-+
-+ dm->pre_number_linked_client = dm->number_linked_client;
-+ dm->pre_number_active_client = dm->number_active_client;
-+
-+ dm->number_linked_client = sta_cnt;
-+ dm->number_active_client = num_active_client;
-+
-+ /*Traffic load information update*/
-+ phydm_traffic_load_decision(dm);
-+
-+ dm->phydm_sys_up_time += PHYDM_WATCH_DOG_PERIOD;
-+
-+ dm->is_dfs_band = phydm_is_dfs_band(dm);
-+ dm->phy_dbg_info.show_phy_sts_cnt = 0;
-+}
-+
-+void phydm_common_info_self_reset(struct dm_struct *dm)
-+{
-+ struct odm_phy_dbg_info *dbg_t = &dm->phy_dbg_info;
-+
-+ dbg_t->beacon_cnt_in_period = dbg_t->num_qry_beacon_pkt;
-+ dbg_t->num_qry_beacon_pkt = 0;
-+
-+ dm->rxsc_l = 0xff;
-+ dm->rxsc_20 = 0xff;
-+ dm->rxsc_40 = 0xff;
-+ dm->rxsc_80 = 0xff;
-+}
-+
-+void *
-+phydm_get_structure(struct dm_struct *dm, u8 structure_type)
-+
-+{
-+ void *structure = NULL;
-+
-+ switch (structure_type) {
-+ case PHYDM_FALSEALMCNT:
-+ structure = &dm->false_alm_cnt;
-+ break;
-+
-+ case PHYDM_CFOTRACK:
-+ structure = &dm->dm_cfo_track;
-+ break;
-+
-+ case PHYDM_ADAPTIVITY:
-+ structure = &dm->adaptivity;
-+ break;
-+
-+ case PHYDM_DFS:
-+ structure = &dm->dfs;
-+ break;
-+
-+ default:
-+ break;
-+ }
-+
-+ return structure;
-+}
-+
-+void phydm_phy_info_update(struct dm_struct *dm)
-+{
-+#if (RTL8822B_SUPPORT == 1)
-+ if (dm->support_ic_type == ODM_RTL8822B)
-+ dm->phy_dbg_info.condi_num = phydm_get_condi_num_8822b(dm);
-+#endif
-+}
-+
-+void phydm_hw_setting(struct dm_struct *dm)
-+{
-+#if (RTL8821A_SUPPORT == 1)
-+ if (dm->support_ic_type & ODM_RTL8821)
-+ odm_hw_setting_8821a(dm);
-+#endif
-+
-+#if 0 /* TODO: implementation done but may not work and do nothing with current flags. Commenting the code to match previous version behavior*/
-+#if (RTL8814A_SUPPORT == 1)
-+ if (dm->support_ic_type & ODM_RTL8814A)
-+ phydm_hwsetting_8814a(dm);
-+#endif
-+#endif
-+
-+#if (RTL8822B_SUPPORT == 1)
-+ if (dm->support_ic_type & ODM_RTL8822B)
-+ phydm_hwsetting_8822b(dm);
-+#endif
-+
-+#if (RTL8812A_SUPPORT == 1)
-+ if (dm->support_ic_type & ODM_RTL8812)
-+ phydm_hwsetting_8812a(dm);
-+#endif
-+
-+#if (RTL8197F_SUPPORT == 1)
-+ if (dm->support_ic_type & ODM_RTL8197F)
-+ phydm_hwsetting_8197f(dm);
-+#endif
-+
-+#if (RTL8192F_SUPPORT == 1)
-+ if (dm->support_ic_type & ODM_RTL8192F)
-+ phydm_hwsetting_8192f(dm);
-+#endif
-+}
-+
-+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
-+u64 phydm_supportability_init_win(
-+ void *dm_void)
-+{
-+ struct dm_struct *dm = (struct dm_struct *)dm_void;
-+ u64 support_ability = 0;
-+
-+ switch (dm->support_ic_type) {
-+/*@---------------N Series--------------------*/
-+#if (RTL8188E_SUPPORT)
-+ case ODM_RTL8188E:
-+ support_ability |=
-+ ODM_BB_DIG |
-+ ODM_BB_RA_MASK |
-+ /*ODM_BB_DYNAMIC_TXPWR |*/
-+ ODM_BB_FA_CNT |
-+ ODM_BB_RSSI_MONITOR |
-+ ODM_BB_CCK_PD |
-+ /*ODM_BB_PWR_TRAIN |*/
-+ ODM_BB_RATE_ADAPTIVE |
-+ ODM_BB_CFO_TRACKING |
-+ ODM_BB_ENV_MONITOR |
-+ ODM_BB_PRIMARY_CCA;
-+ break;
-+#endif
-+
-+#if (RTL8192E_SUPPORT)
-+ case ODM_RTL8192E:
-+ support_ability |=
-+ ODM_BB_DIG |
-+ ODM_BB_RA_MASK |
-+ /*ODM_BB_DYNAMIC_TXPWR |*/
-+ ODM_BB_FA_CNT |
-+ ODM_BB_RSSI_MONITOR |
-+ ODM_BB_CCK_PD |
-+ /*ODM_BB_PWR_TRAIN |*/
-+ ODM_BB_RATE_ADAPTIVE |
-+ ODM_BB_CFO_TRACKING |
-+ ODM_BB_ENV_MONITOR |
-+ ODM_BB_PRIMARY_CCA;
-+ break;
-+#endif
-+
-+#if (RTL8723B_SUPPORT)
-+ case ODM_RTL8723B:
-+ support_ability |=
-+ ODM_BB_DIG |
-+ ODM_BB_RA_MASK |
-+ /*ODM_BB_DYNAMIC_TXPWR |*/
-+ ODM_BB_FA_CNT |
-+ ODM_BB_RSSI_MONITOR |
-+ ODM_BB_CCK_PD |
-+ /*ODM_BB_PWR_TRAIN |*/
-+ ODM_BB_RATE_ADAPTIVE |
-+ ODM_BB_CFO_TRACKING |
-+ ODM_BB_ENV_MONITOR |
-+ ODM_BB_PRIMARY_CCA;
-+ break;
-+#endif
-+
-+#if (RTL8703B_SUPPORT)
-+ case ODM_RTL8703B:
-+ support_ability |=
-+ ODM_BB_DIG |
-+ ODM_BB_RA_MASK |
-+ /*ODM_BB_DYNAMIC_TXPWR |*/
-+ ODM_BB_FA_CNT |
-+ ODM_BB_RSSI_MONITOR |
-+ ODM_BB_CCK_PD |
-+ /*ODM_BB_PWR_TRAIN |*/
-+ ODM_BB_RATE_ADAPTIVE |
-+ ODM_BB_CFO_TRACKING |
-+ ODM_BB_ENV_MONITOR;
-+ break;
-+#endif
-+
-+#if (RTL8723D_SUPPORT)
-+ case ODM_RTL8723D:
-+ support_ability |=
-+ ODM_BB_DIG |
-+ ODM_BB_RA_MASK |
-+ /*ODM_BB_DYNAMIC_TXPWR |*/
-+ ODM_BB_FA_CNT |
-+ ODM_BB_RSSI_MONITOR |
-+ ODM_BB_CCK_PD |
-+ ODM_BB_PWR_TRAIN |
-+ ODM_BB_RATE_ADAPTIVE |
-+ ODM_BB_CFO_TRACKING |
-+ ODM_BB_ENV_MONITOR;
-+ break;
-+#endif
-+
-+#if (RTL8710B_SUPPORT)
-+ case ODM_RTL8710B:
-+ support_ability |=
-+ ODM_BB_DIG |
-+ ODM_BB_RA_MASK |
-+ /*ODM_BB_DYNAMIC_TXPWR |*/
-+ ODM_BB_FA_CNT |
-+ ODM_BB_RSSI_MONITOR |
-+ ODM_BB_CCK_PD |
-+ ODM_BB_PWR_TRAIN |
-+ ODM_BB_RATE_ADAPTIVE |
-+ ODM_BB_CFO_TRACKING |
-+ ODM_BB_ENV_MONITOR;
-+ break;
-+#endif
-+
-+#if (RTL8188F_SUPPORT)
-+ case ODM_RTL8188F:
-+ support_ability |=
-+ ODM_BB_DIG |
-+ ODM_BB_RA_MASK |
-+ /*ODM_BB_DYNAMIC_TXPWR |*/
-+ ODM_BB_FA_CNT |
-+ ODM_BB_RSSI_MONITOR |
-+ ODM_BB_CCK_PD |
-+ /*ODM_BB_PWR_TRAIN |*/
-+ ODM_BB_RATE_ADAPTIVE |
-+ ODM_BB_CFO_TRACKING |
-+ ODM_BB_ENV_MONITOR;
-+ break;
-+#endif
-+
-+#if (RTL8192F_SUPPORT)
-+ case ODM_RTL8192F:
-+ support_ability |=
-+ ODM_BB_DIG |
-+ ODM_BB_RA_MASK |
-+ ODM_BB_FA_CNT |
-+ ODM_BB_RSSI_MONITOR |
-+ ODM_BB_CCK_PD |
-+ ODM_BB_PWR_TRAIN |
-+ ODM_BB_RATE_ADAPTIVE |
-+ ODM_BB_CFO_TRACKING |
-+ ODM_BB_ADAPTIVE_SOML |
-+ ODM_BB_ENV_MONITOR;
-+ /*ODM_BB_LNA_SAT_CHK |*/
-+ /*ODM_BB_PRIMARY_CCA*/
-+
-+ break;
-+#endif
-+
-+/*@---------------AC Series-------------------*/
-+
-+#if (RTL8812A_SUPPORT || RTL8821A_SUPPORT)
-+ case ODM_RTL8812:
-+ case ODM_RTL8821:
-+ support_ability |=
-+ ODM_BB_DIG |
-+ ODM_BB_RA_MASK |
-+ ODM_BB_DYNAMIC_TXPWR |
-+ ODM_BB_FA_CNT |
-+ ODM_BB_RSSI_MONITOR |
-+ ODM_BB_CCK_PD |
-+ /*ODM_BB_PWR_TRAIN |*/
-+ ODM_BB_RATE_ADAPTIVE |
-+ ODM_BB_CFO_TRACKING |
-+ ODM_BB_ENV_MONITOR;
-+ break;
-+#endif
-+
-+#if (RTL8814A_SUPPORT)
-+ case ODM_RTL8814A:
-+ support_ability |=
-+ ODM_BB_DIG |
-+ ODM_BB_RA_MASK |
-+ ODM_BB_DYNAMIC_TXPWR |
-+ ODM_BB_FA_CNT |
-+ ODM_BB_RSSI_MONITOR |
-+ ODM_BB_CCK_PD |
-+ /*ODM_BB_PWR_TRAIN |*/
-+ ODM_BB_RATE_ADAPTIVE |
-+ ODM_BB_CFO_TRACKING |
-+ ODM_BB_ENV_MONITOR;
-+ break;
-+#endif
-+
-+#if (RTL8822B_SUPPORT)
-+ case ODM_RTL8822B:
-+ support_ability |=
-+ ODM_BB_DIG |
-+ ODM_BB_RA_MASK |
-+ /*ODM_BB_DYNAMIC_TXPWR |*/
-+ ODM_BB_FA_CNT |
-+ ODM_BB_RSSI_MONITOR |
-+ ODM_BB_CCK_PD |
-+ /*ODM_BB_PWR_TRAIN |*/
-+ /*ODM_BB_ADAPTIVE_SOML |*/
-+ ODM_BB_RATE_ADAPTIVE |
-+ ODM_BB_CFO_TRACKING |
-+ ODM_BB_ENV_MONITOR;
-+ break;
-+#endif
-+
-+#if (RTL8821C_SUPPORT)
-+ case ODM_RTL8821C:
-+ support_ability |=
-+ ODM_BB_DIG |
-+ ODM_BB_RA_MASK |
-+ /*ODM_BB_DYNAMIC_TXPWR |*/
-+ ODM_BB_FA_CNT |
-+ ODM_BB_RSSI_MONITOR |
-+ ODM_BB_CCK_PD |
-+ /*ODM_BB_PWR_TRAIN |*/
-+ ODM_BB_RATE_ADAPTIVE |
-+ ODM_BB_CFO_TRACKING |
-+ ODM_BB_ENV_MONITOR;
-+ break;
-+#endif
-+
-+/*@---------------JGR3 Series-------------------*/
-+
-+#if (RTL8822C_SUPPORT)
-+ case ODM_RTL8822C:
-+ support_ability |=
-+ ODM_BB_DIG |
-+ ODM_BB_RA_MASK |
-+ /* ODM_BB_DYNAMIC_TXPWR |*/
-+ ODM_BB_FA_CNT |
-+ ODM_BB_RSSI_MONITOR |
-+ ODM_BB_CCK_PD |
-+ ODM_BB_RATE_ADAPTIVE |
-+ ODM_BB_CFO_TRACKING |
-+ ODM_BB_ENV_MONITOR;
-+ break;
-+#endif
-+
-+#if (RTL8814B_SUPPORT)
-+ case ODM_RTL8814B:
-+ support_ability |=
-+ ODM_BB_DIG |
-+ ODM_BB_RA_MASK |
-+ /*ODM_BB_DYNAMIC_TXPWR |*/
-+ ODM_BB_FA_CNT |
-+ ODM_BB_RSSI_MONITOR |
-+ /*ODM_BB_CCK_PD |*/
-+ /*ODM_BB_PWR_TRAIN |*/
-+ ODM_BB_RATE_ADAPTIVE |
-+ ODM_BB_CFO_TRACKING;
-+ /*ODM_BB_ENV_MONITOR;*/
-+ break;
-+#endif
-+
-+ default:
-+ support_ability |=
-+ ODM_BB_DIG |
-+ ODM_BB_RA_MASK |
-+ /*ODM_BB_DYNAMIC_TXPWR |*/
-+ ODM_BB_FA_CNT |
-+ ODM_BB_RSSI_MONITOR |
-+ ODM_BB_CCK_PD |
-+ /*ODM_BB_PWR_TRAIN |*/
-+ ODM_BB_RATE_ADAPTIVE |
-+ ODM_BB_CFO_TRACKING |
-+ ODM_BB_ENV_MONITOR;
-+
-+ pr_debug("[Warning] Supportability Init Warning !!!\n");
-+ break;
-+ }
-+
-+ return support_ability;
-+}
-+#endif
-+
-+#if (DM_ODM_SUPPORT_TYPE & (ODM_CE))
-+u64 phydm_supportability_init_ce(void *dm_void)
-+{
-+ struct dm_struct *dm = (struct dm_struct *)dm_void;
-+ u64 support_ability = 0;
-+
-+ switch (dm->support_ic_type) {
-+/*@---------------N Series--------------------*/
-+#if (RTL8188E_SUPPORT)
-+ case ODM_RTL8188E:
-+ support_ability |=
-+ ODM_BB_DIG |
-+ ODM_BB_RA_MASK |
-+ /*@ODM_BB_DYNAMIC_TXPWR |*/
-+ ODM_BB_FA_CNT |
-+ ODM_BB_RSSI_MONITOR |
-+ ODM_BB_CCK_PD |
-+ /*@ODM_BB_PWR_TRAIN |*/
-+ ODM_BB_RATE_ADAPTIVE |
-+ ODM_BB_CFO_TRACKING |
-+ ODM_BB_ENV_MONITOR |
-+ ODM_BB_PRIMARY_CCA;
-+ break;
-+#endif
-+
-+#if (RTL8192E_SUPPORT)
-+ case ODM_RTL8192E:
-+ support_ability |=
-+ ODM_BB_DIG |
-+ ODM_BB_RA_MASK |
-+ /*@ODM_BB_DYNAMIC_TXPWR |*/
-+ ODM_BB_FA_CNT |
-+ ODM_BB_RSSI_MONITOR |
-+ ODM_BB_CCK_PD |
-+ /*@ODM_BB_PWR_TRAIN |*/
-+ ODM_BB_RATE_ADAPTIVE |
-+ ODM_BB_CFO_TRACKING |
-+ ODM_BB_ENV_MONITOR |
-+ ODM_BB_PRIMARY_CCA;
-+ break;
-+#endif
-+
-+#if (RTL8723B_SUPPORT)
-+ case ODM_RTL8723B:
-+ support_ability |=
-+ ODM_BB_DIG |
-+ ODM_BB_RA_MASK |
-+ /*@ODM_BB_DYNAMIC_TXPWR |*/
-+ ODM_BB_FA_CNT |
-+ ODM_BB_RSSI_MONITOR |
-+ ODM_BB_CCK_PD |
-+ /*@ODM_BB_PWR_TRAIN |*/
-+ ODM_BB_RATE_ADAPTIVE |
-+ ODM_BB_CFO_TRACKING |
-+ ODM_BB_ENV_MONITOR |
-+ ODM_BB_PRIMARY_CCA;
-+ break;
-+#endif
-+
-+#if (RTL8703B_SUPPORT)
-+ case ODM_RTL8703B:
-+ support_ability |=
-+ ODM_BB_DIG |
-+ ODM_BB_RA_MASK |
-+ /*@ODM_BB_DYNAMIC_TXPWR |*/
-+ ODM_BB_FA_CNT |
-+ ODM_BB_RSSI_MONITOR |
-+ ODM_BB_CCK_PD |
-+ /*@ODM_BB_PWR_TRAIN |*/
-+ ODM_BB_RATE_ADAPTIVE |
-+ ODM_BB_CFO_TRACKING |
-+ ODM_BB_ENV_MONITOR;
-+ break;
-+#endif
-+
-+#if (RTL8723D_SUPPORT)
-+ case ODM_RTL8723D:
-+ support_ability |=
-+ ODM_BB_DIG |
-+ ODM_BB_RA_MASK |
-+ /*@ODM_BB_DYNAMIC_TXPWR |*/
-+ ODM_BB_FA_CNT |
-+ ODM_BB_RSSI_MONITOR |
-+ ODM_BB_CCK_PD |
-+ ODM_BB_PWR_TRAIN |
-+ ODM_BB_RATE_ADAPTIVE |
-+ ODM_BB_CFO_TRACKING |
-+ ODM_BB_ENV_MONITOR;
-+ break;
-+#endif
-+
-+#if (RTL8710B_SUPPORT)
-+ case ODM_RTL8710B:
-+ support_ability |=
-+ ODM_BB_DIG |
-+ ODM_BB_RA_MASK |
-+ /*@ODM_BB_DYNAMIC_TXPWR |*/
-+ ODM_BB_FA_CNT |
-+ ODM_BB_RSSI_MONITOR |
-+ ODM_BB_CCK_PD |
-+ /*@ODM_BB_PWR_TRAIN |*/
-+ ODM_BB_RATE_ADAPTIVE |
-+ ODM_BB_CFO_TRACKING |
-+ ODM_BB_ENV_MONITOR;
-+ break;
-+#endif
-+
-+#if (RTL8188F_SUPPORT)
-+ case ODM_RTL8188F:
-+ support_ability |=
-+ ODM_BB_DIG |
-+ ODM_BB_RA_MASK |
-+ /*@ODM_BB_DYNAMIC_TXPWR |*/
-+ ODM_BB_FA_CNT |
-+ ODM_BB_RSSI_MONITOR |
-+ ODM_BB_CCK_PD |
-+ /*@ODM_BB_PWR_TRAIN |*/
-+ ODM_BB_RATE_ADAPTIVE |
-+ ODM_BB_CFO_TRACKING |
-+ ODM_BB_ENV_MONITOR;
-+ break;
-+#endif
-+
-+#if (RTL8192F_SUPPORT)
-+ case ODM_RTL8192F:
-+ support_ability |=
-+ ODM_BB_DIG |
-+ ODM_BB_RA_MASK |
-+ ODM_BB_FA_CNT |
-+ ODM_BB_RSSI_MONITOR |
-+ ODM_BB_CCK_PD |
-+ ODM_BB_PWR_TRAIN |
-+ ODM_BB_RATE_ADAPTIVE |
-+ ODM_BB_CFO_TRACKING |
-+ /*@ODM_BB_ADAPTIVE_SOML |*/
-+ ODM_BB_ENV_MONITOR;
-+ /*@ODM_BB_LNA_SAT_CHK |*/
-+ /*@ODM_BB_PRIMARY_CCA*/
-+ break;
-+#endif
-+/*@---------------AC Series-------------------*/
-+
-+#if (RTL8812A_SUPPORT || RTL8821A_SUPPORT)
-+ case ODM_RTL8812:
-+ case ODM_RTL8821:
-+ support_ability |=
-+ ODM_BB_DIG |
-+ ODM_BB_RA_MASK |
-+ /*@ODM_BB_DYNAMIC_TXPWR |*/
-+ ODM_BB_FA_CNT |
-+ ODM_BB_RSSI_MONITOR |
-+ ODM_BB_CCK_PD |
-+ /*@ODM_BB_PWR_TRAIN |*/
-+ ODM_BB_RATE_ADAPTIVE |
-+ ODM_BB_CFO_TRACKING |
-+ ODM_BB_ENV_MONITOR;
-+ break;
-+#endif
-+
-+#if (RTL8814A_SUPPORT)
-+ case ODM_RTL8814A:
-+ support_ability |=
-+ ODM_BB_DIG |
-+ ODM_BB_RA_MASK |
-+ /*@ODM_BB_DYNAMIC_TXPWR |*/
-+ ODM_BB_FA_CNT |
-+ ODM_BB_RSSI_MONITOR |
-+ ODM_BB_CCK_PD |
-+ /*@ODM_BB_PWR_TRAIN |*/
-+ ODM_BB_RATE_ADAPTIVE |
-+ ODM_BB_CFO_TRACKING |
-+ ODM_BB_ENV_MONITOR;
-+ break;
-+#endif
-+
-+#if (RTL8822B_SUPPORT)
-+ case ODM_RTL8822B:
-+ support_ability |=
-+ ODM_BB_DIG |
-+ ODM_BB_RA_MASK |
-+ /*@ODM_BB_DYNAMIC_TXPWR |*/
-+ ODM_BB_FA_CNT |
-+ ODM_BB_RSSI_MONITOR |
-+ ODM_BB_CCK_PD |
-+ /*@ODM_BB_PWR_TRAIN |*/
-+ ODM_BB_RATE_ADAPTIVE |
-+ ODM_BB_CFO_TRACKING |
-+ ODM_BB_ENV_MONITOR;
-+ break;
-+#endif
-+
-+#if (RTL8821C_SUPPORT)
-+ case ODM_RTL8821C:
-+ support_ability |=
-+ ODM_BB_DIG |
-+ ODM_BB_RA_MASK |
-+ /*@ODM_BB_DYNAMIC_TXPWR |*/
-+ ODM_BB_FA_CNT |
-+ ODM_BB_RSSI_MONITOR |
-+ ODM_BB_CCK_PD |
-+ /*@ODM_BB_PWR_TRAIN |*/
-+ ODM_BB_RATE_ADAPTIVE |
-+ ODM_BB_CFO_TRACKING |
-+ ODM_BB_ENV_MONITOR;
-+ break;
-+#endif
-+
-+/*@---------------JGR3 Series-------------------*/
-+
-+#if (RTL8822C_SUPPORT)
-+ case ODM_RTL8822C:
-+ support_ability |=
-+ ODM_BB_DIG |
-+ ODM_BB_RA_MASK |
-+ /* ODM_BB_DYNAMIC_TXPWR |*/
-+ ODM_BB_FA_CNT |
-+ ODM_BB_RSSI_MONITOR |
-+ ODM_BB_CCK_PD |
-+ ODM_BB_RATE_ADAPTIVE |
-+ ODM_BB_CFO_TRACKING |
-+ ODM_BB_ENV_MONITOR;
-+ break;
-+#endif
-+
-+#if (RTL8814B_SUPPORT)
-+ case ODM_RTL8814B:
-+ support_ability |=
-+ ODM_BB_DIG |
-+ ODM_BB_RA_MASK |
-+ /*@ODM_BB_DYNAMIC_TXPWR |*/
-+ ODM_BB_FA_CNT |
-+ ODM_BB_RSSI_MONITOR;
-+ /*ODM_BB_CCK_PD |*/
-+ /*@ODM_BB_PWR_TRAIN |*/
-+ /*ODM_BB_RATE_ADAPTIVE |*/
-+ /*ODM_BB_CFO_TRACKING |*/
-+ /*ODM_BB_ENV_MONITOR;*/
-+ break;
-+#endif
-+
-+ default:
-+ support_ability |=
-+ ODM_BB_DIG |
-+ ODM_BB_RA_MASK |
-+ /*@ODM_BB_DYNAMIC_TXPWR |*/
-+ ODM_BB_FA_CNT |
-+ ODM_BB_RSSI_MONITOR |
-+ ODM_BB_CCK_PD |
-+ /*@ODM_BB_PWR_TRAIN |*/
-+ ODM_BB_RATE_ADAPTIVE |
-+ ODM_BB_CFO_TRACKING |
-+ ODM_BB_ENV_MONITOR;
-+
-+ pr_debug("[Warning] Supportability Init Warning !!!\n");
-+ break;
-+ }
-+
-+ return support_ability;
-+}
-+#endif
-+
-+#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
-+u64 phydm_supportability_init_ap(
-+ void *dm_void)
-+{
-+ struct dm_struct *dm = (struct dm_struct *)dm_void;
-+ u64 support_ability = 0;
-+
-+ switch (dm->support_ic_type) {
-+/*@---------------N Series--------------------*/
-+#if (RTL8188E_SUPPORT)
-+ case ODM_RTL8188E:
-+ support_ability |=
-+ ODM_BB_DIG |
-+ ODM_BB_RA_MASK |
-+ ODM_BB_FA_CNT |
-+ ODM_BB_RSSI_MONITOR |
-+ ODM_BB_CCK_PD |
-+ /*ODM_BB_PWR_TRAIN |*/
-+ ODM_BB_RATE_ADAPTIVE |
-+ ODM_BB_CFO_TRACKING |
-+ ODM_BB_ENV_MONITOR |
-+ ODM_BB_PRIMARY_CCA;
-+ break;
-+#endif
-+
-+#if (RTL8192E_SUPPORT)
-+ case ODM_RTL8192E:
-+ support_ability |=
-+ ODM_BB_DIG |
-+ ODM_BB_RA_MASK |
-+ ODM_BB_FA_CNT |
-+ ODM_BB_RSSI_MONITOR |
-+ ODM_BB_CCK_PD |
-+ /*ODM_BB_PWR_TRAIN |*/
-+ ODM_BB_RATE_ADAPTIVE |
-+ ODM_BB_CFO_TRACKING |
-+ ODM_BB_ENV_MONITOR |
-+ ODM_BB_PRIMARY_CCA;
-+ break;
-+#endif
-+
-+#if (RTL8723B_SUPPORT)
-+ case ODM_RTL8723B:
-+ support_ability |=
-+ ODM_BB_DIG |
-+ ODM_BB_RA_MASK |
-+ ODM_BB_FA_CNT |
-+ ODM_BB_RSSI_MONITOR |
-+ ODM_BB_CCK_PD |
-+ /*ODM_BB_PWR_TRAIN |*/
-+ ODM_BB_RATE_ADAPTIVE |
-+ ODM_BB_CFO_TRACKING |
-+ ODM_BB_ENV_MONITOR;
-+ break;
-+#endif
-+
-+#if (RTL8198F_SUPPORT || RTL8197F_SUPPORT)
-+ case ODM_RTL8198F:
-+ support_ability |=
-+ /*ODM_BB_DIG |*/
-+ ODM_BB_RA_MASK |
-+ ODM_BB_FA_CNT |
-+ ODM_BB_RSSI_MONITOR;
-+ /*ODM_BB_CCK_PD |*/
-+ /*ODM_BB_PWR_TRAIN |*/
-+ /*ODM_BB_RATE_ADAPTIVE |*/
-+ /*ODM_BB_CFO_TRACKING |*/
-+ /*ODM_BB_ADAPTIVE_SOML |*/
-+ /*ODM_BB_ENV_MONITOR |*/
-+ /*ODM_BB_LNA_SAT_CHK |*/
-+ /*ODM_BB_PRIMARY_CCA;*/
-+ break;
-+ case ODM_RTL8197F:
-+ support_ability |=
-+ ODM_BB_DIG |
-+ ODM_BB_RA_MASK |
-+ ODM_BB_FA_CNT |
-+ ODM_BB_RSSI_MONITOR |
-+ ODM_BB_CCK_PD |
-+ /*ODM_BB_PWR_TRAIN |*/
-+ ODM_BB_RATE_ADAPTIVE |
-+ ODM_BB_CFO_TRACKING |
-+ ODM_BB_ADAPTIVE_SOML |
-+ ODM_BB_ENV_MONITOR |
-+ ODM_BB_LNA_SAT_CHK |
-+ ODM_BB_PRIMARY_CCA;
-+ break;
-+#endif
-+
-+#if (RTL8192F_SUPPORT)
-+ case ODM_RTL8192F:
-+ support_ability |=
-+ ODM_BB_DIG |
-+ ODM_BB_RA_MASK |
-+ ODM_BB_FA_CNT |
-+ ODM_BB_RSSI_MONITOR |
-+ ODM_BB_CCK_PD |
-+ /*ODM_BB_PWR_TRAIN |*/
-+ ODM_BB_RATE_ADAPTIVE |
-+ /*ODM_BB_CFO_TRACKING |*/
-+ ODM_BB_ADAPTIVE_SOML |
-+ /*ODM_BB_ENV_MONITOR |*/
-+ /*ODM_BB_LNA_SAT_CHK |*/
-+ /*ODM_BB_PRIMARY_CCA |*/
-+ 0;
-+ break;
-+#endif
-+
-+/*@---------------AC Series-------------------*/
-+
-+#if (RTL8881A_SUPPORT)
-+ case ODM_RTL8881A:
-+ support_ability |=
-+ ODM_BB_DIG |
-+ ODM_BB_RA_MASK |
-+ ODM_BB_FA_CNT |
-+ ODM_BB_RSSI_MONITOR |
-+ ODM_BB_CCK_PD |
-+ /*ODM_BB_PWR_TRAIN |*/
-+ ODM_BB_RATE_ADAPTIVE |
-+ ODM_BB_CFO_TRACKING |
-+ ODM_BB_ENV_MONITOR;
-+ break;
-+#endif
-+
-+#if (RTL8814A_SUPPORT)
-+ case ODM_RTL8814A:
-+ support_ability |=
-+ ODM_BB_DIG |
-+ ODM_BB_RA_MASK |
-+ ODM_BB_FA_CNT |
-+ ODM_BB_RSSI_MONITOR |
-+ ODM_BB_CCK_PD |
-+ /*ODM_BB_PWR_TRAIN |*/
-+ ODM_BB_RATE_ADAPTIVE |
-+ ODM_BB_CFO_TRACKING |
-+ ODM_BB_ENV_MONITOR;
-+ break;
-+#endif
-+
-+#if (RTL8822B_SUPPORT)
-+ case ODM_RTL8822B:
-+ support_ability |=
-+ ODM_BB_DIG |
-+ ODM_BB_RA_MASK |
-+ ODM_BB_FA_CNT |
-+ ODM_BB_RSSI_MONITOR |
-+ ODM_BB_CCK_PD |
-+ /*ODM_BB_PWR_TRAIN |*/
-+ /*ODM_BB_ADAPTIVE_SOML |*/
-+ ODM_BB_RATE_ADAPTIVE |
-+ ODM_BB_CFO_TRACKING |
-+ ODM_BB_ENV_MONITOR;
-+ break;
-+#endif
-+
-+#if (RTL8821C_SUPPORT)
-+ case ODM_RTL8821C:
-+ support_ability |=
-+ ODM_BB_DIG |
-+ ODM_BB_RA_MASK |
-+ ODM_BB_FA_CNT |
-+ ODM_BB_RSSI_MONITOR |
-+ ODM_BB_CCK_PD |
-+ /*ODM_BB_PWR_TRAIN |*/
-+ ODM_BB_RATE_ADAPTIVE |
-+ ODM_BB_CFO_TRACKING |
-+ ODM_BB_ENV_MONITOR;
-+
-+ break;
-+#endif
-+
-+/*@---------------JGR3 Series-------------------*/
-+
-+#if (RTL8814B_SUPPORT)
-+ case ODM_RTL8814B:
-+ support_ability |=
-+ ODM_BB_DIG |
-+ ODM_BB_RA_MASK |
-+ ODM_BB_FA_CNT |
-+ ODM_BB_RSSI_MONITOR;
-+ /*ODM_BB_CCK_PD |*/
-+ /*ODM_BB_PWR_TRAIN |*/
-+ /*ODM_BB_RATE_ADAPTIVE |*/
-+ /*ODM_BB_CFO_TRACKING |*/
-+ /*ODM_BB_ENV_MONITOR;*/
-+ break;
-+#endif
-+
-+ default:
-+ support_ability |=
-+ ODM_BB_DIG |
-+ ODM_BB_RA_MASK |
-+ ODM_BB_FA_CNT |
-+ ODM_BB_RSSI_MONITOR |
-+ ODM_BB_CCK_PD |
-+ /*ODM_BB_PWR_TRAIN |*/
-+ ODM_BB_RATE_ADAPTIVE |
-+ ODM_BB_CFO_TRACKING |
-+ ODM_BB_ENV_MONITOR;
-+
-+ pr_debug("[Warning] Supportability Init Warning !!!\n");
-+ break;
-+ }
-+
-+#if 0
-+ /*@[Config Antenna Diveristy]*/
-+ if (*dm->enable_antdiv)
-+ support_ability |= ODM_BB_ANT_DIV;
-+
-+ /*@[Config Adaptivity]*/
-+ if (*dm->enable_adaptivity)
-+ support_ability |= ODM_BB_ADAPTIVITY;
-+#endif
-+
-+ return support_ability;
-+}
-+#endif
-+
-+#if (DM_ODM_SUPPORT_TYPE & (ODM_IOT))
-+u64 phydm_supportability_init_iot(
-+ void *dm_void)
-+{
-+ struct dm_struct *dm = (struct dm_struct *)dm_void;
-+ u64 support_ability = 0;
-+
-+ switch (dm->support_ic_type) {
-+#if (RTL8710B_SUPPORT)
-+ case ODM_RTL8710B:
-+ support_ability |=
-+ ODM_BB_DIG |
-+ ODM_BB_RA_MASK |
-+ /*ODM_BB_DYNAMIC_TXPWR |*/
-+ ODM_BB_FA_CNT |
-+ ODM_BB_RSSI_MONITOR |
-+ ODM_BB_CCK_PD |
-+ /*ODM_BB_PWR_TRAIN |*/
-+ ODM_BB_RATE_ADAPTIVE |
-+ ODM_BB_CFO_TRACKING |
-+ ODM_BB_ENV_MONITOR;
-+ break;
-+#endif
-+
-+#if (RTL8195A_SUPPORT)
-+ case ODM_RTL8195A:
-+ support_ability |=
-+ ODM_BB_DIG |
-+ ODM_BB_RA_MASK |
-+ /*ODM_BB_DYNAMIC_TXPWR |*/
-+ ODM_BB_FA_CNT |
-+ ODM_BB_RSSI_MONITOR |
-+ ODM_BB_CCK_PD |
-+ /*ODM_BB_PWR_TRAIN |*/
-+ ODM_BB_RATE_ADAPTIVE |
-+ ODM_BB_CFO_TRACKING |
-+ ODM_BB_ENV_MONITOR;
-+ break;
-+#endif
-+
-+#if (RTL8195B_SUPPORT)
-+ case ODM_RTL8195B:
-+ support_ability |=
-+ ODM_BB_DIG |
-+ ODM_BB_RA_MASK |
-+ /*ODM_BB_DYNAMIC_TXPWR |*/
-+ ODM_BB_FA_CNT |
-+ ODM_BB_RSSI_MONITOR |
-+ ODM_BB_CCK_PD |
-+ /*ODM_BB_PWR_TRAIN |*/
-+ ODM_BB_RATE_ADAPTIVE |
-+ ODM_BB_CFO_TRACKING;
-+ /*ODM_BB_ENV_MONITOR*/
-+ break;
-+#endif
-+
-+#if (RTL8721D_SUPPORT)
-+ case ODM_RTL8721D:
-+ support_ability |=
-+ ODM_BB_DIG |
-+ ODM_BB_RA_MASK |
-+ /*ODM_BB_DYNAMIC_TXPWR |*/
-+ ODM_BB_FA_CNT |
-+ ODM_BB_RSSI_MONITOR |
-+ ODM_BB_CCK_PD |
-+ /*ODM_BB_PWR_TRAIN |*/
-+ ODM_BB_RATE_ADAPTIVE |
-+ ODM_BB_CFO_TRACKING |
-+ ODM_BB_ENV_MONITOR;
-+ break;
-+#endif
-+
-+ default:
-+ support_ability |=
-+ ODM_BB_DIG |
-+ ODM_BB_RA_MASK |
-+ /*ODM_BB_DYNAMIC_TXPWR |*/
-+ ODM_BB_FA_CNT |
-+ ODM_BB_RSSI_MONITOR |
-+ ODM_BB_CCK_PD |
-+ /*ODM_BB_PWR_TRAIN |*/
-+ ODM_BB_RATE_ADAPTIVE |
-+ ODM_BB_CFO_TRACKING |
-+ ODM_BB_ENV_MONITOR;
-+
-+ pr_debug("[Warning] Supportability Init Warning !!!\n");
-+ break;
-+ }
-+
-+ return support_ability;
-+}
-+#endif
-+
-+void phydm_fwoffload_ability_init(struct dm_struct *dm,
-+ enum phydm_offload_ability offload_ability)
-+{
-+ switch (offload_ability) {
-+ case PHYDM_PHY_PARAM_OFFLOAD:
-+ if (dm->support_ic_type &
-+ (ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8821C))
-+ dm->fw_offload_ability |= PHYDM_PHY_PARAM_OFFLOAD;
-+ break;
-+
-+ case PHYDM_RF_IQK_OFFLOAD:
-+ dm->fw_offload_ability |= PHYDM_RF_IQK_OFFLOAD;
-+ break;
-+
-+ default:
-+ PHYDM_DBG(dm, ODM_COMP_INIT, "fwofflad, wrong init type!!\n");
-+ break;
-+ }
-+
-+ PHYDM_DBG(dm, ODM_COMP_INIT, "fw_offload_ability = %x\n",
-+ dm->fw_offload_ability);
-+}
-+
-+void phydm_fwoffload_ability_clear(struct dm_struct *dm,
-+ enum phydm_offload_ability offload_ability)
-+{
-+ switch (offload_ability) {
-+ case PHYDM_PHY_PARAM_OFFLOAD:
-+ if (dm->support_ic_type &
-+ (ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8821C))
-+ dm->fw_offload_ability &= (~PHYDM_PHY_PARAM_OFFLOAD);
-+ break;
-+
-+ case PHYDM_RF_IQK_OFFLOAD:
-+ dm->fw_offload_ability &= (~PHYDM_RF_IQK_OFFLOAD);
-+ break;
-+
-+ default:
-+ PHYDM_DBG(dm, ODM_COMP_INIT, "fwofflad, wrong init type!!\n");
-+ break;
-+ }
-+
-+ PHYDM_DBG(dm, ODM_COMP_INIT, "fw_offload_ability = %x\n",
-+ dm->fw_offload_ability);
-+}
-+
-+void phydm_supportability_init(void *dm_void)
-+{
-+ struct dm_struct *dm = (struct dm_struct *)dm_void;
-+ u64 support_ability;
-+
-+ if (*dm->mp_mode) {
-+ support_ability = 0;
-+ } else {
-+ #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
-+ support_ability = phydm_supportability_init_win(dm);
-+ #elif (DM_ODM_SUPPORT_TYPE & (ODM_AP))
-+ support_ability = phydm_supportability_init_ap(dm);
-+ #elif(DM_ODM_SUPPORT_TYPE & (ODM_CE))
-+ support_ability = phydm_supportability_init_ce(dm);
-+ #elif(DM_ODM_SUPPORT_TYPE & (ODM_IOT))
-+ support_ability = phydm_supportability_init_iot(dm);
-+ #endif
-+
-+ /*@[Config Antenna Diversity]*/
-+ if (IS_FUNC_EN(dm->enable_antdiv))
-+ support_ability |= ODM_BB_ANT_DIV;
-+
-+ /*@[Config TXpath Diversity]*/
-+ if (IS_FUNC_EN(dm->enable_pathdiv))
-+ support_ability |= ODM_BB_PATH_DIV;
-+
-+ /*@[Config Adaptive SOML]*/
-+ if (IS_FUNC_EN(dm->en_adap_soml))
-+ support_ability |= ODM_BB_ADAPTIVE_SOML;
-+
-+ /* @[Config Adaptivity]*/
-+ if (IS_FUNC_EN(dm->enable_adaptivity))
-+ support_ability |= ODM_BB_ADAPTIVITY;
-+ }
-+ odm_cmn_info_init(dm, ODM_CMNINFO_ABILITY, support_ability);
-+ PHYDM_DBG(dm, ODM_COMP_INIT, "IC=0x%x, mp=%d, Supportability=0x%llx\n",
-+ dm->support_ic_type, *dm->mp_mode, dm->support_ability);
-+}
-+
-+void phydm_rfe_init(void *dm_void)
-+{
-+ struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+ PHYDM_DBG(dm, ODM_COMP_INIT, "RFE_Init\n");
-+#if (RTL8822B_SUPPORT == 1)
-+ if (dm->support_ic_type == ODM_RTL8822B)
-+ phydm_rfe_8822b_init(dm);
-+#endif
-+}
-+
-+void phydm_dm_early_init(struct dm_struct *dm)
-+{
-+
-+}
-+
-+void odm_dm_init(struct dm_struct *dm)
-+{
-+ halrf_init(dm);
-+ phydm_supportability_init(dm);
-+ phydm_rfe_init(dm);
-+ phydm_common_info_self_init(dm);
-+ phydm_rx_phy_status_init(dm);
-+#ifdef PHYDM_AUTO_DEGBUG
-+ phydm_auto_dbg_engine_init(dm);
-+#endif
-+ phydm_dig_init(dm);
-+#ifdef PHYDM_SUPPORT_CCKPD
-+ phydm_cck_pd_init(dm);
-+#endif
-+ phydm_env_monitor_init(dm);
-+ phydm_adaptivity_init(dm);
-+ phydm_ra_info_init(dm);
-+ phydm_rssi_monitor_init(dm);
-+ phydm_cfo_tracking_init(dm);
-+ phydm_rf_init(dm);
-+ phydm_dc_cancellation(dm);
-+#ifdef PHYDM_TXA_CALIBRATION
-+ phydm_txcurrentcalibration(dm);
-+ phydm_get_pa_bias_offset(dm);
-+#endif
-+#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
-+ odm_antenna_diversity_init(dm);
-+#endif
-+#ifdef CONFIG_ADAPTIVE_SOML
-+ phydm_adaptive_soml_init(dm);
-+#endif
-+#ifdef CONFIG_PATH_DIVERSITY
-+ phydm_tx_path_diversity_init(dm);
-+#endif
-+#ifdef CONFIG_DYNAMIC_TX_TWR
-+ phydm_dynamic_tx_power_init(dm);
-+#endif
-+#if (PHYDM_LA_MODE_SUPPORT == 1)
-+ adc_smp_init(dm);
-+#endif
-+
-+#ifdef PHYDM_BEAMFORMING_VERSION1
-+ phydm_beamforming_init(dm);
-+#endif
-+
-+#if (RTL8188E_SUPPORT == 1)
-+ odm_ra_info_init_all(dm);
-+#endif
-+#ifdef PHYDM_PRIMARY_CCA
-+ phydm_primary_cca_init(dm);
-+#endif
-+#ifdef CONFIG_PSD_TOOL
-+ phydm_psd_init(dm);
-+#endif
-+
-+#ifdef CONFIG_SMART_ANTENNA
-+ phydm_smt_ant_init(dm);
-+#endif
-+#ifdef PHYDM_LNA_SAT_CHK_SUPPORT
-+ phydm_lna_sat_check_init(dm);
-+#endif
-+#ifdef CONFIG_MCC_DM
-+ #if (RTL8822B_SUPPORT == 1)
-+ phydm_mcc_init(dm);
-+ #endif
-+#endif
-+}
-+
-+void odm_dm_reset(struct dm_struct *dm)
-+{
-+ struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
-+
-+ #ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
-+ odm_ant_div_reset(dm);
-+ #endif
-+ phydm_set_edcca_threshold_api(dm, dig_t->cur_ig_value);
-+}
-+
-+void phydm_supportability_en(void *dm_void, char input[][16], u32 *_used,
-+ char *output, u32 *_out_len)
-+{
-+ struct dm_struct *dm = (struct dm_struct *)dm_void;
-+ u32 dm_value[10] = {0};
-+ u64 pre_support_ability, one = 1;
-+ u64 comp = 0;
-+ u32 used = *_used;
-+ u32 out_len = *_out_len;
-+ u8 i;
-+
-+ for (i = 0; i < 5; i++) {
-+ if (input[i + 1])
-+ PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &dm_value[i]);
-+ }
-+
-+ pre_support_ability = dm->support_ability;
-+ comp = dm->support_ability;
-+
-+ PDM_SNPF(out_len, used, output + used, out_len - used,
-+ "\n================================\n");
-+
-+ if (dm_value[0] == 100) {
-+ PDM_SNPF(out_len, used, output + used, out_len - used,
-+ "[Supportability] PhyDM Selection\n");
-+ PDM_SNPF(out_len, used, output + used, out_len - used,
-+ "================================\n");
-+ PDM_SNPF(out_len, used, output + used, out_len - used,
-+ "00. (( %s ))DIG\n",
-+ ((comp & ODM_BB_DIG) ? ("V") : (".")));
-+ PDM_SNPF(out_len, used, output + used, out_len - used,
-+ "01. (( %s ))RA_MASK\n",
-+ ((comp & ODM_BB_RA_MASK) ? ("V") : (".")));
-+ PDM_SNPF(out_len, used, output + used, out_len - used,
-+ "02. (( %s ))DYN_TXPWR\n",
-+ ((comp & ODM_BB_DYNAMIC_TXPWR) ? ("V") : (".")));
-+ PDM_SNPF(out_len, used, output + used, out_len - used,
-+ "03. (( %s ))FA_CNT\n",
-+ ((comp & ODM_BB_FA_CNT) ? ("V") : (".")));
-+ PDM_SNPF(out_len, used, output + used, out_len - used,
-+ "04. (( %s ))RSSI_MNTR\n",
-+ ((comp & ODM_BB_RSSI_MONITOR) ? ("V") : (".")));
-+ PDM_SNPF(out_len, used, output + used, out_len - used,
-+ "05. (( %s ))CCK_PD\n",
-+ ((comp & ODM_BB_CCK_PD) ? ("V") : (".")));
-+ PDM_SNPF(out_len, used, output + used, out_len - used,
-+ "06. (( %s ))ANT_DIV\n",
-+ ((comp & ODM_BB_ANT_DIV) ? ("V") : (".")));
-+ PDM_SNPF(out_len, used, output + used, out_len - used,
-+ "07. (( %s ))SMT_ANT\n",
-+ ((comp & ODM_BB_SMT_ANT) ? ("V") : (".")));
-+ PDM_SNPF(out_len, used, output + used, out_len - used,
-+ "08. (( %s ))PWR_TRAIN\n",
-+ ((comp & ODM_BB_PWR_TRAIN) ? ("V") : (".")));
-+ PDM_SNPF(out_len, used, output + used, out_len - used,
-+ "09. (( %s ))RA\n",
-+ ((comp & ODM_BB_RATE_ADAPTIVE) ? ("V") : (".")));
-+ PDM_SNPF(out_len, used, output + used, out_len - used,
-+ "10. (( %s ))PATH_DIV\n",
-+ ((comp & ODM_BB_PATH_DIV) ? ("V") : (".")));
-+ PDM_SNPF(out_len, used, output + used, out_len - used,
-+ "11. (( %s ))DFS\n",
-+ ((comp & ODM_BB_DFS) ? ("V") : (".")));
-+ PDM_SNPF(out_len, used, output + used, out_len - used,
-+ "12. (( %s ))DYN_ARFR\n",
-+ ((comp & ODM_BB_DYNAMIC_ARFR) ? ("V") : (".")));
-+ PDM_SNPF(out_len, used, output + used, out_len - used,
-+ "13. (( %s ))ADAPTIVITY\n",
-+ ((comp & ODM_BB_ADAPTIVITY) ? ("V") : (".")));
-+ PDM_SNPF(out_len, used, output + used, out_len - used,
-+ "14. (( %s ))CFO_TRACK\n",
-+ ((comp & ODM_BB_CFO_TRACKING) ? ("V") : (".")));
-+ PDM_SNPF(out_len, used, output + used, out_len - used,
-+ "15. (( %s ))ENV_MONITOR\n",
-+ ((comp & ODM_BB_ENV_MONITOR) ? ("V") : (".")));
-+ PDM_SNPF(out_len, used, output + used, out_len - used,
-+ "16. (( %s ))PRI_CCA\n",
-+ ((comp & ODM_BB_PRIMARY_CCA) ? ("V") : (".")));
-+ PDM_SNPF(out_len, used, output + used, out_len - used,
-+ "17. (( %s ))ADPTV_SOML\n",
-+ ((comp & ODM_BB_ADAPTIVE_SOML) ? ("V") : (".")));
-+ PDM_SNPF(out_len, used, output + used, out_len - used,
-+ "18. (( %s ))LNA_SAT_CHK\n",
-+ ((comp & ODM_BB_LNA_SAT_CHK) ? ("V") : (".")));
-+
-+ PDM_SNPF(out_len, used, output + used, out_len - used,
-+ "================================\n");
-+ PDM_SNPF(out_len, used, output + used, out_len - used,
-+ "[Supportability] PhyDM offload ability\n");
-+ PDM_SNPF(out_len, used, output + used, out_len - used,
-+ "================================\n");
-+
-+ PDM_SNPF(out_len, used, output + used, out_len - used,
-+ "00. (( %s ))PHY PARAM OFFLOAD\n",
-+ ((dm->fw_offload_ability & PHYDM_PHY_PARAM_OFFLOAD) ?
-+ ("V") : (".")));
-+ PDM_SNPF(out_len, used, output + used, out_len - used,
-+ "01. (( %s ))RF IQK OFFLOAD\n",
-+ ((dm->fw_offload_ability & PHYDM_RF_IQK_OFFLOAD) ?
-+ ("V") : (".")));
-+ PDM_SNPF(out_len, used, output + used, out_len - used,
-+ "================================\n");
-+
-+ } else if (dm_value[0] == 101) {
-+ dm->support_ability = 0;
-+ PDM_SNPF(out_len, used, output + used, out_len - used,
-+ "Disable all support_ability components\n");
-+ } else {
-+ if (dm_value[1] == 1) { /* @enable */
-+ dm->support_ability |= (one << dm_value[0]);
-+ } else if (dm_value[1] == 2) {/* @disable */
-+ dm->support_ability &= ~(one << dm_value[0]);
-+ } else {
-+ PDM_SNPF(out_len, used, output + used, out_len - used,
-+ "[Warning!!!] 1:enable, 2:disable\n");
-+ }
-+ }
-+ PDM_SNPF(out_len, used, output + used, out_len - used,
-+ "pre-supportability = 0x%llx\n", pre_support_ability);
-+ PDM_SNPF(out_len, used, output + used, out_len - used,
-+ "Cur-supportability = 0x%llx\n", dm->support_ability);
-+ PDM_SNPF(out_len, used, output + used, out_len - used,
-+ "================================\n");
-+
-+ *_used = used;
-+ *_out_len = out_len;
-+}
-+
-+void phydm_watchdog_lps_32k(struct dm_struct *dm)
-+{
-+ PHYDM_DBG(dm, DBG_COMMON_FLOW, "%s ======>\n", __func__);
-+
-+ phydm_common_info_self_update(dm);
-+ phydm_rssi_monitor_check(dm);
-+ phydm_dig_lps_32k(dm);
-+ phydm_common_info_self_reset(dm);
-+}
-+
-+void phydm_watchdog_lps(struct dm_struct *dm)
-+{
-+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE | ODM_IOT))
-+ PHYDM_DBG(dm, DBG_COMMON_FLOW, "%s ======>\n", __func__);
-+
-+ phydm_common_info_self_update(dm);
-+ phydm_rssi_monitor_check(dm);
-+ phydm_basic_dbg_message(dm);
-+ phydm_receiver_blocking(dm);
-+ phydm_false_alarm_counter_statistics(dm);
-+ phydm_dig_by_rssi_lps(dm);
-+ #ifdef PHYDM_SUPPORT_CCKPD
-+ phydm_cck_pd_th(dm);
-+ #endif
-+ phydm_adaptivity(dm);
-+ #if (DM_ODM_SUPPORT_TYPE & (ODM_CE))
-+ #ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
-+ /*@enable AntDiv in PS mode, request from SD4 Jeff*/
-+ odm_antenna_diversity(dm);
-+ #endif
-+ #endif
-+ phydm_common_info_self_reset(dm);
-+#endif
-+}
-+
-+void phydm_watchdog_mp(struct dm_struct *dm)
-+{
-+}
-+
-+void phydm_pause_dm_watchdog(void *dm_void, enum phydm_pause_type pause_type)
-+{
-+ struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+ if (pause_type == PHYDM_PAUSE) {
-+ dm->disable_phydm_watchdog = 1;
-+ PHYDM_DBG(dm, ODM_COMP_API, "PHYDM Stop\n");
-+ } else {
-+ dm->disable_phydm_watchdog = 0;
-+ PHYDM_DBG(dm, ODM_COMP_API, "PHYDM Start\n");
-+ }
-+}
-+
-+u8 phydm_pause_func(void *dm_void, enum phydm_func_idx pause_func,
-+ enum phydm_pause_type pause_type,
-+ enum phydm_pause_level pause_lv, u8 val_lehgth,
-+ u32 *val_buf)
-+{
-+ struct dm_struct *dm = (struct dm_struct *)dm_void;
-+ struct phydm_func_poiner *func_t = &dm->phydm_func_handler;
-+ s8 *pause_lv_pre = &dm->s8_dummy;
-+ u32 *bkp_val = &dm->u32_dummy;
-+ u32 ori_val[5] = {0};
-+ u64 pause_func_bitmap = (u64)BIT(pause_func);
-+ u8 i = 0;
-+ u8 en_2rcca = 0;
-+ u8 en_bw40m = 0;
-+ u8 pause_result = PAUSE_FAIL;
-+
-+ PHYDM_DBG(dm, ODM_COMP_API, "\n");
-+ PHYDM_DBG(dm, ODM_COMP_API, "[%s][%s] LV=%d, Len=%d\n", __func__,
-+ ((pause_type == PHYDM_PAUSE) ? "Pause" :
-+ ((pause_type == PHYDM_RESUME) ? "Resume" : "Pause no_set")),
-+ pause_lv, val_lehgth);
-+
-+ if (pause_lv >= PHYDM_PAUSE_MAX_NUM) {
-+ PHYDM_DBG(dm, ODM_COMP_API, "[WARNING]Wrong LV=%d\n", pause_lv);
-+ return PAUSE_FAIL;
-+ }
-+
-+ if (pause_func == F00_DIG) {
-+ PHYDM_DBG(dm, ODM_COMP_API, "[DIG]\n");
-+
-+ if (val_lehgth != 1) {
-+ PHYDM_DBG(dm, ODM_COMP_API, "[WARNING] length != 1\n");
-+ return PAUSE_FAIL;
-+ }
-+
-+ ori_val[0] = (u32)(dm->dm_dig_table.cur_ig_value);
-+ pause_lv_pre = &dm->pause_lv_table.lv_dig;
-+ bkp_val = (u32 *)(&dm->dm_dig_table.rvrt_val);
-+ /*@function pointer hook*/
-+ func_t->pause_phydm_handler = phydm_set_dig_val;
-+
-+#ifdef PHYDM_SUPPORT_CCKPD
-+ } else if (pause_func == F05_CCK_PD) {
-+ PHYDM_DBG(dm, ODM_COMP_API, "[CCK_PD]\n");
-+
-+ if (val_lehgth != 1) {
-+ PHYDM_DBG(dm, ODM_COMP_API, "[WARNING] length != 1\n");
-+ return PAUSE_FAIL;
-+ }
-+
-+ ori_val[0] = (u32)dm->dm_cckpd_table.cck_pd_lv;
-+ pause_lv_pre = &dm->pause_lv_table.lv_cckpd;
-+ bkp_val = (u32 *)(&dm->dm_cckpd_table.rvrt_val);
-+ /*@function pointer hook*/
-+ func_t->pause_phydm_handler = phydm_set_cckpd_val;
-+#endif
-+
-+#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
-+ } else if (pause_func == F06_ANT_DIV) {
-+ PHYDM_DBG(dm, ODM_COMP_API, "[AntDiv]\n");
-+
-+ if (val_lehgth != 1) {
-+ PHYDM_DBG(dm, ODM_COMP_API, "[WARNING] length != 1\n");
-+ return PAUSE_FAIL;
-+ }
-+ /*@default antenna*/
-+ ori_val[0] = (u32)(dm->dm_fat_table.rx_idle_ant);
-+ pause_lv_pre = &dm->pause_lv_table.lv_antdiv;
-+ bkp_val = (u32 *)(&dm->dm_fat_table.rvrt_val);
-+ /*@function pointer hook*/
-+ func_t->pause_phydm_handler = phydm_set_antdiv_val;
-+
-+#endif
-+#ifdef PHYDM_SUPPORT_ADAPTIVITY
-+ } else if (pause_func == F13_ADPTVTY) {
-+ PHYDM_DBG(dm, ODM_COMP_API, "[Adaptivity]\n");
-+
-+ if (val_lehgth != 2) {
-+ PHYDM_DBG(dm, ODM_COMP_API, "[WARNING] length != 2\n");
-+ return PAUSE_FAIL;
-+ }
-+
-+ ori_val[0] = (u32)(dm->adaptivity.th_l2h); /*th_l2h*/
-+ ori_val[1] = (u32)(dm->adaptivity.th_h2l); /*th_h2l*/
-+ pause_lv_pre = &dm->pause_lv_table.lv_adapt;
-+ bkp_val = (u32 *)(&dm->adaptivity.rvrt_val);
-+ /*@function pointer hook*/
-+ func_t->pause_phydm_handler = phydm_set_edcca_val;
-+
-+#endif
-+#ifdef CONFIG_ADAPTIVE_SOML
-+ } else if (pause_func == F17_ADPTV_SOML) {
-+ PHYDM_DBG(dm, ODM_COMP_API, "[AD-SOML]\n");
-+
-+ if (val_lehgth != 1) {
-+ PHYDM_DBG(dm, ODM_COMP_API, "[WARNING] length != 1\n");
-+ return PAUSE_FAIL;
-+ }
-+ /*SOML_ON/OFF*/
-+ ori_val[0] = (u32)(dm->dm_soml_table.soml_on_off);
-+
-+ pause_lv_pre = &dm->pause_lv_table.lv_adsl;
-+ bkp_val = (u32 *)(&dm->dm_soml_table.rvrt_val);
-+ /*@function pointer hook*/
-+ func_t->pause_phydm_handler = phydm_set_adsl_val;
-+
-+#endif
-+ } else {
-+ PHYDM_DBG(dm, ODM_COMP_API, "[WARNING] error func idx\n");
-+ return PAUSE_FAIL;
-+ }
-+
-+ PHYDM_DBG(dm, ODM_COMP_API, "Pause_LV{new , pre} = {%d ,%d}\n",
-+ pause_lv, *pause_lv_pre);
-+
-+ if (pause_type == PHYDM_PAUSE || pause_type == PHYDM_PAUSE_NO_SET) {
-+ if (pause_lv <= *pause_lv_pre) {
-+ PHYDM_DBG(dm, ODM_COMP_API,
-+ "[PAUSE FAIL] Pre_LV >= Curr_LV\n");
-+ return PAUSE_FAIL;
-+ }
-+
-+ if (!(dm->pause_ability & pause_func_bitmap)) {
-+ for (i = 0; i < val_lehgth; i++)
-+ bkp_val[i] = ori_val[i];
-+ }
-+
-+ dm->pause_ability |= pause_func_bitmap;
-+ PHYDM_DBG(dm, ODM_COMP_API, "pause_ability=0x%llx\n",
-+ dm->pause_ability);
-+
-+ if (pause_type == PHYDM_PAUSE) {
-+ for (i = 0; i < val_lehgth; i++)
-+ PHYDM_DBG(dm, ODM_COMP_API,
-+ "[PAUSE SUCCESS] val_idx[%d]{New, Ori}={0x%x, 0x%x}\n",
-+ i, val_buf[i], bkp_val[i]);
-+ func_t->pause_phydm_handler(dm, val_buf, val_lehgth);
-+ } else {
-+ for (i = 0; i < val_lehgth; i++)
-+ PHYDM_DBG(dm, ODM_COMP_API,
-+ "[PAUSE NO Set: SUCCESS] val_idx[%d]{Ori}={0x%x}\n",
-+ i, bkp_val[i]);
-+ }
-+
-+ *pause_lv_pre = pause_lv;
-+ pause_result = PAUSE_SUCCESS;
-+
-+ } else if (pause_type == PHYDM_RESUME) {
-+ if ((dm->pause_ability & pause_func_bitmap) == 0) {
-+ PHYDM_DBG(dm, ODM_COMP_API,
-+ "[RESUME] No Need to Revert\n");
-+ return PAUSE_SUCCESS;
-+ }
-+
-+ dm->pause_ability &= ~pause_func_bitmap;
-+ PHYDM_DBG(dm, ODM_COMP_API, "pause_ability=0x%llx\n",
-+ dm->pause_ability);
-+
-+ *pause_lv_pre = PHYDM_PAUSE_RELEASE;
-+
-+ for (i = 0; i < val_lehgth; i++) {
-+ PHYDM_DBG(dm, ODM_COMP_API,
-+ "[RESUME] val_idx[%d]={0x%x}\n", i,
-+ bkp_val[i]);
-+ }
-+
-+ func_t->pause_phydm_handler(dm, bkp_val, val_lehgth);
-+
-+ pause_result = PAUSE_SUCCESS;
-+ } else {
-+ PHYDM_DBG(dm, ODM_COMP_API, "[WARNING] error pause_type\n");
-+ pause_result = PAUSE_FAIL;
-+ }
-+ return pause_result;
-+}
-+
-+void phydm_pause_func_console(void *dm_void, char input[][16], u32 *_used,
-+ char *output, u32 *_out_len)
-+{
-+ struct dm_struct *dm = (struct dm_struct *)dm_void;
-+ char help[] = "-h";
-+ u32 var1[10] = {0};
-+ u32 used = *_used;
-+ u32 out_len = *_out_len;
-+ u32 i;
-+ u8 length = 0;
-+ u32 buf[5] = {0};
-+ u8 set_result = 0;
-+ enum phydm_func_idx func = 0;
-+ enum phydm_pause_type type = 0;
-+ enum phydm_pause_level lv = 0;
-+
-+ if ((strcmp(input[1], help) == 0)) {
-+ PDM_SNPF(out_len, used, output + used, out_len - used,
-+ "{Func} {1:pause,2:pause no set 3:Resume} {lv:0~3} Val[5:0]\n");
-+
-+ goto out;
-+ }
-+
-+ for (i = 0; i < 10; i++) {
-+ if (input[i + 1])
-+ PHYDM_SSCANF(input[i + 1], DCMD_HEX, &var1[i]);
-+ }
-+
-+ func = (enum phydm_func_idx)var1[0];
-+ type = (enum phydm_pause_type)var1[1];
-+ lv = (enum phydm_pause_level)var1[2];
-+
-+ for (i = 0; i < 5; i++)
-+ buf[i] = var1[3 + i];
-+
-+ if (func == F00_DIG) {
-+ PDM_SNPF(out_len, used, output + used, out_len - used,
-+ "[DIG]\n");
-+ length = 1;
-+
-+ } else if (func == F05_CCK_PD) {
-+ PDM_SNPF(out_len, used, output + used, out_len - used,
-+ "[CCK_PD]\n");
-+ length = 1;
-+ } else if (func == F06_ANT_DIV) {
-+ PDM_SNPF(out_len, used, output + used, out_len - used,
-+ "[Ant_Div]\n");
-+ length = 1;
-+ } else if (func == F13_ADPTVTY) {
-+ PDM_SNPF(out_len, used, output + used, out_len - used,
-+ "[Adaptivity]\n");
-+ length = 2;
-+ } else if (func == F17_ADPTV_SOML) {
-+ PDM_SNPF(out_len, used, output + used, out_len - used,
-+ "[ADSL]\n");
-+ length = 1;
-+ } else {
-+ PDM_SNPF(out_len, used, output + used, out_len - used,
-+ "[Set Function Error]\n");
-+ length = 0;
-+ }
-+
-+ if (length != 0) {
-+ PDM_SNPF(out_len, used, output + used, out_len - used,
-+ "{%s, lv=%d} val = %d, %d}\n",
-+ ((type == PHYDM_PAUSE) ? "Pause" :
-+ ((type == PHYDM_RESUME) ? "Resume" : "Pause no_set")),
-+ lv, var1[3], var1[4]);
-+
-+ set_result = phydm_pause_func(dm, func, type, lv, length, buf);
-+ }
-+
-+ PDM_SNPF(out_len, used, output + used, out_len - used,
-+ "set_result = %d\n", set_result);
-+
-+out:
-+ *_used = used;
-+ *_out_len = out_len;
-+}
-+
-+u8 phydm_stop_dm_watchdog_check(void *dm_void)
-+{
-+ struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+ if (dm->disable_phydm_watchdog == 1) {
-+ PHYDM_DBG(dm, DBG_COMMON_FLOW, "Disable phydm\n");
-+ return true;
-+ } else {
-+ return false;
-+ }
-+}
-+
-+void phydm_watchdog(struct dm_struct *dm)
-+{
-+ PHYDM_DBG(dm, DBG_COMMON_FLOW, "%s ======>\n", __func__);
-+
-+ phydm_common_info_self_update(dm);
-+ phydm_phy_info_update(dm);
-+ phydm_rssi_monitor_check(dm);
-+ phydm_basic_dbg_message(dm);
-+ phydm_dm_summary(dm, FIRST_MACID);
-+#ifdef PHYDM_AUTO_DEGBUG
-+ phydm_auto_dbg_engine(dm);
-+#endif
-+ phydm_receiver_blocking(dm);
-+
-+ if (phydm_stop_dm_watchdog_check(dm) == true)
-+ return;
-+
-+ phydm_hw_setting(dm);
-+
-+ #ifdef PHYDM_TDMA_DIG_SUPPORT
-+ if (dm->original_dig_restore == 0)
-+ phydm_tdma_dig_timer_check(dm);
-+ else
-+ #endif
-+ {
-+ phydm_false_alarm_counter_statistics(dm);
-+ phydm_noisy_detection(dm);
-+ phydm_dig(dm);
-+ #ifdef PHYDM_SUPPORT_CCKPD
-+ phydm_cck_pd_th(dm);
-+ #endif
-+ }
-+
-+#ifdef PHYDM_POWER_TRAINING_SUPPORT
-+ phydm_update_power_training_state(dm);
-+#endif
-+ phydm_adaptivity(dm);
-+ phydm_ra_info_watchdog(dm);
-+#ifdef CONFIG_PATH_DIVERSITY
-+ phydm_tx_path_diversity(dm);
-+#endif
-+ phydm_cfo_tracking(dm);
-+#ifdef CONFIG_DYNAMIC_TX_TWR
-+ phydm_dynamic_tx_power(dm);
-+#endif
-+#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
-+ odm_antenna_diversity(dm);
-+#endif
-+#ifdef CONFIG_ADAPTIVE_SOML
-+ phydm_adaptive_soml(dm);
-+#endif
-+
-+#ifdef PHYDM_BEAMFORMING_VERSION1
-+ phydm_beamforming_watchdog(dm);
-+#endif
-+
-+ halrf_watchdog(dm);
-+#ifdef PHYDM_PRIMARY_CCA
-+ phydm_primary_cca(dm);
-+#endif
-+#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
-+ odm_dtc(dm);
-+#endif
-+
-+ phydm_env_mntr_watchdog(dm);
-+
-+#ifdef PHYDM_LNA_SAT_CHK_SUPPORT
-+ phydm_lna_sat_chk_watchdog(dm);
-+#endif
-+#ifdef CONFIG_MCC_DM
-+ #if (RTL8822B_SUPPORT == 1)
-+ phydm_mcc_switch(dm);
-+ #endif
-+#endif
-+ phydm_common_info_self_reset(dm);
-+}
-+
-+/*@
-+ * Init /.. Fixed HW value. Only init time.
-+ */
-+void odm_cmn_info_init(struct dm_struct *dm, enum odm_cmninfo cmn_info,
-+ u64 value)
-+{
-+ /* This section is used for init value */
-+ switch (cmn_info) {
-+ /* @Fixed ODM value. */
-+ case ODM_CMNINFO_ABILITY:
-+ dm->support_ability = (u64)value;
-+ break;
-+
-+ case ODM_CMNINFO_RF_TYPE:
-+ dm->rf_type = (u8)value;
-+ break;
-+
-+ case ODM_CMNINFO_PLATFORM:
-+ dm->support_platform = (u8)value;
-+ break;
-+
-+ case ODM_CMNINFO_INTERFACE:
-+ dm->support_interface = (u8)value;
-+ break;
-+
-+ case ODM_CMNINFO_IC_TYPE:
-+ dm->support_ic_type = (u32)value;
-+ break;
-+
-+ case ODM_CMNINFO_CUT_VER:
-+ dm->cut_version = (u8)value;
-+ break;
-+
-+ case ODM_CMNINFO_FAB_VER:
-+ dm->fab_version = (u8)value;
-+ break;
-+ case ODM_CMNINFO_FW_VER:
-+ dm->fw_version = (u8)value;
-+ break;
-+ case ODM_CMNINFO_FW_SUB_VER:
-+ dm->fw_sub_version = (u8)value;
-+ break;
-+ case ODM_CMNINFO_RFE_TYPE:
-+#if (RTL8821C_SUPPORT == 1)
-+ if (dm->support_ic_type & ODM_RTL8821C)
-+ dm->rfe_type_expand = (u8)value;
-+ else
-+#endif
-+ dm->rfe_type = (u8)value;
-+ phydm_init_hw_info_by_rfe(dm);
-+ break;
-+
-+ case ODM_CMNINFO_RF_ANTENNA_TYPE:
-+ dm->ant_div_type = (u8)value;
-+ break;
-+
-+ case ODM_CMNINFO_WITH_EXT_ANTENNA_SWITCH:
-+ dm->with_extenal_ant_switch = (u8)value;
-+ break;
-+
-+#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
-+ case ODM_CMNINFO_BE_FIX_TX_ANT:
-+ dm->dm_fat_table.b_fix_tx_ant = (u8)value;
-+ break;
-+#endif
-+
-+ case ODM_CMNINFO_BOARD_TYPE:
-+ if (!dm->is_init_hw_info_by_rfe)
-+ dm->board_type = (u8)value;
-+ break;
-+
-+ case ODM_CMNINFO_PACKAGE_TYPE:
-+ if (!dm->is_init_hw_info_by_rfe)
-+ dm->package_type = (u8)value;
-+ break;
-+
-+ case ODM_CMNINFO_EXT_LNA:
-+ if (!dm->is_init_hw_info_by_rfe)
-+ dm->ext_lna = (u8)value;
-+ break;
-+
-+ case ODM_CMNINFO_5G_EXT_LNA:
-+ if (!dm->is_init_hw_info_by_rfe)
-+ dm->ext_lna_5g = (u8)value;
-+ break;
-+
-+ case ODM_CMNINFO_EXT_PA:
-+ if (!dm->is_init_hw_info_by_rfe)
-+ dm->ext_pa = (u8)value;
-+ break;
-+
-+ case ODM_CMNINFO_5G_EXT_PA:
-+ if (!dm->is_init_hw_info_by_rfe)
-+ dm->ext_pa_5g = (u8)value;
-+ break;
-+
-+ case ODM_CMNINFO_GPA:
-+ if (!dm->is_init_hw_info_by_rfe)
-+ dm->type_gpa = (u16)value;
-+ break;
-+
-+ case ODM_CMNINFO_APA:
-+ if (!dm->is_init_hw_info_by_rfe)
-+ dm->type_apa = (u16)value;
-+ break;
-+
-+ case ODM_CMNINFO_GLNA:
-+ if (!dm->is_init_hw_info_by_rfe)
-+ dm->type_glna = (u16)value;
-+ break;
-+
-+ case ODM_CMNINFO_ALNA:
-+ if (!dm->is_init_hw_info_by_rfe)
-+ dm->type_alna = (u16)value;
-+ break;
-+
-+ case ODM_CMNINFO_EXT_TRSW:
-+ if (!dm->is_init_hw_info_by_rfe)
-+ dm->ext_trsw = (u8)value;
-+ break;
-+ case ODM_CMNINFO_EXT_LNA_GAIN:
-+ dm->ext_lna_gain = (u8)value;
-+ break;
-+ case ODM_CMNINFO_PATCH_ID:
-+ dm->iot_table.win_patch_id = (u8)value;
-+ break;
-+ case ODM_CMNINFO_BINHCT_TEST:
-+ dm->is_in_hct_test = (boolean)value;
-+ break;
-+ case ODM_CMNINFO_BWIFI_TEST:
-+ dm->wifi_test = (u8)value;
-+ break;
-+ case ODM_CMNINFO_SMART_CONCURRENT:
-+ dm->is_dual_mac_smart_concurrent = (boolean)value;
-+ break;
-+#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
-+ case ODM_CMNINFO_CONFIG_BB_RF:
-+ dm->config_bbrf = (boolean)value;
-+ break;
-+#endif
-+ case ODM_CMNINFO_IQKPAOFF:
-+ dm->rf_calibrate_info.is_iqk_pa_off = (boolean)value;
-+ break;
-+ case ODM_CMNINFO_REGRFKFREEENABLE:
-+ dm->rf_calibrate_info.reg_rf_kfree_enable = (u8)value;
-+ break;
-+ case ODM_CMNINFO_RFKFREEENABLE:
-+ dm->rf_calibrate_info.rf_kfree_enable = (u8)value;
-+ break;
-+ case ODM_CMNINFO_NORMAL_RX_PATH_CHANGE:
-+ dm->normal_rx_path = (u8)value;
-+ break;
-+ case ODM_CMNINFO_EFUSE0X3D8:
-+ dm->efuse0x3d8 = (u8)value;
-+ break;
-+ case ODM_CMNINFO_EFUSE0X3D7:
-+ dm->efuse0x3d7 = (u8)value;
-+ break;
-+ case ODM_CMNINFO_ADVANCE_OTA:
-+ dm->p_advance_ota = (u8)value;
-+ break;
-+
-+#ifdef CONFIG_PHYDM_DFS_MASTER
-+ case ODM_CMNINFO_DFS_REGION_DOMAIN:
-+ dm->dfs_region_domain = (u8)value;
-+ break;
-+#endif
-+ case ODM_CMNINFO_SOFT_AP_SPECIAL_SETTING:
-+ dm->soft_ap_special_setting = (u32)value;
-+ break;
-+
-+ case ODM_CMNINFO_X_CAP_SETTING:
-+ dm->dm_cfo_track.crystal_cap_default = (u8)value;
-+ break;
-+
-+ case ODM_CMNINFO_DPK_EN:
-+ /*@dm->dpk_en = (u1Byte)value;*/
-+ halrf_cmn_info_set(dm, HALRF_CMNINFO_DPK_EN, (u64)value);
-+ break;
-+
-+ case ODM_CMNINFO_HP_HWID:
-+ dm->hp_hw_id = (boolean)value;
-+ break;
-+ default:
-+ break;
-+ }
-+}
-+
-+void odm_cmn_info_hook(struct dm_struct *dm, enum odm_cmninfo cmn_info,
-+ void *value)
-+{
-+ /* @Hook call by reference pointer. */
-+ switch (cmn_info) {
-+ /* @Dynamic call by reference pointer. */
-+ case ODM_CMNINFO_TX_UNI:
-+ dm->num_tx_bytes_unicast = (u64 *)value;
-+ break;
-+
-+ case ODM_CMNINFO_RX_UNI:
-+ dm->num_rx_bytes_unicast = (u64 *)value;
-+ break;
-+
-+ case ODM_CMNINFO_BAND:
-+ dm->band_type = (u8 *)value;
-+ break;
-+
-+ case ODM_CMNINFO_SEC_CHNL_OFFSET:
-+ dm->sec_ch_offset = (u8 *)value;
-+ break;
-+
-+ case ODM_CMNINFO_SEC_MODE:
-+ dm->security = (u8 *)value;
-+ break;
-+
-+ case ODM_CMNINFO_BW:
-+ dm->band_width = (u8 *)value;
-+ break;
-+
-+ case ODM_CMNINFO_CHNL:
-+ dm->channel = (u8 *)value;
-+ break;
-+
-+ case ODM_CMNINFO_SCAN:
-+ dm->is_scan_in_process = (boolean *)value;
-+ break;
-+
-+ case ODM_CMNINFO_POWER_SAVING:
-+ dm->is_power_saving = (boolean *)value;
-+ break;
-+
-+ case ODM_CMNINFO_TDMA:
-+ dm->is_tdma = (boolean *)value;
-+ break;
-+
-+ case ODM_CMNINFO_ONE_PATH_CCA:
-+ dm->one_path_cca = (u8 *)value;
-+ break;
-+
-+ case ODM_CMNINFO_DRV_STOP:
-+ dm->is_driver_stopped = (boolean *)value;
-+ break;
-+ case ODM_CMNINFO_INIT_ON:
-+ dm->pinit_adpt_in_progress = (boolean *)value;
-+ break;
-+
-+ case ODM_CMNINFO_ANT_TEST:
-+ dm->antenna_test = (u8 *)value;
-+ break;
-+
-+ case ODM_CMNINFO_NET_CLOSED:
-+ dm->is_net_closed = (boolean *)value;
-+ break;
-+
-+ case ODM_CMNINFO_FORCED_RATE:
-+ dm->forced_data_rate = (u16 *)value;
-+ break;
-+ case ODM_CMNINFO_ANT_DIV:
-+ dm->enable_antdiv = (u8 *)value;
-+ break;
-+ case ODM_CMNINFO_PATH_DIV:
-+ dm->enable_pathdiv = (u8 *)value;
-+ break;
-+ case ODM_CMNINFO_ADAPTIVE_SOML:
-+ dm->en_adap_soml = (u8 *)value;
-+ break;
-+ case ODM_CMNINFO_ADAPTIVITY:
-+ dm->enable_adaptivity = (u8 *)value;
-+ break;
-+
-+ case ODM_CMNINFO_P2P_LINK:
-+ dm->dm_dig_table.is_p2p_in_process = (u8 *)value;
-+ break;
-+
-+ case ODM_CMNINFO_IS1ANTENNA:
-+ dm->is_1_antenna = (boolean *)value;
-+ break;
-+
-+ case ODM_CMNINFO_RFDEFAULTPATH:
-+ dm->rf_default_path = (u8 *)value;
-+ break;
-+
-+ case ODM_CMNINFO_FCS_MODE:
-+ dm->is_fcs_mode_enable = (boolean *)value;
-+ break;
-+
-+ case ODM_CMNINFO_HUBUSBMODE:
-+ dm->hub_usb_mode = (u8 *)value;
-+ break;
-+ case ODM_CMNINFO_FWDWRSVDPAGEINPROGRESS:
-+ dm->is_fw_dw_rsvd_page_in_progress = (boolean *)value;
-+ break;
-+ case ODM_CMNINFO_TX_TP:
-+ dm->current_tx_tp = (u32 *)value;
-+ break;
-+ case ODM_CMNINFO_RX_TP:
-+ dm->current_rx_tp = (u32 *)value;
-+ break;
-+ case ODM_CMNINFO_SOUNDING_SEQ:
-+ dm->sounding_seq = (u8 *)value;
-+ break;
-+#ifdef CONFIG_PHYDM_DFS_MASTER
-+ case ODM_CMNINFO_DFS_MASTER_ENABLE:
-+ dm->dfs_master_enabled = (u8 *)value;
-+ break;
-+#endif
-+
-+#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
-+ case ODM_CMNINFO_FORCE_TX_ANT_BY_TXDESC:
-+ dm->dm_fat_table.p_force_tx_by_desc = (u8 *)value;
-+ break;
-+ case ODM_CMNINFO_SET_S0S1_DEFAULT_ANTENNA:
-+ dm->dm_fat_table.p_default_s0_s1 = (u8 *)value;
-+ break;
-+ case ODM_CMNINFO_BF_ANTDIV_DECISION:
-+ dm->dm_fat_table.is_no_csi_feedback = (boolean *)value;
-+ break;
-+#endif
-+
-+ case ODM_CMNINFO_SOFT_AP_MODE:
-+ dm->soft_ap_mode = (u32 *)value;
-+ break;
-+ case ODM_CMNINFO_MP_MODE:
-+ dm->mp_mode = (u8 *)value;
-+ break;
-+ case ODM_CMNINFO_INTERRUPT_MASK:
-+ dm->interrupt_mask = (u32 *)value;
-+ break;
-+ case ODM_CMNINFO_BB_OPERATION_MODE:
-+ dm->bb_op_mode = (u8 *)value;
-+ break;
-+ default:
-+ /*do nothing*/
-+ break;
-+ }
-+}
-+
-+/*@
-+ * Update band/CHannel/.. The values are dynamic but non-per-packet.
-+ */
-+void odm_cmn_info_update(struct dm_struct *dm, u32 cmn_info, u64 value)
-+{
-+ /* This init variable may be changed in run time. */
-+ switch (cmn_info) {
-+ case ODM_CMNINFO_LINK_IN_PROGRESS:
-+ dm->is_link_in_process = (boolean)value;
-+ break;
-+
-+ case ODM_CMNINFO_ABILITY:
-+ dm->support_ability = (u64)value;
-+ break;
-+
-+ case ODM_CMNINFO_RF_TYPE:
-+ dm->rf_type = (u8)value;
-+ break;
-+
-+ case ODM_CMNINFO_WIFI_DIRECT:
-+ dm->is_wifi_direct = (boolean)value;
-+ break;
-+
-+ case ODM_CMNINFO_WIFI_DISPLAY:
-+ dm->is_wifi_display = (boolean)value;
-+ break;
-+
-+ case ODM_CMNINFO_LINK:
-+ dm->is_linked = (boolean)value;
-+ break;
-+
-+ case ODM_CMNINFO_CMW500LINK:
-+ dm->iot_table.is_linked_cmw500 = (boolean)value;
-+ break;
-+
-+ case ODM_CMNINFO_STATION_STATE:
-+ dm->bsta_state = (boolean)value;
-+ break;
-+
-+ case ODM_CMNINFO_RSSI_MIN:
-+ dm->rssi_min = (u8)value;
-+ break;
-+
-+ case ODM_CMNINFO_RSSI_MIN_BY_PATH:
-+ dm->rssi_min_by_path = (u8)value;
-+ break;
-+
-+ case ODM_CMNINFO_DBG_COMP:
-+ dm->debug_components = (u64)value;
-+ break;
-+
-+#ifdef ODM_CONFIG_BT_COEXIST
-+ /* The following is for BT HS mode and BT coexist mechanism. */
-+ case ODM_CMNINFO_BT_ENABLED:
-+ dm->bt_info_table.is_bt_enabled = (boolean)value;
-+ break;
-+
-+ case ODM_CMNINFO_BT_HS_CONNECT_PROCESS:
-+ dm->bt_info_table.is_bt_connect_process = (boolean)value;
-+ break;
-+
-+ case ODM_CMNINFO_BT_HS_RSSI:
-+ dm->bt_info_table.bt_hs_rssi = (u8)value;
-+ break;
-+
-+ case ODM_CMNINFO_BT_OPERATION:
-+ dm->bt_info_table.is_bt_hs_operation = (boolean)value;
-+ break;
-+
-+ case ODM_CMNINFO_BT_LIMITED_DIG:
-+ dm->bt_info_table.is_bt_limited_dig = (boolean)value;
-+ break;
-+#endif
-+
-+ case ODM_CMNINFO_AP_TOTAL_NUM:
-+ dm->ap_total_num = (u8)value;
-+ break;
-+
-+#ifdef CONFIG_PHYDM_DFS_MASTER
-+ case ODM_CMNINFO_DFS_REGION_DOMAIN:
-+ dm->dfs_region_domain = (u8)value;
-+ break;
-+#endif
-+
-+ case ODM_CMNINFO_BT_CONTINUOUS_TURN:
-+ dm->is_bt_continuous_turn = (boolean)value;
-+ break;
-+ default:
-+ break;
-+ }
-+}
-+
-+u32 phydm_cmn_info_query(struct dm_struct *dm, enum phydm_info_query info_type)
-+{
-+ struct phydm_fa_struct *fa_t = &dm->false_alm_cnt;
-+ struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
-+ struct ccx_info *ccx_info = &dm->dm_ccx_info;
-+
-+ switch (info_type) {
-+ /*@=== [FA Relative] ===========================================*/
-+ case PHYDM_INFO_FA_OFDM:
-+ return fa_t->cnt_ofdm_fail;
-+
-+ case PHYDM_INFO_FA_CCK:
-+ return fa_t->cnt_cck_fail;
-+
-+ case PHYDM_INFO_FA_TOTAL:
-+ return fa_t->cnt_all;
-+
-+ case PHYDM_INFO_CCA_OFDM:
-+ return fa_t->cnt_ofdm_cca;
-+
-+ case PHYDM_INFO_CCA_CCK:
-+ return fa_t->cnt_cck_cca;
-+
-+ case PHYDM_INFO_CCA_ALL:
-+ return fa_t->cnt_cca_all;
-+
-+ case PHYDM_INFO_CRC32_OK_VHT:
-+ return fa_t->cnt_vht_crc32_ok;
-+
-+ case PHYDM_INFO_CRC32_OK_HT:
-+ return fa_t->cnt_ht_crc32_ok;
-+
-+ case PHYDM_INFO_CRC32_OK_LEGACY:
-+ return fa_t->cnt_ofdm_crc32_ok;
-+
-+ case PHYDM_INFO_CRC32_OK_CCK:
-+ return fa_t->cnt_cck_crc32_ok;
-+
-+ case PHYDM_INFO_CRC32_ERROR_VHT:
-+ return fa_t->cnt_vht_crc32_error;
-+
-+ case PHYDM_INFO_CRC32_ERROR_HT:
-+ return fa_t->cnt_ht_crc32_error;
-+
-+ case PHYDM_INFO_CRC32_ERROR_LEGACY:
-+ return fa_t->cnt_ofdm_crc32_error;
-+
-+ case PHYDM_INFO_CRC32_ERROR_CCK:
-+ return fa_t->cnt_cck_crc32_error;
-+
-+ case PHYDM_INFO_EDCCA_FLAG:
-+ return fa_t->edcca_flag;
-+
-+ case PHYDM_INFO_OFDM_ENABLE:
-+ return fa_t->ofdm_block_enable;
-+
-+ case PHYDM_INFO_CCK_ENABLE:
-+ return fa_t->cck_block_enable;
-+
-+ case PHYDM_INFO_DBG_PORT_0:
-+ return fa_t->dbg_port0;
-+
-+ case PHYDM_INFO_CRC32_OK_HT_AGG:
-+ return fa_t->cnt_ht_crc32_ok_agg;
-+
-+ case PHYDM_INFO_CRC32_ERROR_HT_AGG:
-+ return fa_t->cnt_ht_crc32_error_agg;
-+
-+ /*@=== [DIG] ================================================*/
-+
-+ case PHYDM_INFO_CURR_IGI:
-+ return dig_t->cur_ig_value;
-+
-+ /*@=== [RSSI] ===============================================*/
-+ case PHYDM_INFO_RSSI_MIN:
-+ return (u32)dm->rssi_min;
-+
-+ case PHYDM_INFO_RSSI_MAX:
-+ return (u32)dm->rssi_max;
-+
-+ case PHYDM_INFO_CLM_RATIO:
-+ return (u32)ccx_info->clm_ratio;
-+ case PHYDM_INFO_NHM_RATIO:
-+ return (u32)ccx_info->nhm_ratio;
-+ default:
-+ return 0xffffffff;
-+ }
-+}
-+
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+void odm_init_all_work_items(struct dm_struct *dm)
-+{
-+ void *adapter = dm->adapter;
-+#if USE_WORKITEM
-+
-+#ifdef CONFIG_ADAPTIVE_SOML
-+ odm_initialize_work_item(dm,
-+ &dm->dm_soml_table.phydm_adaptive_soml_workitem,
-+ (RT_WORKITEM_CALL_BACK)phydm_adaptive_soml_workitem_callback,
-+ (void *)adapter,
-+ "AdaptiveSOMLWorkitem");
-+#endif
-+
-+#ifdef ODM_EVM_ENHANCE_ANTDIV
-+ odm_initialize_work_item(dm,
-+ &dm->phydm_evm_antdiv_workitem,
-+ (RT_WORKITEM_CALL_BACK)phydm_evm_antdiv_workitem_callback,
-+ (void *)adapter,
-+ "EvmAntdivWorkitem");
-+#endif
-+
-+#ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY
-+ odm_initialize_work_item(dm,
-+ &dm->dm_swat_table.phydm_sw_antenna_switch_workitem,
-+ (RT_WORKITEM_CALL_BACK)odm_sw_antdiv_workitem_callback,
-+ (void *)adapter,
-+ "AntennaSwitchWorkitem");
-+#endif
-+#if (defined(CONFIG_HL_SMART_ANTENNA))
-+ odm_initialize_work_item(dm,
-+ &dm->dm_sat_table.hl_smart_antenna_workitem,
-+ (RT_WORKITEM_CALL_BACK)phydm_beam_switch_workitem_callback,
-+ (void *)adapter,
-+ "hl_smart_ant_workitem");
-+
-+ odm_initialize_work_item(dm,
-+ &dm->dm_sat_table.hl_smart_antenna_decision_workitem,
-+ (RT_WORKITEM_CALL_BACK)phydm_beam_decision_workitem_callback,
-+ (void *)adapter,
-+ "hl_smart_ant_decision_workitem");
-+#endif
-+
-+ odm_initialize_work_item(
-+ dm,
-+ &dm->ra_rpt_workitem,
-+ (RT_WORKITEM_CALL_BACK)halrf_update_init_rate_work_item_callback,
-+ (void *)adapter,
-+ "ra_rpt_workitem");
-+
-+#if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))
-+ odm_initialize_work_item(
-+ dm,
-+ &dm->fast_ant_training_workitem,
-+ (RT_WORKITEM_CALL_BACK)odm_fast_ant_training_work_item_callback,
-+ (void *)adapter,
-+ "fast_ant_training_workitem");
-+#endif
-+
-+#endif /*#if USE_WORKITEM*/
-+
-+#ifdef PHYDM_BEAMFORMING_SUPPORT
-+ odm_initialize_work_item(
-+ dm,
-+ &dm->beamforming_info.txbf_info.txbf_enter_work_item,
-+ (RT_WORKITEM_CALL_BACK)hal_com_txbf_enter_work_item_callback,
-+ (void *)adapter,
-+ "txbf_enter_work_item");
-+
-+ odm_initialize_work_item(
-+ dm,
-+ &dm->beamforming_info.txbf_info.txbf_leave_work_item,
-+ (RT_WORKITEM_CALL_BACK)hal_com_txbf_leave_work_item_callback,
-+ (void *)adapter,
-+ "txbf_leave_work_item");
-+
-+ odm_initialize_work_item(
-+ dm,
-+ &dm->beamforming_info.txbf_info.txbf_fw_ndpa_work_item,
-+ (RT_WORKITEM_CALL_BACK)hal_com_txbf_fw_ndpa_work_item_callback,
-+ (void *)adapter,
-+ "txbf_fw_ndpa_work_item");
-+
-+ odm_initialize_work_item(
-+ dm,
-+ &dm->beamforming_info.txbf_info.txbf_clk_work_item,
-+ (RT_WORKITEM_CALL_BACK)hal_com_txbf_clk_work_item_callback,
-+ (void *)adapter,
-+ "txbf_clk_work_item");
-+
-+ odm_initialize_work_item(
-+ dm,
-+ &dm->beamforming_info.txbf_info.txbf_rate_work_item,
-+ (RT_WORKITEM_CALL_BACK)hal_com_txbf_rate_work_item_callback,
-+ (void *)adapter,
-+ "txbf_rate_work_item");
-+
-+ odm_initialize_work_item(
-+ dm,
-+ &dm->beamforming_info.txbf_info.txbf_status_work_item,
-+ (RT_WORKITEM_CALL_BACK)hal_com_txbf_status_work_item_callback,
-+ (void *)adapter,
-+ "txbf_status_work_item");
-+
-+ odm_initialize_work_item(
-+ dm,
-+ &dm->beamforming_info.txbf_info.txbf_reset_tx_path_work_item,
-+ (RT_WORKITEM_CALL_BACK)hal_com_txbf_reset_tx_path_work_item_callback,
-+ (void *)adapter,
-+ "txbf_reset_tx_path_work_item");
-+
-+ odm_initialize_work_item(
-+ dm,
-+ &dm->beamforming_info.txbf_info.txbf_get_tx_rate_work_item,
-+ (RT_WORKITEM_CALL_BACK)hal_com_txbf_get_tx_rate_work_item_callback,
-+ (void *)adapter,
-+ "txbf_get_tx_rate_work_item");
-+#endif
-+
-+#if (PHYDM_LA_MODE_SUPPORT == 1)
-+ odm_initialize_work_item(
-+ dm,
-+ &dm->adcsmp.adc_smp_work_item,
-+ (RT_WORKITEM_CALL_BACK)adc_smp_work_item_callback,
-+ (void *)adapter,
-+ "adc_smp_work_item");
-+
-+ odm_initialize_work_item(
-+ dm,
-+ &dm->adcsmp.adc_smp_work_item_1,
-+ (RT_WORKITEM_CALL_BACK)adc_smp_work_item_callback,
-+ (void *)adapter,
-+ "adc_smp_work_item_1");
-+#endif
-+}
-+
-+void odm_free_all_work_items(struct dm_struct *dm)
-+{
-+#if USE_WORKITEM
-+
-+#ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY
-+ odm_free_work_item(&dm->dm_swat_table.phydm_sw_antenna_switch_workitem);
-+#endif
-+
-+#ifdef CONFIG_ADAPTIVE_SOML
-+ odm_free_work_item(&dm->dm_soml_table.phydm_adaptive_soml_workitem);
-+#endif
-+
-+#ifdef ODM_EVM_ENHANCE_ANTDIV
-+ odm_free_work_item(&dm->phydm_evm_antdiv_workitem);
-+#endif
-+
-+#if (defined(CONFIG_HL_SMART_ANTENNA))
-+ odm_free_work_item(&dm->dm_sat_table.hl_smart_antenna_workitem);
-+ odm_free_work_item(&dm->dm_sat_table.hl_smart_antenna_decision_workitem);
-+#endif
-+
-+#if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))
-+ odm_free_work_item(&dm->fast_ant_training_workitem);
-+#endif
-+ odm_free_work_item(&dm->ra_rpt_workitem);
-+/*odm_free_work_item((&dm->sbdcnt_workitem));*/
-+#endif
-+
-+#ifdef PHYDM_BEAMFORMING_SUPPORT
-+ odm_free_work_item((&dm->beamforming_info.txbf_info.txbf_enter_work_item));
-+ odm_free_work_item((&dm->beamforming_info.txbf_info.txbf_leave_work_item));
-+ odm_free_work_item((&dm->beamforming_info.txbf_info.txbf_fw_ndpa_work_item));
-+ odm_free_work_item((&dm->beamforming_info.txbf_info.txbf_clk_work_item));
-+ odm_free_work_item((&dm->beamforming_info.txbf_info.txbf_rate_work_item));
-+ odm_free_work_item((&dm->beamforming_info.txbf_info.txbf_status_work_item));
-+ odm_free_work_item((&dm->beamforming_info.txbf_info.txbf_reset_tx_path_work_item));
-+ odm_free_work_item((&dm->beamforming_info.txbf_info.txbf_get_tx_rate_work_item));
-+#endif
-+
-+#if (PHYDM_LA_MODE_SUPPORT == 1)
-+ odm_free_work_item((&dm->adcsmp.adc_smp_work_item));
-+ odm_free_work_item((&dm->adcsmp.adc_smp_work_item_1));
-+#endif
-+}
-+#endif /*#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)*/
-+
-+void odm_init_all_timers(struct dm_struct *dm)
-+{
-+#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))
-+ odm_ant_div_timers(dm, INIT_ANTDIV_TIMMER);
-+#endif
-+#if (defined(PHYDM_TDMA_DIG_SUPPORT))
-+#ifdef IS_USE_NEW_TDMA
-+ phydm_tdma_dig_timers(dm, INIT_TDMA_DIG_TIMMER);
-+#endif
-+#endif
-+#ifdef CONFIG_ADAPTIVE_SOML
-+ phydm_adaptive_soml_timers(dm, INIT_SOML_TIMMER);
-+#endif
-+#ifdef PHYDM_LNA_SAT_CHK_SUPPORT
-+#ifdef PHYDM_LNA_SAT_CHK_TYPE1
-+ phydm_lna_sat_chk_timers(dm, INIT_LNA_SAT_CHK_TIMMER);
-+#endif
-+#endif
-+
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+ odm_initialize_timer(dm, &dm->sbdcnt_timer,
-+ (void *)phydm_sbd_callback, NULL, "SbdTimer");
-+#ifdef PHYDM_BEAMFORMING_SUPPORT
-+ odm_initialize_timer(dm, &dm->beamforming_info.txbf_info.txbf_fw_ndpa_timer,
-+ (void *)hal_com_txbf_fw_ndpa_timer_callback, NULL,
-+ "txbf_fw_ndpa_timer");
-+#endif
-+#endif
-+
-+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
-+#ifdef PHYDM_BEAMFORMING_SUPPORT
-+ odm_initialize_timer(dm, &dm->beamforming_info.beamforming_timer,
-+ (void *)beamforming_sw_timer_callback, NULL,
-+ "beamforming_timer");
-+#endif
-+#endif
-+}
-+
-+void odm_cancel_all_timers(struct dm_struct *dm)
-+{
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+ /* @2012/01/12 MH Temp BSOD fix. We need to find NIC allocate mem fail reason in win7*/
-+ if (dm->adapter == NULL)
-+ return;
-+#endif
-+
-+#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))
-+ odm_ant_div_timers(dm, CANCEL_ANTDIV_TIMMER);
-+#endif
-+#ifdef PHYDM_TDMA_DIG_SUPPORT
-+#ifdef IS_USE_NEW_TDMA
-+ phydm_tdma_dig_timers(dm, CANCEL_TDMA_DIG_TIMMER);
-+#endif
-+#endif
-+#ifdef CONFIG_ADAPTIVE_SOML
-+ phydm_adaptive_soml_timers(dm, CANCEL_SOML_TIMMER);
-+#endif
-+#ifdef PHYDM_LNA_SAT_CHK_SUPPORT
-+#ifdef PHYDM_LNA_SAT_CHK_TYPE1
-+ phydm_lna_sat_chk_timers(dm, CANCEL_LNA_SAT_CHK_TIMMER);
-+#endif
-+#endif
-+
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+ odm_cancel_timer(dm, &dm->sbdcnt_timer);
-+#ifdef PHYDM_BEAMFORMING_SUPPORT
-+ odm_cancel_timer(dm, &dm->beamforming_info.txbf_info.txbf_fw_ndpa_timer);
-+#endif
-+#endif
-+
-+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
-+#ifdef PHYDM_BEAMFORMING_SUPPORT
-+ odm_cancel_timer(dm, &dm->beamforming_info.beamforming_timer);
-+#endif
-+#endif
-+}
-+
-+void odm_release_all_timers(struct dm_struct *dm)
-+{
-+#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))
-+ odm_ant_div_timers(dm, RELEASE_ANTDIV_TIMMER);
-+#endif
-+#ifdef PHYDM_TDMA_DIG_SUPPORT
-+#ifdef IS_USE_NEW_TDMA
-+ phydm_tdma_dig_timers(dm, RELEASE_TDMA_DIG_TIMMER);
-+#endif
-+#endif
-+#ifdef CONFIG_ADAPTIVE_SOML
-+ phydm_adaptive_soml_timers(dm, RELEASE_SOML_TIMMER);
-+#endif
-+#ifdef PHYDM_LNA_SAT_CHK_SUPPORT
-+#ifdef PHYDM_LNA_SAT_CHK_TYPE1
-+ phydm_lna_sat_chk_timers(dm, RELEASE_LNA_SAT_CHK_TIMMER);
-+#endif
-+#endif
-+
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+ odm_release_timer(dm, &dm->sbdcnt_timer);
-+#ifdef PHYDM_BEAMFORMING_SUPPORT
-+ odm_release_timer(dm, &dm->beamforming_info.txbf_info.txbf_fw_ndpa_timer);
-+#endif
-+#endif
-+
-+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
-+#ifdef PHYDM_BEAMFORMING_SUPPORT
-+ odm_release_timer(dm, &dm->beamforming_info.beamforming_timer);
-+#endif
-+#endif
-+}
-+
-+#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
-+void odm_init_all_threads(
-+ struct dm_struct *dm)
-+{
-+#ifdef TPT_THREAD
-+ k_tpt_task_init(dm->priv);
-+#endif
-+}
-+
-+void odm_stop_all_threads(
-+ struct dm_struct *dm)
-+{
-+#ifdef TPT_THREAD
-+ k_tpt_task_stop(dm->priv);
-+#endif
-+}
-+#endif
-+
-+#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
-+/* @Justin: According to the current RRSI to adjust Response Frame TX power,
-+ * 2012/11/05
-+ */
-+void odm_dtc(struct dm_struct *dm)
-+{
-+#ifdef CONFIG_DM_RESP_TXAGC
-+/* RSSI higher than this value, start to decade TX power */
-+#define DTC_BASE 35
-+
-+/* RSSI lower than this value, start to increase TX power */
-+#define DTC_DWN_BASE (DTC_BASE - 5)
-+
-+ /* RSSI vs TX power step mapping: decade TX power */
-+ static const u8 dtc_table_down[] = {
-+ DTC_BASE,
-+ (DTC_BASE + 5),
-+ (DTC_BASE + 10),
-+ (DTC_BASE + 15),
-+ (DTC_BASE + 20),
-+ (DTC_BASE + 25)};
-+
-+ /* RSSI vs TX power step mapping: increase TX power */
-+ static const u8 dtc_table_up[] = {
-+ DTC_DWN_BASE,
-+ (DTC_DWN_BASE - 5),
-+ (DTC_DWN_BASE - 10),
-+ (DTC_DWN_BASE - 15),
-+ (DTC_DWN_BASE - 15),
-+ (DTC_DWN_BASE - 20),
-+ (DTC_DWN_BASE - 20),
-+ (DTC_DWN_BASE - 25),
-+ (DTC_DWN_BASE - 25),
-+ (DTC_DWN_BASE - 30),
-+ (DTC_DWN_BASE - 35)};
-+
-+ u8 i;
-+ u8 dtc_steps = 0;
-+ u8 sign;
-+ u8 resp_txagc = 0;
-+
-+#if 0
-+ /* @As DIG is disabled, DTC is also disable */
-+ if (!(dm->support_ability & ODM_XXXXXX))
-+ return;
-+#endif
-+
-+ if (dm->rssi_min > DTC_BASE) {
-+ /* need to decade the CTS TX power */
-+ sign = 1;
-+ for (i = 0; i < ARRAY_SIZE(dtc_table_down); i++) {
-+ if (dtc_table_down[i] >= dm->rssi_min || dtc_steps >= 6)
-+ break;
-+ else
-+ dtc_steps++;
-+ }
-+ }
-+#if 0
-+ else if (dm->rssi_min > DTC_DWN_BASE) {
-+ /* needs to increase the CTS TX power */
-+ sign = 0;
-+ dtc_steps = 1;
-+ for (i = 0; i < ARRAY_SIZE(dtc_table_up); i++) {
-+ if (dtc_table_up[i] <= dm->rssi_min || dtc_steps >= 10)
-+ break;
-+ else
-+ dtc_steps++;
-+ }
-+ }
-+#endif
-+ else {
-+ sign = 0;
-+ dtc_steps = 0;
-+ }
-+
-+ resp_txagc = dtc_steps | (sign << 4);
-+ resp_txagc = resp_txagc | (resp_txagc << 5);
-+ odm_write_1byte(dm, 0x06d9, resp_txagc);
-+
-+ PHYDM_DBG(dm, ODM_COMP_PWR_TRAIN,
-+ "%s rssi_min:%u, set RESP_TXAGC to %s %u\n", __func__,
-+ dm->rssi_min, sign ? "minus" : "plus", dtc_steps);
-+#endif /* @CONFIG_RESP_TXAGC_ADJUST */
-+}
-+
-+#endif /* @#if (DM_ODM_SUPPORT_TYPE == ODM_CE) */
-+
-+/*@<20170126, BB-Kevin>8188F D-CUT DC cancellation and 8821C*/
-+void phydm_dc_cancellation(struct dm_struct *dm)
-+{
-+#ifdef PHYDM_DC_CANCELLATION
-+ u32 offset_i_hex[PHYDM_MAX_RF_PATH] = {0};
-+ u32 offset_q_hex[PHYDM_MAX_RF_PATH] = {0};
-+ u32 reg_value32[PHYDM_MAX_RF_PATH] = {0};
-+ u8 path = RF_PATH_A;
-+ u8 set_result;
-+
-+ if (!(dm->support_ic_type & ODM_DC_CANCELLATION_SUPPORT))
-+ return;
-+ if ((dm->support_ic_type & ODM_RTL8188F) &&
-+ dm->cut_version < ODM_CUT_D)
-+ return;
-+ if ((dm->support_ic_type & ODM_RTL8192F) &&
-+ dm->cut_version == ODM_CUT_A)
-+ return;
-+
-+ PHYDM_DBG(dm, ODM_COMP_API, "%s ======>\n", __func__);
-+
-+ /*@DC_Estimation (only for 2x2 ic now) */
-+
-+ for (path = RF_PATH_A; path < PHYDM_MAX_RF_PATH; path++) {
-+ if (path > RF_PATH_A &&
-+ dm->support_ic_type & (ODM_RTL8821C | ODM_RTL8188F |
-+ ODM_RTL8710B | ODM_RTL8721D))
-+ break;
-+ else if (path > RF_PATH_B &&
-+ dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8192F))
-+ break;
-+ if (phydm_stop_ic_trx(dm, PHYDM_SET) == PHYDM_SET_FAIL) {
-+ PHYDM_DBG(dm, ODM_COMP_API, "STOP_TRX_FAIL\n");
-+ return;
-+ }
-+ odm_write_dig(dm, 0x7e);
-+ /*@Disable LNA*/
-+ if (dm->support_ic_type & ODM_RTL8821C)
-+ halrf_rf_lna_setting(dm, HALRF_LNA_DISABLE);
-+ /*Turn off 3-wire*/
-+ phydm_stop_3_wire(dm, PHYDM_SET);
-+ if (dm->support_ic_type & (ODM_RTL8188F | ODM_RTL8710B)) {
-+ /*set debug port to 0x235*/
-+ if (!phydm_set_bb_dbg_port(dm, DBGPORT_PRI_1, 0x235)) {
-+ PHYDM_DBG(dm, ODM_COMP_API,
-+ "Set Debug port Fail\n");
-+ return;
-+ }
-+ } else if (dm->support_ic_type & ODM_RTL8721D) {
-+ /*set debug port to 0x200*/
-+ if (!phydm_set_bb_dbg_port(dm, DBGPORT_PRI_2, 0x200)) {
-+ PHYDM_DBG(dm, ODM_COMP_API,
-+ "Set Debug port Fail\n");
-+ return;
-+ }
-+ } else if (dm->support_ic_type & ODM_RTL8821C) {
-+ if (!phydm_set_bb_dbg_port(dm, DBGPORT_PRI_1, 0x200)) {
-+ /*set debug port to 0x200*/
-+ PHYDM_DBG(dm, ODM_COMP_API,
-+ "Set Debug port Fail\n");
-+ return;
-+ }
-+ phydm_bb_dbg_port_header_sel(dm, 0x0);
-+ } else if (dm->support_ic_type & ODM_RTL8822B) {
-+ if (path == RF_PATH_A &&
-+ !phydm_set_bb_dbg_port(dm, DBGPORT_PRI_1, 0x200)) {
-+ /*set debug port to 0x200*/
-+ PHYDM_DBG(dm, ODM_COMP_API,
-+ "Set Debug port Fail\n");
-+ return;
-+ }
-+ if (path == RF_PATH_B &&
-+ !phydm_set_bb_dbg_port(dm, DBGPORT_PRI_1, 0x202)) {
-+ /*set debug port to 0x200*/
-+ PHYDM_DBG(dm, ODM_COMP_API,
-+ "Set Debug port Fail\n");
-+ return;
-+ }
-+ phydm_bb_dbg_port_header_sel(dm, 0x0);
-+ } else if (dm->support_ic_type & ODM_RTL8192F) {
-+ if (path == RF_PATH_A &&
-+ !phydm_set_bb_dbg_port(dm, DBGPORT_PRI_1, 0x235)) {
-+ /*set debug port to 0x235*/
-+ PHYDM_DBG(dm, ODM_COMP_API,
-+ "Set Debug port Fail\n");
-+ return;
-+ }
-+ if (path == RF_PATH_B &&
-+ !phydm_set_bb_dbg_port(dm, DBGPORT_PRI_1, 0x23d)) {
-+ /*set debug port to 0x23d*/
-+ PHYDM_DBG(dm, ODM_COMP_API,
-+ "Set Debug port Fail\n");
-+ return;
-+ }
-+ }
-+
-+ /*@disable CCK DCNF*/
-+ odm_set_bb_reg(dm, R_0xa78, MASKBYTE1, 0x0);
-+
-+ PHYDM_DBG(dm, ODM_COMP_API, "DC cancellation Begin!!!\n");
-+
-+ phydm_stop_ck320(dm, true); /*stop ck320*/
-+
-+ /* the same debug port both for path-a and path-b*/
-+ reg_value32[path] = phydm_get_bb_dbg_port_val(dm);
-+
-+ phydm_stop_ck320(dm, false); /*start ck320*/
-+
-+ phydm_release_bb_dbg_port(dm);
-+ /* @Turn on 3-wire*/
-+ phydm_stop_3_wire(dm, PHYDM_REVERT);
-+ /* @Enable LNA*/
-+ if (dm->support_ic_type & ODM_RTL8821C)
-+ halrf_rf_lna_setting(dm, HALRF_LNA_ENABLE);
-+
-+ odm_write_dig(dm, 0x20);
-+
-+ set_result = phydm_stop_ic_trx(dm, PHYDM_REVERT);
-+
-+ PHYDM_DBG(dm, ODM_COMP_API, "DC cancellation OK!!!\n");
-+ }
-+
-+ /*@DC_Cancellation*/
-+ /*@DC compensation to CCK data path*/
-+ odm_set_bb_reg(dm, R_0xa9c, BIT(20), 0x1);
-+ if (dm->support_ic_type & (ODM_RTL8188F | ODM_RTL8710B)) {
-+ offset_i_hex[0] = (reg_value32[0] & 0xffc0000) >> 18;
-+ offset_q_hex[0] = (reg_value32[0] & 0x3ff00) >> 8;
-+
-+ /*@Before filling into registers,
-+ *offset should be multiplexed (-1)
-+ */
-+ offset_i_hex[0] = (offset_i_hex[0] >= 0x200) ?
-+ (0x400 - offset_i_hex[0]) :
-+ (0x1ff - offset_i_hex[0]);
-+ offset_q_hex[0] = (offset_q_hex[0] >= 0x200) ?
-+ (0x400 - offset_q_hex[0]) :
-+ (0x1ff - offset_q_hex[0]);
-+
-+ odm_set_bb_reg(dm, R_0x950, 0x1ff, offset_i_hex[0]);
-+ odm_set_bb_reg(dm, R_0x950, 0x1ff0000, offset_q_hex[0]);
-+ } else if (dm->support_ic_type & (ODM_RTL8821C | ODM_RTL8822B)) {
-+ /* Path-a */
-+ offset_i_hex[0] = (reg_value32[0] & 0xffc00) >> 10;
-+ offset_q_hex[0] = reg_value32[0] & 0x3ff;
-+
-+ /*@Before filling into registers,
-+ *offset should be multiplexed (-1)
-+ */
-+ offset_i_hex[0] = 0x400 - offset_i_hex[0];
-+ offset_q_hex[0] = 0x400 - offset_q_hex[0];
-+
-+ odm_set_bb_reg(dm, R_0xc10, 0x3c000000,
-+ (0x3c0 & offset_i_hex[0]) >> 6);
-+ odm_set_bb_reg(dm, R_0xc10, 0xfc00, 0x3f & offset_i_hex[0]);
-+ odm_set_bb_reg(dm, R_0xc14, 0x3c000000,
-+ (0x3c0 & offset_q_hex[0]) >> 6);
-+ odm_set_bb_reg(dm, R_0xc14, 0xfc00, 0x3f & offset_q_hex[0]);
-+
-+ /* Path-b */
-+ if (dm->rf_type > RF_1T1R) {
-+ offset_i_hex[1] = (reg_value32[1] & 0xffc00) >> 10;
-+ offset_q_hex[1] = reg_value32[1] & 0x3ff;
-+
-+ /*@Before filling into registers,
-+ *offset should be multiplexed (-1)
-+ */
-+ offset_i_hex[1] = 0x400 - offset_i_hex[1];
-+ offset_q_hex[1] = 0x400 - offset_q_hex[1];
-+
-+ odm_set_bb_reg(dm, R_0xe10, 0x3c000000,
-+ (0x3c0 & offset_i_hex[1]) >> 6);
-+ odm_set_bb_reg(dm, R_0xe10, 0xfc00,
-+ 0x3f & offset_i_hex[1]);
-+ odm_set_bb_reg(dm, R_0xe14, 0x3c000000,
-+ (0x3c0 & offset_q_hex[1]) >> 6);
-+ odm_set_bb_reg(dm, R_0xe14, 0xfc00,
-+ 0x3f & offset_q_hex[1]);
-+ }
-+ } else if (dm->support_ic_type & (ODM_RTL8192F)) {
-+ /* Path-a I:df4[27:18],Q:df4[17:8]*/
-+ offset_i_hex[0] = (reg_value32[0] & 0xffc0000) >> 18;
-+ offset_q_hex[0] = (reg_value32[0] & 0x3ff00) >> 8;
-+
-+ /*@Before filling into registers,
-+ *offset should be multiplexed (-1)
-+ */
-+ offset_i_hex[0] = (offset_i_hex[0] >= 0x200) ?
-+ (0x400 - offset_i_hex[0]) :
-+ (0xff - offset_i_hex[0]);
-+ offset_q_hex[0] = (offset_q_hex[0] >= 0x200) ?
-+ (0x400 - offset_q_hex[0]) :
-+ (0xff - offset_q_hex[0]);
-+ /*Path-a I:c10[7:0],Q:c10[15:8]*/
-+ odm_set_bb_reg(dm, R_0xc10, 0xff, offset_i_hex[0]);
-+ odm_set_bb_reg(dm, R_0xc10, 0xff00, offset_q_hex[0]);
-+
-+ /* Path-b */
-+ if (dm->rf_type > RF_1T1R) {
-+ /* @I:df4[27:18],Q:df4[17:8]*/
-+ offset_i_hex[1] = (reg_value32[1] & 0xffc0000) >> 18;
-+ offset_q_hex[1] = (reg_value32[1] & 0x3ff00) >> 8;
-+
-+ /*@Before filling into registers,
-+ *offset should be multiplexed (-1)
-+ */
-+ offset_i_hex[1] = (offset_i_hex[1] >= 0x200) ?
-+ (0x400 - offset_i_hex[1]) :
-+ (0xff - offset_i_hex[1]);
-+ offset_q_hex[1] = (offset_q_hex[1] >= 0x200) ?
-+ (0x400 - offset_q_hex[1]) :
-+ (0xff - offset_q_hex[1]);
-+ /*Path-b I:c18[7:0],Q:c18[15:8]*/
-+ odm_set_bb_reg(dm, R_0xc18, 0xff, offset_i_hex[1]);
-+ odm_set_bb_reg(dm, R_0xc18, 0xff00, offset_q_hex[1]);
-+ }
-+ } else if (dm->support_ic_type & (ODM_RTL8721D)) {
-+ /*judy modified 20180517*/
-+ offset_i_hex[0] = (reg_value32[0] & 0xff800) >> 11;
-+ offset_q_hex[0] = (reg_value32[0] & 0x3fe) >> 1;
-+
-+ /*@Before filling into registers,
-+ *offset should be multiplexed (-1)
-+ */
-+ offset_i_hex[0] = 0x200 - offset_i_hex[0];
-+ offset_q_hex[0] = 0x200 - offset_q_hex[0];
-+
-+ odm_set_bb_reg(dm, R_0x950, 0x1ff, offset_i_hex[0]);
-+ odm_set_bb_reg(dm, R_0x950, 0x1ff0000, offset_q_hex[0]);
-+ }
-+#endif
-+}
-+
-+void phydm_receiver_blocking(void *dm_void)
-+{
-+#ifdef CONFIG_RECEIVER_BLOCKING
-+ struct dm_struct *dm = (struct dm_struct *)dm_void;
-+ u32 chnl = *dm->channel;
-+ u8 bw = *dm->band_width;
-+ u32 bb_regf0 = odm_get_bb_reg(dm, R_0xf0, 0xf000);
-+
-+ if (!(dm->support_ic_type & ODM_RECEIVER_BLOCKING_SUPPORT) ||
-+ !(dm->support_ability & ODM_BB_ADAPTIVITY))
-+ return;
-+
-+ if ((dm->support_ic_type & ODM_RTL8188E && bb_regf0 < 8) ||
-+ dm->support_ic_type & ODM_RTL8192E) {
-+ /*@8188E_T version*/
-+ if (dm->consecutive_idlel_time <= 10 || *dm->mp_mode)
-+ goto end;
-+
-+ if (bw == CHANNEL_WIDTH_20 && chnl == 1) {
-+ phydm_nbi_setting(dm, FUNC_ENABLE, chnl, 20, 2410,
-+ PHYDM_DONT_CARE);
-+ dm->is_rx_blocking_en = true;
-+ } else if ((bw == CHANNEL_WIDTH_20) && (chnl == 13)) {
-+ phydm_nbi_setting(dm, FUNC_ENABLE, chnl, 20, 2473,
-+ PHYDM_DONT_CARE);
-+ dm->is_rx_blocking_en = true;
-+ } else if (dm->is_rx_blocking_en && chnl != 1 && chnl != 13) {
-+ phydm_nbi_enable(dm, FUNC_DISABLE);
-+ odm_set_bb_reg(dm, R_0xc40, 0x1f000000, 0x1f);
-+ dm->is_rx_blocking_en = false;
-+ }
-+ return;
-+ } else if ((dm->support_ic_type & ODM_RTL8188E && bb_regf0 >= 8)) {
-+ /*@8188E_S version*/
-+ if (dm->consecutive_idlel_time <= 10 || *dm->mp_mode)
-+ goto end;
-+
-+ if (bw == CHANNEL_WIDTH_20 && chnl == 13) {
-+ phydm_nbi_setting(dm, FUNC_ENABLE, chnl, 20, 2473,
-+ PHYDM_DONT_CARE);
-+ dm->is_rx_blocking_en = true;
-+ } else if (dm->is_rx_blocking_en && chnl != 13) {
-+ phydm_nbi_enable(dm, FUNC_DISABLE);
-+ odm_set_bb_reg(dm, R_0xc40, 0x1f000000, 0x1f);
-+ dm->is_rx_blocking_en = false;
-+ }
-+ return;
-+ }
-+
-+end:
-+ if (dm->is_rx_blocking_en) {
-+ phydm_nbi_enable(dm, FUNC_DISABLE);
-+ odm_set_bb_reg(dm, R_0xc40, 0x1f000000, 0x1f);
-+ dm->is_rx_blocking_en = false;
-+ }
-+#endif
-+}
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm.h linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm.h
-new file mode 100644
-index 000000000..820be2fa8
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm.h
-@@ -0,0 +1,1356 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ * The full GNU General Public License is included in this distribution in the
-+ * file called LICENSE.
-+ *
-+ * Contact Information:
-+ * wlanfae
-+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
-+ * Hsinchu 300, Taiwan.
-+ *
-+ * Larry Finger
-+ *
-+ *****************************************************************************/
-+
-+#ifndef __HALDMOUTSRC_H__
-+#define __HALDMOUTSRC_H__
-+
-+/*@============================================================*/
-+/*@include files*/
-+/*@============================================================*/
-+/*PHYDM header*/
-+#include "phydm_pre_define.h"
-+#include "phydm_features.h"
-+#include "phydm_dig.h"
-+#ifdef CONFIG_PATH_DIVERSITY
-+#include "phydm_pathdiv.h"
-+#endif
-+#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
-+#include "phydm_antdiv.h"
-+#endif
-+
-+#include "phydm_soml.h"
-+
-+#ifdef CONFIG_SMART_ANTENNA
-+#include "phydm_smt_ant.h"
-+#endif
-+#ifdef CONFIG_ANT_DETECTION
-+#include "phydm_antdect.h"
-+#endif
-+#include "phydm_rainfo.h"
-+#ifdef CONFIG_DYNAMIC_TX_TWR
-+#include "phydm_dynamictxpower.h"
-+#endif
-+#include "phydm_cfotracking.h"
-+#include "phydm_adaptivity.h"
-+#include "phydm_dfs.h"
-+#include "phydm_ccx.h"
-+#include "txbf/phydm_hal_txbf_api.h"
-+#if (PHYDM_LA_MODE_SUPPORT == 1)
-+#include "phydm_adc_sampling.h"
-+#endif
-+#ifdef CONFIG_PSD_TOOL
-+#include "phydm_psd.h"
-+#endif
-+#ifdef PHYDM_PRIMARY_CCA
-+#include "phydm_primary_cca.h"
-+#endif
-+#include "phydm_cck_pd.h"
-+#include "phydm_rssi_monitor.h"
-+#ifdef PHYDM_AUTO_DEGBUG
-+#include "phydm_auto_dbg.h"
-+#endif
-+#include "phydm_math_lib.h"
-+#include "phydm_noisemonitor.h"
-+#include "phydm_api.h"
-+#ifdef PHYDM_POWER_TRAINING_SUPPORT
-+#include "phydm_pow_train.h"
-+#endif
-+#ifdef PHYDM_LNA_SAT_CHK_SUPPORT
-+#include "phydm_lna_sat.h"
-+#endif
-+#ifdef PHYDM_PMAC_TX_SETTING_SUPPORT
-+#include "phydm_pmac_tx_setting.h"
-+#endif
-+#ifdef PHYDM_MP_SUPPORT
-+#include "phydm_mp.h"
-+#endif
-+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
-+ #include "phydm_beamforming.h"
-+#endif
-+
-+#include "phydm_regtable.h"
-+
-+/*@HALRF header*/
-+#include "halrf/halrf_iqk.h"
-+#include "halrf/halrf_dpk.h"
-+#include "halrf/halrf.h"
-+#include "halrf/halrf_powertracking.h"
-+#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
-+ #include "halrf/halphyrf_ap.h"
-+#elif(DM_ODM_SUPPORT_TYPE & (ODM_CE))
-+ #include "halrf/halphyrf_ce.h"
-+#elif (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
-+ #include "halrf/halphyrf_win.h"
-+#elif(DM_ODM_SUPPORT_TYPE & (ODM_IOT))
-+ #include "halrf/halphyrf_iot.h"
-+#endif
-+
-+extern const u16 phy_rate_table[28];
-+
-+/*@============================================================*/
-+/*@Definition */
-+/*@============================================================*/
-+
-+/* Traffic load decision */
-+#define TRAFFIC_NO_TP 0
-+#define TRAFFIC_ULTRA_LOW 1
-+#define TRAFFIC_LOW 2
-+#define TRAFFIC_MID 3
-+#define TRAFFIC_HIGH 4
-+
-+#define NONE 0
-+
-+#if defined(DM_ODM_CE_MAC80211)
-+#define MAX_2(x, y) \
-+ __max2(typeof(x), typeof(y), \
-+ x, y)
-+#define __max2(t1, t2, x, y) ({ \
-+ t1 m80211_max1 = (x); \
-+ t2 m80211_max2 = (y); \
-+ m80211_max1 > m80211_max2 ? m80211_max1 : m80211_max2; })
-+
-+#define MIN_2(x, y) \
-+ __min2(typeof(x), typeof(y), \
-+ x, y)
-+#define __min2(t1, t2, x, y) ({ \
-+ t1 m80211_min1 = (x); \
-+ t2 m80211_min2 = (y); \
-+ m80211_min1 < m80211_min2 ? m80211_min1 : m80211_min2; })
-+
-+#define DIFF_2(x, y) \
-+ __diff2(typeof(x), typeof(y), \
-+ x, y)
-+#define __diff2(t1, t2, x, y) ({ \
-+ t1 __d1 = (x); \
-+ t2 __d2 = (y); \
-+ (__d1 >= __d2) ? (__d1 - __d2) : (__d2 - __d1); })
-+#else
-+#define MAX_2(_x_, _y_) (((_x_) > (_y_)) ? (_x_) : (_y_))
-+#define MIN_2(_x_, _y_) (((_x_) < (_y_)) ? (_x_) : (_y_))
-+#define DIFF_2(_x_, _y_) ((_x_ >= _y_) ? (_x_ - _y_) : (_y_ - _x_))
-+#endif
-+
-+#define IS_GREATER(_x_, _y_) (((_x_) >= (_y_)) ? true : false)
-+#define IS_LESS(_x_, _y_) (((_x_) < (_y_)) ? true : false)
-+
-+#if defined(DM_ODM_CE_MAC80211)
-+#define BYTE_DUPLICATE_2_DWORD(B0) ({ \
-+ u32 __b_dup = (B0);\
-+ (((__b_dup) << 24) | ((__b_dup) << 16) | ((__b_dup) << 8) | (__b_dup));\
-+ })
-+#else
-+#define BYTE_DUPLICATE_2_DWORD(B0) \
-+ (((B0) << 24) | ((B0) << 16) | ((B0) << 8) | (B0))
-+#endif
-+#define BYTE_2_DWORD(B3, B2, B1, B0) \
-+ (((B3) << 24) | ((B2) << 16) | ((B1) << 8) | (B0))
-+#define BIT_2_BYTE(B3, B2, B1, B0) \
-+ (((B3) << 3) | ((B2) << 2) | ((B1) << 1) | (B0))
-+
-+/*@For cmn sta info*/
-+#if defined(DM_ODM_CE_MAC80211)
-+#define is_sta_active(sta) ({ \
-+ struct cmn_sta_info *__sta = (sta); \
-+ ((__sta) && (__sta->dm_ctrl & STA_DM_CTRL_ACTIVE)); \
-+ })
-+
-+#define IS_FUNC_EN(name) ({ \
-+ u8 *__is_func_name = (name); \
-+ (__is_func_name) && (*__is_func_name); \
-+ })
-+#else
-+#define is_sta_active(sta) ((sta) && (sta->dm_ctrl & STA_DM_CTRL_ACTIVE))
-+
-+#define IS_FUNC_EN(name) ((name) && (*name))
-+#endif
-+
-+#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
-+ #define PHYDM_WATCH_DOG_PERIOD 1 /*second*/
-+#else
-+ #define PHYDM_WATCH_DOG_PERIOD 2 /*second*/
-+#endif
-+
-+#define PHY_HIST_SIZE 12
-+
-+/*@============================================================*/
-+/*structure and define*/
-+/*@============================================================*/
-+
-+#define dm_type_by_fw 0
-+#define dm_type_by_driver 1
-+
-+#ifdef BB_RAM_SUPPORT
-+
-+struct phydm_bb_ram_per_sta {
-+ /* @Reg0x1E84 for RAM I/O*/
-+ boolean hw_igi_en;
-+ boolean tx_pwr_offset0_en;
-+ boolean tx_pwr_offset1_en;
-+ /* @ macid from 0 to 63, above 63 => mapping to 63*/
-+ u8 macid_addr;
-+ /* @hw_igi value for paths after packet Tx in a period of time*/
-+ u8 hw_igi;
-+ /* @tx_pwr_offset0 offset for Tx power index*/
-+ s8 tx_pwr_offset0;
-+ s8 tx_pwr_offset1;
-+
-+};
-+
-+struct phydm_bb_ram_ctrl {
-+ /*@ For 98F/14B/22C/12F, each TxAGC step will be 0.25dB*/
-+ struct phydm_bb_ram_per_sta pram_sta_ctrl[ODM_ASSOCIATE_ENTRY_NUM];
-+ /*------------ For table2 do not set power offset by macid --------*/
-+ /* For type == 2'b10, 0x1e70[22:16] = tx_pwr_offset_reg0, 0x1e70[23] = enable */
-+ boolean tx_pwr_offset_reg0_en;
-+ u8 tx_pwr_offset_reg0;
-+ /* For type == 2'b11, 0x1e70[30:24] = tx_pwr_offset_reg1, 0x1e70[31] = enable */
-+ boolean tx_pwr_offset_reg1_en;
-+ u8 tx_pwr_offset_reg1;
-+};
-+
-+#endif
-+
-+struct phydm_phystatus_statistic {
-+ /*@[CCK]*/
-+ u32 rssi_cck_sum;
-+ u32 rssi_cck_cnt;
-+ /*@[OFDM]*/
-+ u32 rssi_ofdm_sum;
-+ u32 rssi_ofdm_cnt;
-+ u32 evm_ofdm_sum;
-+ u32 snr_ofdm_sum;
-+ u16 evm_ofdm_hist[PHY_HIST_SIZE];
-+ u16 snr_ofdm_hist[PHY_HIST_SIZE];
-+ /*@[1SS]*/
-+ u32 rssi_1ss_cnt;
-+ u32 rssi_1ss_sum;
-+ u32 evm_1ss_sum;
-+ u32 snr_1ss_sum;
-+ u16 evm_1ss_hist[PHY_HIST_SIZE];
-+ u16 snr_1ss_hist[PHY_HIST_SIZE];
-+ /*@[2SS]*/
-+ #if (defined(PHYDM_COMPILE_ABOVE_2SS))
-+ u32 rssi_2ss_cnt;
-+ u32 rssi_2ss_sum[2];
-+ u32 evm_2ss_sum[2];
-+ u32 snr_2ss_sum[2];
-+ u16 evm_2ss_hist[2][PHY_HIST_SIZE];
-+ u16 snr_2ss_hist[2][PHY_HIST_SIZE];
-+ #endif
-+ /*@[3SS]*/
-+ #if (defined(PHYDM_COMPILE_ABOVE_3SS))
-+ u32 rssi_3ss_cnt;
-+ u32 rssi_3ss_sum[3];
-+ u32 evm_3ss_sum[3];
-+ u32 snr_3ss_sum[3];
-+ u16 evm_3ss_hist[3][PHY_HIST_SIZE];
-+ u16 snr_3ss_hist[3][PHY_HIST_SIZE];
-+ #endif
-+ /*@[4SS]*/
-+ #if (defined(PHYDM_COMPILE_ABOVE_4SS))
-+ u32 rssi_4ss_cnt;
-+ u32 rssi_4ss_sum[4];
-+ u32 evm_4ss_sum[4];
-+ u32 snr_4ss_sum[4];
-+ u16 evm_4ss_hist[4][PHY_HIST_SIZE];
-+ u16 snr_4ss_hist[4][PHY_HIST_SIZE];
-+ #endif
-+};
-+
-+struct phydm_phystatus_avg {
-+ /*@[CCK]*/
-+ u8 rssi_cck_avg;
-+ /*@[OFDM]*/
-+ u8 rssi_ofdm_avg;
-+ u8 evm_ofdm_avg;
-+ u8 snr_ofdm_avg;
-+ /*@[1SS]*/
-+ u8 rssi_1ss_avg;
-+ u8 evm_1ss_avg;
-+ u8 snr_1ss_avg;
-+ /*@[2SS]*/
-+ #if (defined(PHYDM_COMPILE_ABOVE_2SS))
-+ u8 rssi_2ss_avg[2];
-+ u8 evm_2ss_avg[2];
-+ u8 snr_2ss_avg[2];
-+ #endif
-+ /*@[3SS]*/
-+ #if (defined(PHYDM_COMPILE_ABOVE_3SS))
-+ u8 rssi_3ss_avg[3];
-+ u8 evm_3ss_avg[3];
-+ u8 snr_3ss_avg[3];
-+ #endif
-+ /*@[4SS]*/
-+ #if (defined(PHYDM_COMPILE_ABOVE_4SS))
-+ u8 rssi_4ss_avg[4];
-+ u8 evm_4ss_avg[4];
-+ u8 snr_4ss_avg[4];
-+ #endif
-+};
-+
-+struct odm_phy_dbg_info {
-+ /*@ODM Write,debug info*/
-+ u32 num_qry_phy_status_cck;
-+ u32 num_qry_phy_status_ofdm;
-+#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1) || (defined(PHYSTS_3RD_TYPE_SUPPORT))
-+ u32 num_qry_mu_pkt;
-+ u32 num_qry_bf_pkt;
-+ u16 num_mu_vht_pkt[VHT_RATE_NUM];
-+ boolean is_ldpc_pkt;
-+ boolean is_stbc_pkt;
-+ u8 num_of_ppdu[4];
-+ u8 gid_num[4];
-+#endif
-+ u32 condi_num; /*@condition number U(18,4)*/
-+ u8 condi_num_cdf[CN_CNT_MAX];
-+ u8 num_qry_beacon_pkt;
-+ u8 beacon_cnt_in_period; /*@beacon cnt within watchdog period*/
-+ u8 beacon_phy_rate;
-+ u8 show_phy_sts_all_pkt; /*@Show phy status witch not match BSSID*/
-+ u16 show_phy_sts_max_cnt; /*@show number of phy-status row data per PHYDM watchdog*/
-+ u16 show_phy_sts_cnt;
-+ u16 num_qry_legacy_pkt[LEGACY_RATE_NUM];
-+ u16 num_qry_ht_pkt[HT_RATE_NUM];
-+ u16 num_qry_pkt_sc_20m[LOW_BW_RATE_NUM]; /*@20M SC*/
-+ boolean ht_pkt_not_zero;
-+ boolean low_bw_20_occur;
-+ #if ODM_IC_11AC_SERIES_SUPPORT || defined(PHYDM_IC_JGR3_SERIES_SUPPORT)
-+ u16 num_qry_vht_pkt[VHT_RATE_NUM];
-+ u16 num_qry_pkt_sc_40m[LOW_BW_RATE_NUM]; /*@40M SC*/
-+ boolean vht_pkt_not_zero;
-+ boolean low_bw_40_occur;
-+ #endif
-+ u16 snr_hist_th[PHY_HIST_SIZE - 1];
-+ u16 evm_hist_th[PHY_HIST_SIZE - 1];
-+ #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
-+ s16 cfo_tail[4]; /* per-path's cfo_tail */
-+ #endif
-+ struct phydm_phystatus_statistic physts_statistic_info;
-+ struct phydm_phystatus_avg phystatus_statistic_avg;
-+};
-+
-+enum odm_cmninfo {
-+ /*@Fixed value*/
-+ /*@-----------HOOK BEFORE REG INIT-----------*/
-+ ODM_CMNINFO_PLATFORM = 0,
-+ ODM_CMNINFO_ABILITY,
-+ ODM_CMNINFO_INTERFACE,
-+ ODM_CMNINFO_MP_TEST_CHIP,
-+ ODM_CMNINFO_IC_TYPE,
-+ ODM_CMNINFO_CUT_VER,
-+ ODM_CMNINFO_FAB_VER,
-+ ODM_CMNINFO_FW_VER,
-+ ODM_CMNINFO_FW_SUB_VER,
-+ ODM_CMNINFO_RF_TYPE,
-+ ODM_CMNINFO_RFE_TYPE,
-+ ODM_CMNINFO_DPK_EN,
-+ ODM_CMNINFO_BOARD_TYPE,
-+ ODM_CMNINFO_PACKAGE_TYPE,
-+ ODM_CMNINFO_EXT_LNA,
-+ ODM_CMNINFO_5G_EXT_LNA,
-+ ODM_CMNINFO_EXT_PA,
-+ ODM_CMNINFO_5G_EXT_PA,
-+ ODM_CMNINFO_GPA,
-+ ODM_CMNINFO_APA,
-+ ODM_CMNINFO_GLNA,
-+ ODM_CMNINFO_ALNA,
-+ ODM_CMNINFO_TDMA,
-+ ODM_CMNINFO_EXT_TRSW,
-+ ODM_CMNINFO_EXT_LNA_GAIN,
-+ ODM_CMNINFO_PATCH_ID,
-+ ODM_CMNINFO_BINHCT_TEST,
-+ ODM_CMNINFO_BWIFI_TEST,
-+ ODM_CMNINFO_SMART_CONCURRENT,
-+ ODM_CMNINFO_CONFIG_BB_RF,
-+ ODM_CMNINFO_IQKPAOFF,
-+ ODM_CMNINFO_HUBUSBMODE,
-+ ODM_CMNINFO_FWDWRSVDPAGEINPROGRESS,
-+ ODM_CMNINFO_TX_TP,
-+ ODM_CMNINFO_RX_TP,
-+ ODM_CMNINFO_SOUNDING_SEQ,
-+ ODM_CMNINFO_REGRFKFREEENABLE,
-+ ODM_CMNINFO_RFKFREEENABLE,
-+ ODM_CMNINFO_NORMAL_RX_PATH_CHANGE,
-+ ODM_CMNINFO_EFUSE0X3D8,
-+ ODM_CMNINFO_EFUSE0X3D7,
-+ ODM_CMNINFO_SOFT_AP_SPECIAL_SETTING,
-+ ODM_CMNINFO_X_CAP_SETTING,
-+ ODM_CMNINFO_ADVANCE_OTA,
-+ ODM_CMNINFO_HP_HWID,
-+ /*@-----------HOOK BEFORE REG INIT-----------*/
-+
-+ /*@Dynamic value:*/
-+
-+ /*@--------- POINTER REFERENCE-----------*/
-+ ODM_CMNINFO_TX_UNI,
-+ ODM_CMNINFO_RX_UNI,
-+ ODM_CMNINFO_BAND,
-+ ODM_CMNINFO_SEC_CHNL_OFFSET,
-+ ODM_CMNINFO_SEC_MODE,
-+ ODM_CMNINFO_BW,
-+ ODM_CMNINFO_CHNL,
-+ ODM_CMNINFO_FORCED_RATE,
-+ ODM_CMNINFO_ANT_DIV,
-+ ODM_CMNINFO_PATH_DIV,
-+ ODM_CMNINFO_ADAPTIVE_SOML,
-+ ODM_CMNINFO_ADAPTIVITY,
-+ ODM_CMNINFO_SCAN,
-+ ODM_CMNINFO_POWER_SAVING,
-+ ODM_CMNINFO_ONE_PATH_CCA,
-+ ODM_CMNINFO_DRV_STOP,
-+ ODM_CMNINFO_PNP_IN,
-+ ODM_CMNINFO_INIT_ON,
-+ ODM_CMNINFO_ANT_TEST,
-+ ODM_CMNINFO_NET_CLOSED,
-+ ODM_CMNINFO_P2P_LINK,
-+ ODM_CMNINFO_FCS_MODE,
-+ ODM_CMNINFO_IS1ANTENNA,
-+ ODM_CMNINFO_RFDEFAULTPATH,
-+ ODM_CMNINFO_DFS_MASTER_ENABLE,
-+ ODM_CMNINFO_FORCE_TX_ANT_BY_TXDESC,
-+ ODM_CMNINFO_SET_S0S1_DEFAULT_ANTENNA,
-+ ODM_CMNINFO_SOFT_AP_MODE,
-+ ODM_CMNINFO_MP_MODE,
-+ ODM_CMNINFO_INTERRUPT_MASK,
-+ ODM_CMNINFO_BB_OPERATION_MODE,
-+ ODM_CMNINFO_BF_ANTDIV_DECISION,
-+ /*@--------- POINTER REFERENCE-----------*/
-+
-+ /*@------------CALL BY VALUE-------------*/
-+ ODM_CMNINFO_WIFI_DIRECT,
-+ ODM_CMNINFO_WIFI_DISPLAY,
-+ ODM_CMNINFO_LINK_IN_PROGRESS,
-+ ODM_CMNINFO_LINK,
-+ ODM_CMNINFO_CMW500LINK,
-+ ODM_CMNINFO_STATION_STATE,
-+ ODM_CMNINFO_RSSI_MIN,
-+ ODM_CMNINFO_RSSI_MIN_BY_PATH,
-+ ODM_CMNINFO_DBG_COMP,
-+ ODM_CMNINFO_RA_THRESHOLD_HIGH, /*to be removed*/
-+ ODM_CMNINFO_RA_THRESHOLD_LOW, /*to be removed*/
-+ ODM_CMNINFO_RF_ANTENNA_TYPE,
-+ ODM_CMNINFO_WITH_EXT_ANTENNA_SWITCH,
-+ ODM_CMNINFO_BE_FIX_TX_ANT,
-+ ODM_CMNINFO_BT_ENABLED,
-+ ODM_CMNINFO_BT_HS_CONNECT_PROCESS,
-+ ODM_CMNINFO_BT_HS_RSSI,
-+ ODM_CMNINFO_BT_OPERATION,
-+ ODM_CMNINFO_BT_LIMITED_DIG,
-+ ODM_CMNINFO_AP_TOTAL_NUM,
-+ ODM_CMNINFO_POWER_TRAINING,
-+ ODM_CMNINFO_DFS_REGION_DOMAIN,
-+ ODM_CMNINFO_BT_CONTINUOUS_TURN,
-+ /*@------------CALL BY VALUE-------------*/
-+
-+ /*@Dynamic ptr array hook itms.*/
-+ ODM_CMNINFO_STA_STATUS,
-+ ODM_CMNINFO_MAX,
-+
-+};
-+
-+enum phydm_rfe_bb_source_sel {
-+ PAPE_2G = 0,
-+ PAPE_5G = 1,
-+ LNA0N_2G = 2,
-+ LNAON_5G = 3,
-+ TRSW = 4,
-+ TRSW_B = 5,
-+ GNT_BT = 6,
-+ ZERO = 7,
-+ ANTSEL_0 = 8,
-+ ANTSEL_1 = 9,
-+ ANTSEL_2 = 0xa,
-+ ANTSEL_3 = 0xb,
-+ ANTSEL_4 = 0xc,
-+ ANTSEL_5 = 0xd,
-+ ANTSEL_6 = 0xe,
-+ ANTSEL_7 = 0xf
-+};
-+
-+enum phydm_info_query {
-+ PHYDM_INFO_FA_OFDM,
-+ PHYDM_INFO_FA_CCK,
-+ PHYDM_INFO_FA_TOTAL,
-+ PHYDM_INFO_CCA_OFDM,
-+ PHYDM_INFO_CCA_CCK,
-+ PHYDM_INFO_CCA_ALL,
-+ PHYDM_INFO_CRC32_OK_VHT,
-+ PHYDM_INFO_CRC32_OK_HT,
-+ PHYDM_INFO_CRC32_OK_LEGACY,
-+ PHYDM_INFO_CRC32_OK_CCK,
-+ PHYDM_INFO_CRC32_ERROR_VHT,
-+ PHYDM_INFO_CRC32_ERROR_HT,
-+ PHYDM_INFO_CRC32_ERROR_LEGACY,
-+ PHYDM_INFO_CRC32_ERROR_CCK,
-+ PHYDM_INFO_EDCCA_FLAG,
-+ PHYDM_INFO_OFDM_ENABLE,
-+ PHYDM_INFO_CCK_ENABLE,
-+ PHYDM_INFO_CRC32_OK_HT_AGG,
-+ PHYDM_INFO_CRC32_ERROR_HT_AGG,
-+ PHYDM_INFO_DBG_PORT_0,
-+ PHYDM_INFO_CURR_IGI,
-+ PHYDM_INFO_RSSI_MIN,
-+ PHYDM_INFO_RSSI_MAX,
-+ PHYDM_INFO_CLM_RATIO,
-+ PHYDM_INFO_NHM_RATIO,
-+};
-+
-+enum phydm_api {
-+ PHYDM_API_NBI = 1,
-+ PHYDM_API_CSI_MASK = 2,
-+};
-+
-+enum phydm_func_idx { /*@F_XXX = PHYDM XXX function*/
-+
-+ F00_DIG = 0,
-+ F01_RA_MASK = 1,
-+ F02_DYN_TXPWR = 2,
-+ F03_FA_CNT = 3,
-+ F04_RSSI_MNTR = 4,
-+ F05_CCK_PD = 5,
-+ F06_ANT_DIV = 6,
-+ F07_SMT_ANT = 7,
-+ F08_PWR_TRAIN = 8,
-+ F09_RA = 9,
-+ F10_PATH_DIV = 10,
-+ F11_DFS = 11,
-+ F12_DYN_ARFR = 12,
-+ F13_ADPTVTY = 13,
-+ F14_CFO_TRK = 14,
-+ F15_ENV_MNTR = 15,
-+ F16_PRI_CCA = 16,
-+ F17_ADPTV_SOML = 17,
-+ F18_LNA_SAT_CHK = 18,
-+};
-+
-+/*@=[PHYDM supportability]==========================================*/
-+enum odm_ability {
-+ ODM_BB_DIG = BIT(F00_DIG),
-+ ODM_BB_RA_MASK = BIT(F01_RA_MASK),
-+ ODM_BB_DYNAMIC_TXPWR = BIT(F02_DYN_TXPWR),
-+ ODM_BB_FA_CNT = BIT(F03_FA_CNT),
-+ ODM_BB_RSSI_MONITOR = BIT(F04_RSSI_MNTR),
-+ ODM_BB_CCK_PD = BIT(F05_CCK_PD),
-+ ODM_BB_ANT_DIV = BIT(F06_ANT_DIV),
-+ ODM_BB_SMT_ANT = BIT(F07_SMT_ANT),
-+ ODM_BB_PWR_TRAIN = BIT(F08_PWR_TRAIN),
-+ ODM_BB_RATE_ADAPTIVE = BIT(F09_RA),
-+ ODM_BB_PATH_DIV = BIT(F10_PATH_DIV),
-+ ODM_BB_DFS = BIT(F11_DFS),
-+ ODM_BB_DYNAMIC_ARFR = BIT(F12_DYN_ARFR),
-+ ODM_BB_ADAPTIVITY = BIT(F13_ADPTVTY),
-+ ODM_BB_CFO_TRACKING = BIT(F14_CFO_TRK),
-+ ODM_BB_ENV_MONITOR = BIT(F15_ENV_MNTR),
-+ ODM_BB_PRIMARY_CCA = BIT(F16_PRI_CCA),
-+ ODM_BB_ADAPTIVE_SOML = BIT(F17_ADPTV_SOML),
-+ ODM_BB_LNA_SAT_CHK = BIT(F18_LNA_SAT_CHK),
-+};
-+
-+/*@=[PHYDM Debug Component]=====================================*/
-+enum phydm_dbg_comp {
-+ /*@BB Driver Functions*/
-+ DBG_DIG = BIT(F00_DIG),
-+ DBG_RA_MASK = BIT(F01_RA_MASK),
-+ DBG_DYN_TXPWR = BIT(F02_DYN_TXPWR),
-+ DBG_FA_CNT = BIT(F03_FA_CNT),
-+ DBG_RSSI_MNTR = BIT(F04_RSSI_MNTR),
-+ DBG_CCKPD = BIT(F05_CCK_PD),
-+ DBG_ANT_DIV = BIT(F06_ANT_DIV),
-+ DBG_SMT_ANT = BIT(F07_SMT_ANT),
-+ DBG_PWR_TRAIN = BIT(F08_PWR_TRAIN),
-+ DBG_RA = BIT(F09_RA),
-+ DBG_PATH_DIV = BIT(F10_PATH_DIV),
-+ DBG_DFS = BIT(F11_DFS),
-+ DBG_DYN_ARFR = BIT(F12_DYN_ARFR),
-+ DBG_ADPTVTY = BIT(F13_ADPTVTY),
-+ DBG_CFO_TRK = BIT(F14_CFO_TRK),
-+ DBG_ENV_MNTR = BIT(F15_ENV_MNTR),
-+ DBG_PRI_CCA = BIT(F16_PRI_CCA),
-+ DBG_ADPTV_SOML = BIT(F17_ADPTV_SOML),
-+ DBG_LNA_SAT_CHK = BIT(F18_LNA_SAT_CHK),
-+ /*BIT(19)*/
-+ /*Neet to re-arrange*/
-+ DBG_PHY_STATUS = BIT(20),
-+ DBG_TMP = BIT(21),
-+ DBG_FW_TRACE = BIT(22),
-+ DBG_TXBF = BIT(23),
-+ DBG_COMMON_FLOW = BIT(24),
-+ DBG_COMP_MCC = BIT(25),
-+ /*BIT(26)*/
-+ DBG_DM_SUMMARY = BIT(27),
-+ ODM_PHY_CONFIG = BIT(28),
-+ ODM_COMP_INIT = BIT(29),
-+ DBG_CMN = BIT(30),/*@common*/
-+ ODM_COMP_API = BIT(31)
-+};
-+
-+/*@=========================================================*/
-+
-+/*@ODM_CMNINFO_ONE_PATH_CCA*/
-+enum odm_cca_path {
-+ ODM_CCA_2R = 0,
-+ ODM_CCA_1R_A = 1,
-+ ODM_CCA_1R_B = 2,
-+};
-+
-+enum phy_reg_pg_type {
-+ PHY_REG_PG_RELATIVE_VALUE = 0,
-+ PHY_REG_PG_EXACT_VALUE = 1
-+};
-+
-+enum phydm_offload_ability {
-+ PHYDM_PHY_PARAM_OFFLOAD = BIT(0),
-+ PHYDM_RF_IQK_OFFLOAD = BIT(1),
-+};
-+
-+struct phydm_pause_lv {
-+ s8 lv_dig;
-+ s8 lv_cckpd;
-+ s8 lv_antdiv;
-+ s8 lv_adapt;
-+ s8 lv_adsl;
-+};
-+
-+struct phydm_func_poiner {
-+ void (*pause_phydm_handler)(void *dm_void, u32 *val_buf, u8 val_len);
-+};
-+
-+struct pkt_process_info {
-+ u8 phystatus_smp_mode_en; /*@send phystatus every sampling time*/
-+ u8 pre_ppdu_cnt;
-+ u8 lna_idx;
-+ u8 vga_idx;
-+};
-+
-+#ifdef ODM_CONFIG_BT_COEXIST
-+struct phydm_bt_info {
-+ boolean is_bt_enabled; /*@BT is enabled*/
-+ boolean is_bt_connect_process; /*@BT HS is under connection progress.*/
-+ u8 bt_hs_rssi; /*@BT HS mode wifi rssi value.*/
-+ boolean is_bt_hs_operation; /*@BT HS mode is under progress*/
-+ boolean is_bt_limited_dig; /*@BT is busy.*/
-+};
-+#endif
-+
-+struct phydm_iot_center {
-+ boolean is_linked_cmw500;
-+ u8 win_patch_id; /*@Customer ID*/
-+ u32 phydm_patch_id;
-+
-+};
-+
-+#if (RTL8822B_SUPPORT == 1)
-+struct drp_rtl8822b_struct {
-+ enum bb_path path_judge;
-+ u16 path_a_cck_fa;
-+ u16 path_b_cck_fa;
-+};
-+#endif
-+
-+#ifdef CONFIG_MCC_DM
-+#define MCC_DM_REG_NUM 32
-+struct _phydm_mcc_dm_ {
-+ u8 mcc_pre_status;
-+ u8 mcc_reg_id[MCC_DM_REG_NUM];
-+ u16 mcc_dm_reg[MCC_DM_REG_NUM];
-+ u8 mcc_dm_val[MCC_DM_REG_NUM][2];
-+ /*mcc DIG*/
-+ u8 mcc_rssi[2];
-+ /*u8 mcc_igi[2];*/
-+
-+ /* need to be config by driver*/
-+ u8 mcc_status;
-+ u8 sta_macid[2][NUM_STA];
-+ u16 mcc_rf_channel[2];
-+
-+};
-+#endif
-+
-+
-+#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
-+ #if (RT_PLATFORM != PLATFORM_LINUX)
-+ typedef
-+ #endif
-+
-+struct dm_struct {
-+#else/*for AP, CE Team*/
-+struct dm_struct {
-+#endif
-+ /*@Add for different team use temporarily*/
-+ void *adapter; /*@For CE/NIC team*/
-+ struct rtl8192cd_priv *priv; /*@For AP team*/
-+ boolean odm_ready;
-+ enum phy_reg_pg_type phy_reg_pg_value_type;
-+ u8 phy_reg_pg_version;
-+ u64 support_ability; /*@PHYDM function Supportability*/
-+ u64 pause_ability; /*@PHYDM function pause Supportability*/
-+ u64 debug_components;
-+ u8 cmn_dbg_msg_period;
-+ u8 cmn_dbg_msg_cnt;
-+ u32 fw_debug_components;
-+ u32 num_qry_phy_status_all; /*@CCK + OFDM*/
-+ u32 last_num_qry_phy_status_all;
-+ u32 rx_pwdb_ave;
-+ boolean is_init_hw_info_by_rfe;
-+
-+ /*@------ ODM HANDLE, DRIVER NEEDS NOT TO HOOK------*/
-+ boolean is_cck_high_power;
-+ u8 rf_path_rx_enable;
-+ /*@------ ODM HANDLE, DRIVER NEEDS NOT TO HOOK------*/
-+
-+ /* @COMMON INFORMATION */
-+
-+ /*@Init value*/
-+ /*@-----------HOOK BEFORE REG INIT-----------*/
-+
-+ u8 support_platform; /*@PHYDM Platform info WIN/AP/CE = 1/2/3 */
-+ u8 normal_rx_path;
-+ boolean brxagcswitch; /* @for rx AGC table switch in Microsoft case */
-+ u8 support_interface; /*@PHYDM PCIE/USB/SDIO = 1/2/3*/
-+ u32 support_ic_type; /*@PHYDM supported IC*/
-+ u8 ic_ip_series; /*N/AC/JGR3*/
-+ enum phydm_phy_sts_type ic_phy_sts_type; /*@Type1/type2/type3*/
-+ u8 cut_version; /*@cut version TestChip/A-cut/B-cut... = 0/1/2/3/...*/
-+ u8 fab_version; /*@Fab version TSMC/UMC = 0/1*/
-+ u8 fw_version;
-+ u8 fw_sub_version;
-+ u8 rf_type; /*@RF type 4T4R/3T3R/2T2R/1T2R/1T1R/...*/
-+ u8 rfe_type;
-+ u8 board_type;
-+ u8 package_type;
-+ u16 type_glna;
-+ u16 type_gpa;
-+ u16 type_alna;
-+ u16 type_apa;
-+ u8 ext_lna; /*@with 2G external LNA NO/Yes = 0/1*/
-+ u8 ext_lna_5g; /*@with 5G external LNA NO/Yes = 0/1*/
-+ u8 ext_pa; /*@with 2G external PNA NO/Yes = 0/1*/
-+ u8 ext_pa_5g; /*@with 5G external PNA NO/Yes = 0/1*/
-+ u8 efuse0x3d7; /*@with Efuse number*/
-+ u8 efuse0x3d8;
-+ u8 ext_trsw; /*@with external TRSW NO/Yes = 0/1*/
-+ u8 ext_lna_gain; /*@gain of external lna*/
-+ boolean is_in_hct_test;
-+ u8 wifi_test;
-+ boolean is_dual_mac_smart_concurrent;
-+ u32 bk_support_ability; /*SD4 only*/
-+ u8 with_extenal_ant_switch;
-+ /*@cck agc relative*/
-+ boolean cck_new_agc;
-+ s8 cck_lna_gain_table[8];
-+ /*@-------------------------------------*/
-+ u32 phydm_sys_up_time;
-+ u8 num_rf_path; /*@ex: 8821C=1, 8192E=2, 8814B=4*/
-+ u32 soft_ap_special_setting;
-+ s8 s8_dummy;
-+ u8 u8_dummy;
-+ u16 u16_dummy;
-+ u32 u32_dummy;
-+ u8 rfe_hwsetting_band;
-+ u8 p_advance_ota;
-+ boolean hp_hw_id;
-+ boolean BOOLEAN_temp;
-+ boolean is_dfs_band;
-+ u8 is_rx_blocking_en;
-+ u16 fw_offload_ability;
-+/*@-----------HOOK BEFORE REG INIT-----------*/
-+/*@===========================================================*/
-+/*@====[ CALL BY Reference ]=========================================*/
-+/*@===========================================================*/
-+
-+ u64 *num_tx_bytes_unicast; /*@TX Unicast byte cnt*/
-+ u64 *num_rx_bytes_unicast; /*@RX Unicast byte cnt*/
-+ u8 *band_type; /*@2.4G/5G = 0/1*/
-+ u8 *sec_ch_offset; /*@Secondary channel offset don't_care/below/above = 0/1/2*/
-+ u8 *security; /*@security mode Open/WEP/AES/TKIP = 0/1/2/3*/
-+ u8 *band_width; /*@20M/40M/80M = 0/1/2*/
-+ u8 *channel; /*@central CH number*/
-+ boolean *is_scan_in_process;
-+ boolean *is_power_saving;
-+ boolean *is_tdma;
-+ u8 *one_path_cca; /*@CCA path 2-path/path-A/path-B = 0/1/2; using enum odm_cca_path.*/
-+ u8 *antenna_test;
-+ boolean *is_net_closed;
-+ boolean *is_fcs_mode_enable;
-+ /*@--------- For 8723B IQK-------------------------------------*/
-+ boolean *is_1_antenna;
-+ u8 *rf_default_path; /* @0:S1, 1:S0 */
-+ /*@-----------------------------------------------------------*/
-+
-+ u16 *forced_data_rate;
-+ u8 *enable_antdiv;
-+ u8 *enable_pathdiv;
-+ u8 *en_adap_soml;
-+ u8 *enable_adaptivity;
-+ u8 *hub_usb_mode; /*@1:USB2.0, 2:USB3.0*/
-+ boolean *is_fw_dw_rsvd_page_in_progress;
-+ u32 *current_tx_tp;
-+ u32 *current_rx_tp;
-+ u8 *sounding_seq;
-+ u32 *soft_ap_mode;
-+ u8 *mp_mode;
-+ u32 *interrupt_mask;
-+ u8 *bb_op_mode;
-+/*@===========================================================*/
-+/*@====[ CALL BY VALUE ]===========================================*/
-+/*@===========================================================*/
-+
-+ u8 disable_phydm_watchdog;
-+ boolean is_link_in_process;
-+ boolean is_wifi_direct;
-+ boolean is_wifi_display;
-+ boolean is_linked;
-+ boolean bsta_state;
-+ u8 rssi_min;
-+ u8 rssi_min_macid;
-+ u8 pre_rssi_min;
-+ u8 rssi_max;
-+ u8 rssi_max_macid;
-+ u8 rssi_min_by_path;
-+ boolean is_one_entry_only;
-+ u32 one_entry_macid;
-+ u32 one_entry_tp;
-+ u32 pre_one_entry_tp;
-+ u8 pre_number_linked_client;
-+ u8 number_linked_client;
-+ u8 pre_number_active_client;
-+ u8 number_active_client;
-+ boolean is_disable_phy_api;
-+ u8 rssi_a;
-+ u8 rssi_b;
-+ u8 rssi_c;
-+ u8 rssi_d;
-+ s8 rxsc_80;
-+ s8 rxsc_40;
-+ s8 rxsc_20;
-+ s8 rxsc_l;
-+ u64 rssi_trsw;
-+ u64 rssi_trsw_h;
-+ u64 rssi_trsw_l;
-+ u64 rssi_trsw_iso;
-+ u8 tx_ant_status;
-+ u8 rx_ant_status;
-+ u8 cck_lna_idx;
-+ u8 cck_vga_idx;
-+ u8 curr_station_id;
-+ u8 ofdm_agc_idx[4];
-+ u8 rx_rate;
-+ u8 rate_ss;
-+ u8 tx_rate;
-+ u8 linked_interval;
-+ u8 pre_channel;
-+ u32 txagc_offset_value_a;
-+ boolean is_txagc_offset_positive_a;
-+ u32 txagc_offset_value_b;
-+ boolean is_txagc_offset_positive_b;
-+ u8 ap_total_num;
-+ /*@[traffic]*/
-+ u8 traffic_load;
-+ u8 pre_traffic_load;
-+ u32 tx_tp; /*@Mbps*/
-+ u32 rx_tp; /*@Mbps*/
-+ u32 total_tp; /*@Mbps*/
-+ u8 txrx_state_all; /*@0:tx, 1:rx, 2:bi-dir*/
-+ u64 cur_tx_ok_cnt;
-+ u64 cur_rx_ok_cnt;
-+ u64 last_tx_ok_cnt;
-+ u64 last_rx_ok_cnt;
-+ u16 consecutive_idlel_time; /*@unit: second*/
-+ /*@---------------------------*/
-+ boolean is_bb_swing_offset_positive_a;
-+ boolean is_bb_swing_offset_positive_b;
-+
-+ /*@[DIG]*/
-+ boolean MPDIG_2G; /*off MPDIG*/
-+ u8 times_2g; /*@for MP DIG*/
-+ u8 force_igi; /*@for debug*/
-+
-+ /*@[TDMA-DIG]*/
-+ u8 tdma_dig_timer_ms;
-+ u8 tdma_dig_state_number;
-+ u8 tdma_dig_low_upper_bond;
-+ u8 force_tdma_low_igi;
-+ u8 force_tdma_high_igi;
-+ u8 fix_expire_to_zero;
-+ boolean original_dig_restore;
-+ /*@---------------------------*/
-+
-+ /*@[AntDiv]*/
-+ u8 ant_div_type;
-+ u8 antdiv_rssi;
-+ u8 fat_comb_a;
-+ u8 fat_comb_b;
-+ u8 antdiv_intvl;
-+ u8 ant_type;
-+ u8 ant_type2;
-+ u8 pre_ant_type;
-+ u8 pre_ant_type2;
-+ u8 antdiv_period;
-+ u8 evm_antdiv_period;
-+ u8 antdiv_select;
-+ u8 antdiv_train_num; /*@training time for each antenna in EVM method*/
-+ u8 stop_antdiv_rssi_th;
-+ u16 stop_antdiv_tp_diff_th;
-+ u16 stop_antdiv_tp_th;
-+ u8 antdiv_tp_period;
-+ u16 tp_active_th;
-+ u8 tp_active_occur;
-+ u8 path_select;
-+ u8 antdiv_evm_en;
-+ u8 bdc_holdstate;
-+ u8 antdiv_counter;
-+ /*@---------------------------*/
-+
-+ u8 ndpa_period;
-+ boolean h2c_rarpt_connect;
-+ boolean cck_agc_report_type; /*@1:4bit LNA, 0:3bit LNA */
-+ u8 print_agc;
-+ u8 la_mode;
-+ /*@---8821C Antenna and RF Set BTG/WLG/WLA Select---------------*/
-+ u8 current_rf_set_8821c;
-+ u8 default_rf_set_8821c;
-+ u8 current_ant_num_8821c;
-+ u8 default_ant_num_8821c;
-+ u8 rfe_type_expand;
-+ /*@-----------------------------------------------------------*/
-+ /*@---For Adaptivtiy---------------------------------------------*/
-+ s8 TH_L2H_default;
-+ s8 th_edcca_hl_diff_default;
-+ s8 th_l2h_ini;
-+ s8 th_edcca_hl_diff;
-+ boolean carrier_sense_enable;
-+ /*@-----------------------------------------------------------*/
-+
-+ u8 pre_dbg_priority;
-+ u8 nbi_set_result;
-+ u8 c2h_cmd_start;
-+ u8 fw_debug_trace[60];
-+ u8 pre_c2h_seq;
-+ boolean fw_buff_is_enpty;
-+ u32 data_frame_num;
-+
-+ /*@--- for noise detection ---------------------------------------*/
-+ boolean is_noisy_state;
-+ boolean noisy_decision; /*@b_noisy*/
-+ boolean pre_b_noisy;
-+ u32 noisy_decision_smooth;
-+ /*@-----------------------------------------------------------*/
-+
-+ /*@--- for MCC ant weighting ------------------------------------*/
-+ boolean is_stop_dym_ant_weighting;
-+ /*@-----------------------------------------------------------*/
-+
-+ boolean is_disable_dym_ecs;
-+ boolean is_disable_dym_ant_weighting;
-+ struct cmn_sta_info *phydm_sta_info[ODM_ASSOCIATE_ENTRY_NUM];
-+ u8 phydm_macid_table[ODM_ASSOCIATE_ENTRY_NUM];/*@sta_idx = phydm_macid_table[HW_macid]*/
-+
-+#if (RATE_ADAPTIVE_SUPPORT == 1)
-+ u16 currmin_rpt_time;
-+ struct _phydm_txstatistic_ hw_stats;
-+ struct _odm_ra_info_ ra_info[ODM_ASSOCIATE_ENTRY_NUM];
-+/*Use mac_id as array index. STA mac_id=0*/
-+/*VWiFi Client mac_id={1, ODM_ASSOCIATE_ENTRY_NUM-1} //YJ,add,120119*/
-+#endif
-+ /*@2012/02/14 MH Add to share 88E ra with other SW team*/
-+ /*We need to colelct all support abilit to a proper area.*/
-+ boolean ra_support88e;
-+ boolean *is_driver_stopped;
-+ boolean *is_driver_is_going_to_pnp_set_power_sleep;
-+ boolean *pinit_adpt_in_progress;
-+ boolean is_user_assign_level;
-+ u8 RSSI_BT; /*@come from BT*/
-+
-+ /*@---PSD Relative ---------------------------------------------*/
-+ boolean is_psd_in_process;
-+ boolean is_psd_active;
-+ /*@-----------------------------------------------------------*/
-+
-+ boolean bsomlenabled; /* @D-SoML control */
-+ boolean bhtstfdisabled; /* @dynamic HTSTF gain control*/
-+ u32 n_iqk_cnt;
-+ u32 n_iqk_ok_cnt;
-+ u32 n_iqk_fail_cnt;
-+
-+#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
-+ boolean config_bbrf;
-+#endif
-+ boolean is_disable_power_training;
-+ boolean is_bt_continuous_turn;
-+ u8 enhance_pwr_th[3];
-+ u8 set_pwr_th[3];
-+ /*@----------Dyn Tx Pwr ---------------------------------------*/
-+#ifdef BB_RAM_SUPPORT
-+ struct phydm_bb_ram_ctrl p_bb_ram_ctrl;
-+#endif
-+ u8 dynamic_tx_high_power_lvl;
-+ void (*fill_desc_dyntxpwr)(void *dm, u8 *desc, u8 dyn_tx_power);
-+ u8 last_dtp_lvl;
-+ u8 min_power_index;
-+ u32 tx_agc_ofdm_18_6;
-+ /*-------------------------------------------------------------*/
-+ u8 rx_pkt_type;
-+
-+#ifdef CONFIG_PHYDM_DFS_MASTER
-+ u8 dfs_region_domain;
-+ u8 *dfs_master_enabled;
-+ /*@---phydm_radar_detect_with_dbg_parm start --------------------*/
-+ u8 radar_detect_dbg_parm_en;
-+ u32 radar_detect_reg_918;
-+ u32 radar_detect_reg_91c;
-+ u32 radar_detect_reg_920;
-+ u32 radar_detect_reg_924;
-+ u32 radar_detect_reg_f54;
-+ u32 radar_detect_reg_f58;
-+ u32 radar_detect_reg_f5c;
-+ u32 radar_detect_reg_f70;
-+ u32 radar_detect_reg_f74;
-+/*@-----------------------------------------------------------*/
-+#endif
-+
-+/*@=== PHYDM Timer ========================================== (start)*/
-+
-+ struct phydm_timer_list mpt_dig_timer;
-+ struct phydm_timer_list fast_ant_training_timer;
-+#ifdef ODM_EVM_ENHANCE_ANTDIV
-+ struct phydm_timer_list evm_fast_ant_training_timer;
-+#endif
-+#ifdef PHYDM_TDMA_DIG_SUPPORT
-+ struct phydm_timer_list tdma_dig_timer;
-+#endif
-+ struct phydm_timer_list sbdcnt_timer;
-+
-+/*@=== PHYDM Workitem ======================================= (start)*/
-+
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+#if USE_WORKITEM
-+ RT_WORK_ITEM fast_ant_training_workitem;
-+ RT_WORK_ITEM ra_rpt_workitem;
-+ RT_WORK_ITEM sbdcnt_workitem;
-+ RT_WORK_ITEM phydm_evm_antdiv_workitem;
-+#endif
-+#endif
-+
-+/*@=== PHYDM Structure ======================================== (start)*/
-+ struct phydm_func_poiner phydm_func_handler;
-+ struct phydm_iot_center iot_table;
-+
-+#ifdef ODM_CONFIG_BT_COEXIST
-+ struct phydm_bt_info bt_info_table;
-+#endif
-+
-+ struct pkt_process_info pkt_proc_struct;
-+ struct phydm_adaptivity_struct adaptivity;
-+ struct _DFS_STATISTICS dfs;
-+ struct odm_noise_monitor noise_level;
-+ struct odm_phy_dbg_info phy_dbg_info;
-+
-+#ifdef CONFIG_ADAPTIVE_SOML
-+ struct adaptive_soml dm_soml_table;
-+#endif
-+
-+#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))
-+ #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
-+ struct _BF_DIV_COEX_ dm_bdc_table;
-+ #endif
-+
-+ #if (defined(CONFIG_HL_SMART_ANTENNA))
-+ struct smt_ant_honbo dm_sat_table;
-+ #endif
-+#endif
-+
-+#if (defined(CONFIG_SMART_ANTENNA))
-+ struct smt_ant smtant_table;
-+#endif
-+
-+ struct _hal_rf_ rf_table; /*@for HALRF function*/
-+ struct dm_rf_calibration_struct rf_calibrate_info;
-+ struct dm_iqk_info IQK_info;
-+ struct dm_dpk_info dpk_info;
-+
-+#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
-+ struct phydm_fat_struct dm_fat_table;
-+ struct sw_antenna_switch dm_swat_table;
-+#endif
-+ struct phydm_dig_struct dm_dig_table;
-+#ifdef PHYDM_LNA_SAT_CHK_SUPPORT
-+ struct phydm_lna_sat_t dm_lna_sat_info;
-+#endif
-+
-+#ifdef CONFIG_MCC_DM
-+ struct _phydm_mcc_dm_ mcc_dm;
-+#endif
-+
-+#ifdef PHYDM_SUPPORT_CCKPD
-+ struct phydm_cckpd_struct dm_cckpd_table;
-+#endif
-+
-+#ifdef PHYDM_PRIMARY_CCA
-+ struct phydm_pricca_struct dm_pri_cca;
-+#endif
-+
-+ struct ra_table dm_ra_table;
-+ struct phydm_fa_struct false_alm_cnt;
-+#ifdef PHYDM_TDMA_DIG_SUPPORT
-+ struct phydm_fa_acc_struct false_alm_cnt_acc;
-+#ifdef IS_USE_NEW_TDMA
-+ struct phydm_fa_acc_struct false_alm_cnt_acc_low;
-+#endif
-+#endif
-+ struct phydm_cfo_track_struct dm_cfo_track;
-+ struct ccx_info dm_ccx_info;
-+
-+ struct odm_power_trim_data power_trim_data;
-+#if (RTL8822B_SUPPORT == 1)
-+ struct drp_rtl8822b_struct phydm_rtl8822b;
-+#endif
-+
-+#ifdef CONFIG_PSD_TOOL
-+ struct psd_info dm_psd_table;
-+#endif
-+
-+#if (PHYDM_LA_MODE_SUPPORT == 1)
-+ struct rt_adcsmp adcsmp;
-+#endif
-+
-+#if (defined(CONFIG_PATH_DIVERSITY))
-+ struct _ODM_PATH_DIVERSITY_ dm_path_div;
-+#endif
-+
-+#if (defined(CONFIG_ANT_DETECTION))
-+ struct _ANT_DETECTED_INFO ant_detected_info;
-+#endif
-+
-+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
-+#ifdef PHYDM_BEAMFORMING_SUPPORT
-+ struct _RT_BEAMFORMING_INFO beamforming_info;
-+#endif
-+#endif
-+#ifdef PHYDM_AUTO_DEGBUG
-+ struct phydm_auto_dbg_struct auto_dbg_table;
-+#endif
-+
-+ struct phydm_pause_lv pause_lv_table;
-+ struct phydm_api_stuc api_table;
-+#ifdef PHYDM_POWER_TRAINING_SUPPORT
-+ struct phydm_pow_train_stuc pow_train_table;
-+#endif
-+
-+#ifdef PHYDM_PMAC_TX_SETTING_SUPPORT
-+ struct phydm_pmac_tx dm_pmac_tx_table;
-+#endif
-+
-+#ifdef PHYDM_MP_SUPPORT
-+ struct phydm_mp dm_mp_table;
-+#endif
-+/*@==========================================================*/
-+
-+#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
-+
-+#if (RT_PLATFORM != PLATFORM_LINUX)
-+} dm_struct; /*@DM_Dynamic_Mechanism_Structure*/
-+#else
-+};
-+#endif
-+
-+#else /*@for AP,CE Team*/
-+};
-+#endif
-+
-+enum phydm_adv_ota {
-+ PHYDM_PATHB_1RCCA = BIT(0),
-+ PHYDM_HP_OTA_SETTING_A = BIT(1),
-+ PHYDM_HP_OTA_SETTING_B = BIT(2),
-+ PHYDM_ASUS_OTA_SETTING = BIT(3),
-+ PHYDM_ASUS_OTA_SETTING_CCK_PATH = BIT(4),
-+ PHYDM_HP_OTA_SETTING_CCK_PATH = BIT(5),
-+ PHYDM_LENOVO_OTA_SETTING_NBI_CSI = BIT(6),
-+
-+};
-+
-+enum phydm_bb_op_mode {
-+ PHYDM_PERFORMANCE_MODE = 0, /*Service one device*/
-+ PHYDM_BALANCE_MODE = 1, /*@Service more than one device*/
-+};
-+
-+enum phydm_structure_type {
-+ PHYDM_FALSEALMCNT,
-+ PHYDM_CFOTRACK,
-+ PHYDM_ADAPTIVITY,
-+ PHYDM_DFS,
-+ PHYDM_ROMINFO,
-+
-+};
-+
-+enum odm_bb_config_type {
-+ CONFIG_BB_PHY_REG,
-+ CONFIG_BB_AGC_TAB,
-+ CONFIG_BB_AGC_TAB_2G,
-+ CONFIG_BB_AGC_TAB_5G,
-+ CONFIG_BB_PHY_REG_PG,
-+ CONFIG_BB_PHY_REG_MP,
-+ CONFIG_BB_AGC_TAB_DIFF,
-+ CONFIG_BB_RF_CAL_INIT,
-+};
-+
-+enum odm_rf_config_type {
-+ CONFIG_RF_RADIO,
-+ CONFIG_RF_TXPWR_LMT,
-+ CONFIG_RF_SYN_RADIO,
-+};
-+
-+enum odm_fw_config_type {
-+ CONFIG_FW_NIC,
-+ CONFIG_FW_NIC_2,
-+ CONFIG_FW_AP,
-+ CONFIG_FW_AP_2,
-+ CONFIG_FW_MP,
-+ CONFIG_FW_WOWLAN,
-+ CONFIG_FW_WOWLAN_2,
-+ CONFIG_FW_AP_WOWLAN,
-+ CONFIG_FW_BT,
-+};
-+
-+/*status code*/
-+#if (DM_ODM_SUPPORT_TYPE != ODM_WIN)
-+enum rt_status {
-+ RT_STATUS_SUCCESS,
-+ RT_STATUS_FAILURE,
-+ RT_STATUS_PENDING,
-+ RT_STATUS_RESOURCE,
-+ RT_STATUS_INVALID_CONTEXT,
-+ RT_STATUS_INVALID_PARAMETER,
-+ RT_STATUS_NOT_SUPPORT,
-+ RT_STATUS_OS_API_FAILED,
-+};
-+#endif /*@end of enum rt_status definition*/
-+
-+void
-+phydm_watchdog_lps(struct dm_struct *dm);
-+
-+void
-+phydm_watchdog_lps_32k(struct dm_struct *dm);
-+
-+void
-+phydm_txcurrentcalibration(struct dm_struct *dm);
-+
-+void
-+phydm_dm_early_init(struct dm_struct *dm);
-+
-+void
-+odm_dm_init(struct dm_struct *dm);
-+
-+void
-+odm_dm_reset(struct dm_struct *dm);
-+
-+void
-+phydm_fwoffload_ability_init(struct dm_struct *dm,
-+ enum phydm_offload_ability offload_ability);
-+
-+void
-+phydm_fwoffload_ability_clear(struct dm_struct *dm,
-+ enum phydm_offload_ability offload_ability);
-+
-+void
-+phydm_supportability_en(void *dm_void, char input[][16], u32 *_used,
-+ char *output, u32 *_out_len);
-+
-+void
-+phydm_pause_dm_watchdog(void *dm_void, enum phydm_pause_type pause_type);
-+
-+void
-+phydm_watchdog(struct dm_struct *dm);
-+
-+void
-+phydm_watchdog_mp(struct dm_struct *dm);
-+
-+u8
-+phydm_pause_func(void *dm_void, enum phydm_func_idx pause_func,
-+ enum phydm_pause_type pause_type,
-+ enum phydm_pause_level pause_lv, u8 val_lehgth, u32 *val_buf);
-+
-+void
-+phydm_pause_func_console(void *dm_void, char input[][16], u32 *_used,
-+ char *output, u32 *_out_len);
-+
-+void
-+odm_cmn_info_init(struct dm_struct *dm, enum odm_cmninfo cmn_info, u64 value);
-+
-+void
-+odm_cmn_info_hook(struct dm_struct *dm, enum odm_cmninfo cmn_info, void *value);
-+
-+void
-+odm_cmn_info_update(struct dm_struct *dm, u32 cmn_info, u64 value);
-+
-+u32
-+phydm_cmn_info_query(struct dm_struct *dm, enum phydm_info_query info_type);
-+
-+void
-+odm_init_all_timers(struct dm_struct *dm);
-+
-+void
-+odm_cancel_all_timers(struct dm_struct *dm);
-+
-+void
-+odm_release_all_timers(struct dm_struct *dm);
-+
-+void *
-+phydm_get_structure(struct dm_struct *dm, u8 structure_type);
-+
-+void
-+phydm_dc_cancellation(struct dm_struct *dm);
-+
-+void
-+phydm_receiver_blocking(void *dm_void);
-+
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+void
-+odm_init_all_work_items(
-+ struct dm_struct *dm
-+);
-+void
-+odm_free_all_work_items(
-+ struct dm_struct *dm
-+);
-+#endif /*@#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)*/
-+
-+#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
-+void
-+odm_dtc(struct dm_struct *dm);
-+#endif
-+
-+#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
-+void
-+odm_init_all_threads(
-+ struct dm_struct *dm
-+);
-+
-+void
-+odm_stop_all_threads(
-+ struct dm_struct *dm
-+);
-+#endif
-+
-+#endif
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm.mk linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm.mk
-new file mode 100644
-index 000000000..a05df647d
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm.mk
-@@ -0,0 +1,226 @@
-+EXTRA_CFLAGS += -I$(src)/hal/phydm
-+
-+_PHYDM_FILES := hal/phydm/phydm_debug.o \
-+ hal/phydm/phydm_antdiv.o\
-+ hal/phydm/phydm_soml.o\
-+ hal/phydm/phydm_smt_ant.o\
-+ hal/phydm/phydm_antdect.o\
-+ hal/phydm/phydm_interface.o\
-+ hal/phydm/phydm_phystatus.o\
-+ hal/phydm/phydm_hwconfig.o\
-+ hal/phydm/phydm.o\
-+ hal/phydm/phydm_dig.o\
-+ hal/phydm/phydm_pathdiv.o\
-+ hal/phydm/phydm_rainfo.o\
-+ hal/phydm/phydm_dynamictxpower.o\
-+ hal/phydm/phydm_adaptivity.o\
-+ hal/phydm/phydm_cfotracking.o\
-+ hal/phydm/phydm_noisemonitor.o\
-+ hal/phydm/phydm_beamforming.o\
-+ hal/phydm/phydm_dfs.o\
-+ hal/phydm/txbf/halcomtxbf.o\
-+ hal/phydm/txbf/haltxbfinterface.o\
-+ hal/phydm/txbf/phydm_hal_txbf_api.o\
-+ hal/phydm/phydm_adc_sampling.o\
-+ hal/phydm/phydm_ccx.o\
-+ hal/phydm/phydm_psd.o\
-+ hal/phydm/phydm_primary_cca.o\
-+ hal/phydm/phydm_cck_pd.o\
-+ hal/phydm/phydm_rssi_monitor.o\
-+ hal/phydm/phydm_auto_dbg.o\
-+ hal/phydm/phydm_math_lib.o\
-+ hal/phydm/phydm_api.o\
-+ hal/phydm/phydm_pow_train.o\
-+ hal/phydm/phydm_lna_sat.o\
-+ hal/phydm/phydm_pmac_tx_setting.o\
-+ hal/phydm/phydm_mp.o\
-+ hal/phydm/halrf/halrf.o\
-+ hal/phydm/halrf/halrf_debug.o\
-+ hal/phydm/halrf/halphyrf_ce.o\
-+ hal/phydm/halrf/halrf_powertracking_ce.o\
-+ hal/phydm/halrf/halrf_powertracking.o\
-+ hal/phydm/halrf/halrf_kfree.o
-+
-+ifeq ($(CONFIG_RTL8188E), y)
-+RTL871X = rtl8188e
-+_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8188e_mac.o\
-+ hal/phydm/$(RTL871X)/halhwimg8188e_bb.o\
-+ hal/phydm/$(RTL871X)/halhwimg8188e_rf.o\
-+ hal/phydm/halrf/$(RTL871X)/halrf_8188e_ce.o\
-+ hal/phydm/$(RTL871X)/phydm_regconfig8188e.o\
-+ hal/phydm/$(RTL871X)/hal8188erateadaptive.o\
-+ hal/phydm/$(RTL871X)/phydm_rtl8188e.o
-+endif
-+
-+ifeq ($(CONFIG_RTL8192E), y)
-+RTL871X = rtl8192e
-+_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8192e_mac.o\
-+ hal/phydm/$(RTL871X)/halhwimg8192e_bb.o\
-+ hal/phydm/$(RTL871X)/halhwimg8192e_rf.o\
-+ hal/phydm/halrf/$(RTL871X)/halrf_8192e_ce.o\
-+ hal/phydm/$(RTL871X)/phydm_regconfig8192e.o\
-+ hal/phydm/$(RTL871X)/phydm_rtl8192e.o
-+endif
-+
-+
-+ifeq ($(CONFIG_RTL8812A), y)
-+RTL871X = rtl8812a
-+_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8812a_mac.o\
-+ hal/phydm/$(RTL871X)/halhwimg8812a_bb.o\
-+ hal/phydm/$(RTL871X)/halhwimg8812a_rf.o\
-+ hal/phydm/halrf/$(RTL871X)/halrf_8812a_ce.o\
-+ hal/phydm/$(RTL871X)/phydm_regconfig8812a.o\
-+ hal/phydm/$(RTL871X)/phydm_rtl8812a.o\
-+ hal/phydm/txbf/haltxbfjaguar.o
-+endif
-+
-+ifeq ($(CONFIG_RTL8821A), y)
-+RTL871X = rtl8821a
-+_PHYDM_FILES += hal/phydm/rtl8821a/halhwimg8821a_mac.o\
-+ hal/phydm/rtl8821a/halhwimg8821a_bb.o\
-+ hal/phydm/rtl8821a/halhwimg8821a_rf.o\
-+ hal/phydm/halrf/rtl8812a/halrf_8812a_ce.o\
-+ hal/phydm/halrf/rtl8821a/halrf_8821a_ce.o\
-+ hal/phydm/rtl8821a/phydm_regconfig8821a.o\
-+ hal/phydm/rtl8821a/phydm_rtl8821a.o\
-+ hal/phydm/halrf/rtl8821a/halrf_iqk_8821a_ce.o\
-+ hal/phydm/txbf/haltxbfjaguar.o
-+endif
-+
-+
-+ifeq ($(CONFIG_RTL8723B), y)
-+RTL871X = rtl8723b
-+_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8723b_bb.o\
-+ hal/phydm/$(RTL871X)/halhwimg8723b_mac.o\
-+ hal/phydm/$(RTL871X)/halhwimg8723b_rf.o\
-+ hal/phydm/$(RTL871X)/halhwimg8723b_mp.o\
-+ hal/phydm/$(RTL871X)/phydm_regconfig8723b.o\
-+ hal/phydm/halrf/$(RTL871X)/halrf_8723b_ce.o\
-+ hal/phydm/$(RTL871X)/phydm_rtl8723b.o
-+endif
-+
-+
-+ifeq ($(CONFIG_RTL8814A), y)
-+RTL871X = rtl8814a
-+_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8814a_bb.o\
-+ hal/phydm/$(RTL871X)/halhwimg8814a_mac.o\
-+ hal/phydm/$(RTL871X)/halhwimg8814a_rf.o\
-+ hal/phydm/halrf/$(RTL871X)/halrf_iqk_8814a.o\
-+ hal/phydm/$(RTL871X)/phydm_regconfig8814a.o\
-+ hal/phydm/halrf/$(RTL871X)/halrf_8814a_ce.o\
-+ hal/phydm/$(RTL871X)/phydm_rtl8814a.o\
-+ hal/phydm/txbf/haltxbf8814a.o
-+endif
-+
-+
-+ifeq ($(CONFIG_RTL8723C), y)
-+RTL871X = rtl8703b
-+_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8703b_bb.o\
-+ hal/phydm/$(RTL871X)/halhwimg8703b_mac.o\
-+ hal/phydm/$(RTL871X)/halhwimg8703b_rf.o\
-+ hal/phydm/$(RTL871X)/phydm_regconfig8703b.o\
-+ hal/phydm/$(RTL871X)/phydm_rtl8703b.o\
-+ hal/phydm/halrf/$(RTL871X)/halrf_8703b.o
-+endif
-+
-+ifeq ($(CONFIG_RTL8723D), y)
-+RTL871X = rtl8723d
-+_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8723d_bb.o\
-+ hal/phydm/$(RTL871X)/halhwimg8723d_mac.o\
-+ hal/phydm/$(RTL871X)/halhwimg8723d_rf.o\
-+ hal/phydm/$(RTL871X)/phydm_regconfig8723d.o\
-+ hal/phydm/$(RTL871X)/phydm_rtl8723d.o\
-+ hal/phydm/halrf/$(RTL871X)/halrf_8723d.o
-+endif
-+
-+
-+ifeq ($(CONFIG_RTL8710B), y)
-+RTL871X = rtl8710b
-+_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8710b_bb.o\
-+ hal/phydm/$(RTL871X)/halhwimg8710b_mac.o\
-+ hal/phydm/$(RTL871X)/halhwimg8710b_rf.o\
-+ hal/phydm/$(RTL871X)/phydm_regconfig8710b.o\
-+ hal/phydm/$(RTL871X)/phydm_rtl8710b.o\
-+ hal/phydm/halrf/$(RTL871X)/halrf_8710b.o
-+endif
-+
-+
-+ifeq ($(CONFIG_RTL8188F), y)
-+RTL871X = rtl8188f
-+_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8188f_bb.o\
-+ hal/phydm/$(RTL871X)/halhwimg8188f_mac.o\
-+ hal/phydm/$(RTL871X)/halhwimg8188f_rf.o\
-+ hal/phydm/$(RTL871X)/phydm_regconfig8188f.o\
-+ hal/phydm/halrf/$(RTL871X)/halrf_8188f.o \
-+ hal/phydm/$(RTL871X)/phydm_rtl8188f.o
-+endif
-+
-+ifeq ($(CONFIG_RTL8822B), y)
-+RTL871X = rtl8822b
-+_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8822b_bb.o \
-+ hal/phydm/$(RTL871X)/halhwimg8822b_mac.o \
-+ hal/phydm/$(RTL871X)/halhwimg8822b_rf.o \
-+ hal/phydm/halrf/$(RTL871X)/halrf_8822b.o \
-+ hal/phydm/$(RTL871X)/phydm_hal_api8822b.o \
-+ hal/phydm/halrf/$(RTL871X)/halrf_iqk_8822b.o \
-+ hal/phydm/halrf/$(RTL871X)/halrf_rfk_init_8822b.o \
-+ hal/phydm/$(RTL871X)/phydm_regconfig8822b.o \
-+ hal/phydm/$(RTL871X)/phydm_rtl8822b.o
-+
-+_PHYDM_FILES += hal/phydm/txbf/haltxbf8822b.o
-+endif
-+
-+
-+ifeq ($(CONFIG_RTL8821C), y)
-+RTL871X = rtl8821c
-+_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8821c_bb.o \
-+ hal/phydm/$(RTL871X)/halhwimg8821c_mac.o \
-+ hal/phydm/$(RTL871X)/halhwimg8821c_rf.o \
-+ hal/phydm/$(RTL871X)/phydm_hal_api8821c.o \
-+ hal/phydm/$(RTL871X)/phydm_regconfig8821c.o\
-+ hal/phydm/halrf/$(RTL871X)/halrf_8821c.o\
-+ hal/phydm/halrf/$(RTL871X)/halrf_iqk_8821c.o
-+endif
-+ifeq ($(CONFIG_RTL8192F), y)
-+RTL871X = rtl8192f
-+_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8192f_bb.o\
-+ hal/phydm/$(RTL871X)/halhwimg8192f_mac.o\
-+ hal/phydm/$(RTL871X)/halhwimg8192f_rf.o\
-+ hal/phydm/$(RTL871X)/phydm_hal_api8192f.o\
-+ hal/phydm/$(RTL871X)/phydm_regconfig8192f.o\
-+ hal/phydm/$(RTL871X)/phydm_rtl8192f.o\
-+ hal/phydm/halrf/$(RTL871X)/halrf_8192f.o
-+endif
-+
-+ifeq ($(CONFIG_RTL8198F), y)
-+RTL871X = rtl8198f
-+_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8198f_bb.o\
-+ hal/phydm/$(RTL871X)/halhwimg8198f_mac.o\
-+ hal/phydm/$(RTL871X)/halhwimg8198f_rf.o\
-+ hal/phydm/$(RTL871X)/phydm_hal_api8198f.o\
-+ hal/phydm/$(RTL871X)/phydm_regconfig8198f.o
-+endif
-+
-+ifeq ($(CONFIG_RTL8822C), y)
-+RTL871X = rtl8822c
-+_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8822c_bb.o\
-+ hal/phydm/$(RTL871X)/halhwimg8822c_mac.o\
-+ hal/phydm/$(RTL871X)/halhwimg8822c_rf.o\
-+ hal/phydm/$(RTL871X)/phydm_hal_api8822c.o\
-+ hal/phydm/$(RTL871X)/phydm_regconfig8822c.o\
-+ hal/phydm/halrf/$(RTL871X)/halrf_8822c.o\
-+ hal/phydm/halrf/$(RTL871X)/halrf_iqk_8822c.o\
-+ hal/phydm/halrf/$(RTL871X)/halrf_tssi_8822c.o\
-+ hal/phydm/halrf/$(RTL871X)/halrf_dpk_8822c.o\
-+ hal/phydm/halrf/$(RTL871X)/halrf_rfk_init_8822c.o
-+endif
-+
-+ifeq ($(CONFIG_RTL8814B), y)
-+RTL871X = rtl8814b
-+_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8814b_bb.o\
-+ hal/phydm/$(RTL871X)/phydm_hal_api8814b.o\
-+ hal/phydm/$(RTL871X)/phydm_regconfig8814b.o\
-+ hal/phydm/halrf/$(RTL871X)/halrf_8814b.o \
-+ hal/phydm/halrf/$(RTL871X)/halrf_iqk_8814b.o \
-+ hal/phydm/halrf/$(RTL871X)/halrf_rfk_init_8814b.o
-+endif
-\ No newline at end of file
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_adaptivity.c linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_adaptivity.c
-new file mode 100644
-index 000000000..086903624
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_adaptivity.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/phydm_adaptivity.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/phydm_adaptivity.c
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/phydm_adaptivity.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/phydm_adaptivity.c 2021-03-07 18:16:17.059956289 +0200
@@ -0,0 +1,764 @@
+/******************************************************************************
+ *
@@ -205941,11 +198018,9 @@ index 000000000..086903624
+ return;
+#endif
+}
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_adaptivity.h linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_adaptivity.h
-new file mode 100644
-index 000000000..147a12527
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_adaptivity.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/phydm_adaptivity.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/phydm_adaptivity.h
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/phydm_adaptivity.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/phydm_adaptivity.h 2021-03-07 18:16:17.059956289 +0200
@@ -0,0 +1,122 @@
+/******************************************************************************
+ *
@@ -206069,11 +198144,9 @@ index 000000000..147a12527
+void phydm_adaptivity(void *dm_void);
+
+#endif
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_adc_sampling.c linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_adc_sampling.c
-new file mode 100644
-index 000000000..d2278560e
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_adc_sampling.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/phydm_adc_sampling.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/phydm_adc_sampling.c
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/phydm_adc_sampling.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/phydm_adc_sampling.c 2021-03-07 18:16:17.059956289 +0200
@@ -0,0 +1,1291 @@
+/******************************************************************************
+ *
@@ -207366,11 +199439,9 @@ index 000000000..d2278560e
+}
+
+#endif /*@endif PHYDM_LA_MODE_SUPPORT*/
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_adc_sampling.h linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_adc_sampling.h
-new file mode 100644
-index 000000000..ef5520184
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_adc_sampling.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/phydm_adc_sampling.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/phydm_adc_sampling.h
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/phydm_adc_sampling.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/phydm_adc_sampling.h 2021-03-07 18:16:17.059956289 +0200
@@ -0,0 +1,151 @@
+/******************************************************************************
+ *
@@ -207523,11 +199594,9 @@ index 000000000..ef5520184
+
+#endif
+#endif
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_antdect.c linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_antdect.c
-new file mode 100644
-index 000000000..5a44a054a
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_antdect.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/phydm_antdect.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/phydm_antdect.c
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/phydm_antdect.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/phydm_antdect.c 2021-03-07 18:16:17.059956289 +0200
@@ -0,0 +1,891 @@
+/******************************************************************************
+ *
@@ -208420,11 +200489,9 @@ index 000000000..5a44a054a
+}
+#endif
+
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_antdect.h linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_antdect.h
-new file mode 100644
-index 000000000..f7fc75f18
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_antdect.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/phydm_antdect.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/phydm_antdect.h
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/phydm_antdect.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/phydm_antdect.h 2021-03-07 18:16:17.059956289 +0200
@@ -0,0 +1,78 @@
+/******************************************************************************
+ *
@@ -208504,11 +200571,9 @@ index 000000000..f7fc75f18
+void odm_sw_ant_detect_init(void *dm_void);
+#endif
+#endif
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_antdiv.c linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_antdiv.c
-new file mode 100644
-index 000000000..702406e68
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_antdiv.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/phydm_antdiv.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/phydm_antdiv.c
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/phydm_antdiv.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/phydm_antdiv.c 2021-03-07 18:16:17.060956337 +0200
@@ -0,0 +1,5897 @@
+/******************************************************************************
+ *
@@ -214407,11 +206472,9 @@ index 000000000..702406e68
+}
+#endif /*@#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY*/
+
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_antdiv.h linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_antdiv.h
-new file mode 100644
-index 000000000..0449ce821
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_antdiv.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/phydm_antdiv.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/phydm_antdiv.h
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/phydm_antdiv.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/phydm_antdiv.h 2021-03-07 18:16:17.060956337 +0200
@@ -0,0 +1,519 @@
+/******************************************************************************
+ *
@@ -214932,11 +206995,9 @@ index 000000000..0449ce821
+void odm_antenna_diversity(void *dm_void);
+#endif /*@#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY*/
+#endif /*@#ifndef __ODMANTDIV_H__*/
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_api.c linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_api.c
-new file mode 100644
-index 000000000..f84279c39
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_api.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/phydm_api.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/phydm_api.c
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/phydm_api.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/phydm_api.c 2021-03-07 18:16:17.060956337 +0200
@@ -0,0 +1,2949 @@
+/******************************************************************************
+ *
@@ -217887,11 +209948,9 @@ index 000000000..f84279c39
+#endif
+}
+#endif
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_api.h linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_api.h
-new file mode 100644
-index 000000000..8ab47a0c5
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_api.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/phydm_api.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/phydm_api.h
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/phydm_api.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/phydm_api.h 2021-03-07 18:16:17.060956337 +0200
@@ -0,0 +1,186 @@
+/******************************************************************************
+ *
@@ -218079,11 +210138,9 @@ index 000000000..8ab47a0c5
+#endif
+
+#endif
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_auto_dbg.c linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_auto_dbg.c
-new file mode 100644
-index 000000000..1a9d95331
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_auto_dbg.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/phydm_auto_dbg.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/phydm_auto_dbg.c
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/phydm_auto_dbg.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/phydm_auto_dbg.c 2021-03-07 18:16:17.060956337 +0200
@@ -0,0 +1,713 @@
+/******************************************************************************
+ *
@@ -218798,11 +210855,9 @@ index 000000000..1a9d95331
+ phydm_check_hang_init(dm);
+}
+#endif
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_auto_dbg.h linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_auto_dbg.h
-new file mode 100644
-index 000000000..f6ef51d4f
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_auto_dbg.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/phydm_auto_dbg.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/phydm_auto_dbg.h
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/phydm_auto_dbg.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/phydm_auto_dbg.h 2021-03-07 18:16:17.060956337 +0200
@@ -0,0 +1,113 @@
+/******************************************************************************
+ *
@@ -218917,11 +210972,9 @@ index 000000000..f6ef51d4f
+void phydm_auto_dbg_engine_init(void *dm_void);
+#endif
+#endif
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_beamforming.c linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_beamforming.c
-new file mode 100644
-index 000000000..bc4855c15
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_beamforming.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/phydm_beamforming.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/phydm_beamforming.c
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/phydm_beamforming.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/phydm_beamforming.c 2021-03-07 18:16:17.061956384 +0200
@@ -0,0 +1,2050 @@
+/******************************************************************************
+ *
@@ -220973,11 +213026,9 @@ index 000000000..bc4855c15
+}
+
+#endif
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_beamforming.h linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_beamforming.h
-new file mode 100644
-index 000000000..26e54c0ee
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_beamforming.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/phydm_beamforming.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/phydm_beamforming.h
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/phydm_beamforming.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/phydm_beamforming.h 2021-03-07 18:16:17.061956384 +0200
@@ -0,0 +1,363 @@
+/******************************************************************************
+ *
@@ -221342,11 +213393,3278 @@ index 000000000..26e54c0ee
+#endif /*@(DM_ODM_SUPPORT_TYPE & (ODM_CE | ODM_AP))*/
+#endif /*@#ifdef PHYDM_BEAMFORMING_SUPPORT*/
+#endif
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_cck_pd.c linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_cck_pd.c
-new file mode 100644
-index 000000000..8f5229abf
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_cck_pd.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/phydm.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/phydm.c
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/phydm.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/phydm.c 2021-03-07 18:16:17.058956242 +0200
+@@ -0,0 +1,3265 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * The full GNU General Public License is included in this distribution in the
++ * file called LICENSE.
++ *
++ * Contact Information:
++ * wlanfae
++ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
++ * Hsinchu 300, Taiwan.
++ *
++ * Larry Finger
++ *
++ *****************************************************************************/
++
++/*@************************************************************
++ * include files
++ ************************************************************/
++
++#include "mp_precomp.h"
++#include "phydm_precomp.h"
++
++const u16 phy_rate_table[] = {
++ /*@20M*/
++ 1, 2, 5, 11,
++ 6, 9, 12, 18, 24, 36, 48, 54,
++ 6, 13, 19, 26, 39, 52, 58, 65, /*@MCS0~7*/
++ 13, 26, 39, 52, 78, 104, 117, 130 /*@MCS8~15*/
++};
++
++void phydm_traffic_load_decision(void *dm_void)
++{
++ struct dm_struct *dm = (struct dm_struct *)dm_void;
++ u8 shift = 0;
++
++ /*@---TP & Trafic-load calculation---*/
++
++ if (dm->last_tx_ok_cnt > *dm->num_tx_bytes_unicast)
++ dm->last_tx_ok_cnt = *dm->num_tx_bytes_unicast;
++
++ if (dm->last_rx_ok_cnt > *dm->num_rx_bytes_unicast)
++ dm->last_rx_ok_cnt = *dm->num_rx_bytes_unicast;
++
++ dm->cur_tx_ok_cnt = *dm->num_tx_bytes_unicast - dm->last_tx_ok_cnt;
++ dm->cur_rx_ok_cnt = *dm->num_rx_bytes_unicast - dm->last_rx_ok_cnt;
++ dm->last_tx_ok_cnt = *dm->num_tx_bytes_unicast;
++ dm->last_rx_ok_cnt = *dm->num_rx_bytes_unicast;
++
++ /*@AP: <<3(8bit), >>20(10^6,M), >>0(1sec)*/
++ shift = 17 + (PHYDM_WATCH_DOG_PERIOD - 1);
++ /*@WIN&CE: <<3(8bit), >>20(10^6,M), >>1(2sec)*/
++
++ dm->tx_tp = (dm->tx_tp >> 1) + (u32)((dm->cur_tx_ok_cnt >> shift) >> 1);
++ dm->rx_tp = (dm->rx_tp >> 1) + (u32)((dm->cur_rx_ok_cnt >> shift) >> 1);
++
++ dm->total_tp = dm->tx_tp + dm->rx_tp;
++
++ /*@[Calculate TX/RX state]*/
++ if (dm->tx_tp > (dm->rx_tp << 1))
++ dm->txrx_state_all = TX_STATE;
++ else if (dm->rx_tp > (dm->tx_tp << 1))
++ dm->txrx_state_all = RX_STATE;
++ else
++ dm->txrx_state_all = BI_DIRECTION_STATE;
++
++ /*@[Traffic load decision]*/
++ dm->pre_traffic_load = dm->traffic_load;
++
++ if (dm->cur_tx_ok_cnt > 1875000 || dm->cur_rx_ok_cnt > 1875000) {
++ /* @( 1.875M * 8bit ) / 2sec= 7.5M bits /sec )*/
++ dm->traffic_load = TRAFFIC_HIGH;
++ } else if (dm->cur_tx_ok_cnt > 500000 || dm->cur_rx_ok_cnt > 500000) {
++ /*@( 0.5M * 8bit ) / 2sec = 2M bits /sec )*/
++ dm->traffic_load = TRAFFIC_MID;
++ } else if (dm->cur_tx_ok_cnt > 100000 || dm->cur_rx_ok_cnt > 100000) {
++ /*@( 0.1M * 8bit ) / 2sec = 0.4M bits /sec )*/
++ dm->traffic_load = TRAFFIC_LOW;
++ } else if (dm->cur_tx_ok_cnt > 25000 || dm->cur_rx_ok_cnt > 25000) {
++ /*@( 0.025M * 8bit ) / 2sec = 0.1M bits /sec )*/
++ dm->traffic_load = TRAFFIC_ULTRA_LOW;
++ } else {
++ dm->traffic_load = TRAFFIC_NO_TP;
++ }
++
++ /*@[Calculate consecutive idlel time]*/
++ if (dm->traffic_load == 0)
++ dm->consecutive_idlel_time += PHYDM_WATCH_DOG_PERIOD;
++ else
++ dm->consecutive_idlel_time = 0;
++
++ #if 0
++ PHYDM_DBG(dm, DBG_COMMON_FLOW,
++ "cur_tx_ok_cnt = %d, cur_rx_ok_cnt = %d, last_tx_ok_cnt = %d, last_rx_ok_cnt = %d\n",
++ dm->cur_tx_ok_cnt, dm->cur_rx_ok_cnt, dm->last_tx_ok_cnt,
++ dm->last_rx_ok_cnt);
++
++ PHYDM_DBG(dm, DBG_COMMON_FLOW, "tx_tp = %d, rx_tp = %d\n", dm->tx_tp,
++ dm->rx_tp);
++ #endif
++}
++
++void phydm_cck_new_agc_chk(struct dm_struct *dm)
++{
++ dm->cck_new_agc = 0;
++
++#if ((RTL8723D_SUPPORT == 1) || (RTL8822B_SUPPORT == 1) || \
++ (RTL8821C_SUPPORT == 1) || (RTL8197F_SUPPORT == 1) || \
++ (RTL8710B_SUPPORT == 1) || (RTL8192F_SUPPORT == 1) || \
++ (RTL8195B_SUPPORT == 1) || (RTL8198F_SUPPORT == 1) || \
++ (RTL8822C_SUPPORT == 1) || (RTL8721D_SUPPORT == 1))
++ if (dm->support_ic_type &
++ (ODM_RTL8723D | ODM_RTL8822B | ODM_RTL8821C | ODM_RTL8197F |
++ ODM_RTL8710B | ODM_RTL8192F | ODM_RTL8195B | ODM_RTL8721D)) {
++ /*@1: new agc 0: old agc*/
++ dm->cck_new_agc = (boolean)odm_get_bb_reg(dm, R_0xa9c, BIT(17));
++ } else if (dm->support_ic_type & (ODM_RTL8198F | ODM_RTL8822C)) {
++ /*@1: new agc 0: old agc*/
++ dm->cck_new_agc = (boolean)odm_get_bb_reg(dm, R_0x1a9c,
++ BIT(17));
++ }
++#endif
++}
++
++/*select 3 or 4 bit LNA */
++void phydm_cck_lna_bit_num_chk(struct dm_struct *dm)
++{
++ boolean report_type = 0;
++ #if (RTL8192E_SUPPORT == 1)
++ u32 value_824, value_82c;
++ #endif
++
++ #if (RTL8192E_SUPPORT == 1)
++ if (dm->support_ic_type & (ODM_RTL8192E)) {
++ /* @0x824[9] = 0x82C[9] = 0xA80[7] those registers setting
++ * should be equal or CCK RSSI report may be incorrect
++ */
++ value_824 = odm_get_bb_reg(dm, R_0x824, BIT(9));
++ value_82c = odm_get_bb_reg(dm, R_0x82c, BIT(9));
++
++ if (value_824 != value_82c)
++ odm_set_bb_reg(dm, R_0x82c, BIT(9), value_824);
++ odm_set_bb_reg(dm, R_0xa80, BIT(7), value_824);
++ report_type = (boolean)value_824;
++ }
++ #endif
++
++ #if (RTL8703B_SUPPORT || RTL8723D_SUPPORT || RTL8710B_SUPPORT)
++ if (dm->support_ic_type &
++ (ODM_RTL8703B | ODM_RTL8723D | ODM_RTL8710B)) {
++ report_type = (boolean)odm_get_bb_reg(dm, R_0x950, BIT(11));
++
++ if (report_type != 1)
++ pr_debug("[Warning] CCK should be 4bit LNA\n");
++ }
++ #endif
++
++ #if (RTL8821C_SUPPORT == 1)
++ if (dm->support_ic_type & ODM_RTL8821C) {
++ if (dm->default_rf_set_8821c == SWITCH_TO_BTG)
++ report_type = 1;
++ }
++ #endif
++
++ dm->cck_agc_report_type = report_type;
++
++ PHYDM_DBG(dm, ODM_COMP_INIT, "cck_agc_report_type=((%d))\n",
++ dm->cck_agc_report_type);
++}
++
++void phydm_init_cck_setting(struct dm_struct *dm)
++{
++ u32 reg_tmp = 0;
++ u32 mask_tmp = 0;
++
++ reg_tmp = ODM_REG(CCK_RPT_FORMAT, dm);
++ mask_tmp = ODM_BIT(CCK_RPT_FORMAT, dm);
++ dm->is_cck_high_power = (boolean)odm_get_bb_reg(dm, reg_tmp, mask_tmp);
++
++ PHYDM_DBG(dm, ODM_COMP_INIT, "ext_lna_gain=((%d))\n", dm->ext_lna_gain);
++
++ phydm_config_cck_rx_antenna_init(dm);
++
++ if (dm->support_ic_type & (ODM_RTL8192F))
++ phydm_config_cck_rx_path(dm, BB_PATH_AB);
++ else
++ phydm_config_cck_rx_path(dm, BB_PATH_A);
++
++ phydm_cck_new_agc_chk(dm);
++ phydm_cck_lna_bit_num_chk(dm);
++ phydm_get_cck_rssi_table_from_reg(dm);
++}
++
++void phydm_init_hw_info_by_rfe(struct dm_struct *dm)
++{
++#if (RTL8822B_SUPPORT == 1)
++ /*@if (dm->support_ic_type & ODM_RTL8822B)*/
++ /*@phydm_init_hw_info_by_rfe_type_8822b(dm);*/
++#endif
++#if (RTL8821C_SUPPORT == 1)
++ if (dm->support_ic_type & ODM_RTL8821C)
++ phydm_init_hw_info_by_rfe_type_8821c(dm);
++#endif
++#if (RTL8197F_SUPPORT == 1)
++ if (dm->support_ic_type & ODM_RTL8197F)
++ phydm_init_hw_info_by_rfe_type_8197f(dm);
++#endif
++}
++
++void phydm_common_info_self_init(struct dm_struct *dm)
++{
++ u32 reg_tmp = 0;
++ u32 mask_tmp = 0;
++
++ /*@BB IP Generation*/
++ if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
++ dm->ic_ip_series = PHYDM_IC_JGR3;
++ else if (dm->support_ic_type & ODM_IC_11AC_SERIES)
++ dm->ic_ip_series = PHYDM_IC_AC;
++ else if (dm->support_ic_type & ODM_IC_11N_SERIES)
++ dm->ic_ip_series = PHYDM_IC_N;
++
++ /*@BB phy-status Generation*/
++ if (dm->support_ic_type & PHYSTS_3RD_TYPE_IC)
++ dm->ic_phy_sts_type = PHYDM_PHYSTS_TYPE_3;
++ else if (dm->support_ic_type & PHYSTS_2ND_TYPE_IC)
++ dm->ic_phy_sts_type = PHYDM_PHYSTS_TYPE_2;
++ else
++ dm->ic_phy_sts_type = PHYDM_PHYSTS_TYPE_1;
++
++ phydm_init_cck_setting(dm);
++
++ reg_tmp = ODM_REG(BB_RX_PATH, dm);
++ mask_tmp = ODM_BIT(BB_RX_PATH, dm);
++ dm->rf_path_rx_enable = (u8)odm_get_bb_reg(dm, reg_tmp, mask_tmp);
++#if (DM_ODM_SUPPORT_TYPE != ODM_CE)
++ dm->is_net_closed = &dm->BOOLEAN_temp;
++
++ phydm_init_debug_setting(dm);
++#endif
++ phydm_init_soft_ml_setting(dm);
++
++ dm->phydm_sys_up_time = 0;
++
++ if (dm->support_ic_type & ODM_IC_1SS)
++ dm->num_rf_path = 1;
++ else if (dm->support_ic_type & ODM_IC_2SS)
++ dm->num_rf_path = 2;
++ #if 0
++ /* @RTK do not has IC which is equipped with 3 RF paths,
++ * so ODM_IC_3SS is an enpty macro and result in coverity check errors
++ */
++ else if (dm->support_ic_type & ODM_IC_3SS)
++ dm->num_rf_path = 3;
++ #endif
++ else if (dm->support_ic_type & ODM_IC_4SS)
++ dm->num_rf_path = 4;
++ else
++ dm->num_rf_path = 1;
++
++ phydm_trx_antenna_setting_init(dm, dm->num_rf_path);
++
++ dm->tx_rate = 0xFF;
++ dm->rssi_min_by_path = 0xFF;
++
++ dm->number_linked_client = 0;
++ dm->pre_number_linked_client = 0;
++ dm->number_active_client = 0;
++ dm->pre_number_active_client = 0;
++
++ dm->last_tx_ok_cnt = 0;
++ dm->last_rx_ok_cnt = 0;
++ dm->tx_tp = 0;
++ dm->rx_tp = 0;
++ dm->total_tp = 0;
++ dm->traffic_load = TRAFFIC_LOW;
++
++ dm->nbi_set_result = 0;
++ dm->is_init_hw_info_by_rfe = false;
++ dm->pre_dbg_priority = DBGPORT_RELEASE;
++ dm->tp_active_th = 5;
++ dm->disable_phydm_watchdog = 0;
++
++ dm->u8_dummy = 0xf;
++ dm->u16_dummy = 0xffff;
++ dm->u32_dummy = 0xffffffff;
++
++ dm->pause_lv_table.lv_cckpd = PHYDM_PAUSE_RELEASE;
++ dm->pause_lv_table.lv_dig = PHYDM_PAUSE_RELEASE;
++}
++
++void phydm_cmn_sta_info_update(void *dm_void, u8 macid)
++{
++ struct dm_struct *dm = (struct dm_struct *)dm_void;
++ struct cmn_sta_info *sta = dm->phydm_sta_info[macid];
++ struct ra_sta_info *ra = NULL;
++
++ if (is_sta_active(sta)) {
++ ra = &sta->ra_info;
++ } else {
++ PHYDM_DBG(dm, DBG_RA_MASK, "[Warning] %s invalid sta_info\n",
++ __func__);
++ return;
++ }
++
++ PHYDM_DBG(dm, DBG_RA_MASK, "%s ======>\n", __func__);
++ PHYDM_DBG(dm, DBG_RA_MASK, "MACID=%d\n", sta->mac_id);
++
++ /*@[Calculate TX/RX state]*/
++ if (sta->tx_moving_average_tp > (sta->rx_moving_average_tp << 1))
++ ra->txrx_state = TX_STATE;
++ else if (sta->rx_moving_average_tp > (sta->tx_moving_average_tp << 1))
++ ra->txrx_state = RX_STATE;
++ else
++ ra->txrx_state = BI_DIRECTION_STATE;
++
++ ra->is_noisy = dm->noisy_decision;
++}
++
++void phydm_common_info_self_update(struct dm_struct *dm)
++{
++ u8 sta_cnt = 0, num_active_client = 0;
++ u32 i, one_entry_macid = 0;
++ u32 ma_rx_tp = 0;
++ u32 tp_diff = 0;
++ struct cmn_sta_info *sta;
++
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++
++ PADAPTER adapter = (PADAPTER)dm->adapter;
++
++ PMGNT_INFO mgnt_info = &((PADAPTER)adapter)->MgntInfo;
++
++ sta = dm->phydm_sta_info[0];
++ if (mgnt_info->mAssoc) {
++ sta->dm_ctrl |= STA_DM_CTRL_ACTIVE;
++ for (i = 0; i < 6; i++)
++ sta->mac_addr[i] = mgnt_info->Bssid[i];
++ } else if (GetFirstClientPort(adapter)) {
++ //void *client_adapter = GetFirstClientPort(adapter);
++ struct _ADAPTER *client_adapter = GetFirstClientPort(adapter);
++
++ sta->dm_ctrl |= STA_DM_CTRL_ACTIVE;
++ for (i = 0; i < 6; i++)
++ sta->mac_addr[i] = client_adapter->MgntInfo.Bssid[i];
++ } else {
++ sta->dm_ctrl = sta->dm_ctrl & (~STA_DM_CTRL_ACTIVE);
++ for (i = 0; i < 6; i++)
++ sta->mac_addr[i] = 0;
++ }
++
++ /* STA mode is linked to AP */
++ if (is_sta_active(sta) && !ACTING_AS_AP(adapter))
++ dm->bsta_state = true;
++ else
++ dm->bsta_state = false;
++#endif
++
++ for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
++ sta = dm->phydm_sta_info[i];
++ if (is_sta_active(sta)) {
++ sta_cnt++;
++
++ if (sta_cnt == 1)
++ one_entry_macid = i;
++
++ phydm_cmn_sta_info_update(dm, (u8)i);
++ #ifdef PHYDM_BEAMFORMING_SUPPORT
++ /*@phydm_get_txbf_device_num(dm, (u8)i);*/
++ #endif
++
++ ma_rx_tp = sta->rx_moving_average_tp +
++ sta->tx_moving_average_tp;
++
++ PHYDM_DBG(dm, DBG_COMMON_FLOW,
++ "TP[%d]: ((%d )) bit/sec\n", i, ma_rx_tp);
++
++ if (ma_rx_tp > ACTIVE_TP_THRESHOLD)
++ num_active_client++;
++ }
++ }
++
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++ dm->is_linked = (sta_cnt != 0) ? true : false;
++#endif
++
++ if (sta_cnt == 1) {
++ dm->is_one_entry_only = true;
++ dm->one_entry_macid = one_entry_macid;
++ dm->one_entry_tp = ma_rx_tp;
++
++ dm->tp_active_occur = 0;
++
++ PHYDM_DBG(dm, DBG_COMMON_FLOW,
++ "one_entry_tp=((%d)), pre_one_entry_tp=((%d))\n",
++ dm->one_entry_tp, dm->pre_one_entry_tp);
++
++ if (dm->one_entry_tp > dm->pre_one_entry_tp &&
++ dm->pre_one_entry_tp <= 2) {
++ tp_diff = dm->one_entry_tp - dm->pre_one_entry_tp;
++
++ if (tp_diff > dm->tp_active_th)
++ dm->tp_active_occur = 1;
++ }
++ dm->pre_one_entry_tp = dm->one_entry_tp;
++ } else {
++ dm->is_one_entry_only = false;
++ }
++
++ dm->pre_number_linked_client = dm->number_linked_client;
++ dm->pre_number_active_client = dm->number_active_client;
++
++ dm->number_linked_client = sta_cnt;
++ dm->number_active_client = num_active_client;
++
++ /*Traffic load information update*/
++ phydm_traffic_load_decision(dm);
++
++ dm->phydm_sys_up_time += PHYDM_WATCH_DOG_PERIOD;
++
++ dm->is_dfs_band = phydm_is_dfs_band(dm);
++ dm->phy_dbg_info.show_phy_sts_cnt = 0;
++}
++
++void phydm_common_info_self_reset(struct dm_struct *dm)
++{
++ struct odm_phy_dbg_info *dbg_t = &dm->phy_dbg_info;
++
++ dbg_t->beacon_cnt_in_period = dbg_t->num_qry_beacon_pkt;
++ dbg_t->num_qry_beacon_pkt = 0;
++
++ dm->rxsc_l = 0xff;
++ dm->rxsc_20 = 0xff;
++ dm->rxsc_40 = 0xff;
++ dm->rxsc_80 = 0xff;
++}
++
++void *
++phydm_get_structure(struct dm_struct *dm, u8 structure_type)
++
++{
++ void *structure = NULL;
++
++ switch (structure_type) {
++ case PHYDM_FALSEALMCNT:
++ structure = &dm->false_alm_cnt;
++ break;
++
++ case PHYDM_CFOTRACK:
++ structure = &dm->dm_cfo_track;
++ break;
++
++ case PHYDM_ADAPTIVITY:
++ structure = &dm->adaptivity;
++ break;
++
++ case PHYDM_DFS:
++ structure = &dm->dfs;
++ break;
++
++ default:
++ break;
++ }
++
++ return structure;
++}
++
++void phydm_phy_info_update(struct dm_struct *dm)
++{
++#if (RTL8822B_SUPPORT == 1)
++ if (dm->support_ic_type == ODM_RTL8822B)
++ dm->phy_dbg_info.condi_num = phydm_get_condi_num_8822b(dm);
++#endif
++}
++
++void phydm_hw_setting(struct dm_struct *dm)
++{
++#if (RTL8821A_SUPPORT == 1)
++ if (dm->support_ic_type & ODM_RTL8821)
++ odm_hw_setting_8821a(dm);
++#endif
++
++#if 0 /* TODO: implementation done but may not work and do nothing with current flags. Commenting the code to match previous version behavior*/
++#if (RTL8814A_SUPPORT == 1)
++ if (dm->support_ic_type & ODM_RTL8814A)
++ phydm_hwsetting_8814a(dm);
++#endif
++#endif
++
++#if (RTL8822B_SUPPORT == 1)
++ if (dm->support_ic_type & ODM_RTL8822B)
++ phydm_hwsetting_8822b(dm);
++#endif
++
++#if (RTL8812A_SUPPORT == 1)
++ if (dm->support_ic_type & ODM_RTL8812)
++ phydm_hwsetting_8812a(dm);
++#endif
++
++#if (RTL8197F_SUPPORT == 1)
++ if (dm->support_ic_type & ODM_RTL8197F)
++ phydm_hwsetting_8197f(dm);
++#endif
++
++#if (RTL8192F_SUPPORT == 1)
++ if (dm->support_ic_type & ODM_RTL8192F)
++ phydm_hwsetting_8192f(dm);
++#endif
++}
++
++#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
++u64 phydm_supportability_init_win(
++ void *dm_void)
++{
++ struct dm_struct *dm = (struct dm_struct *)dm_void;
++ u64 support_ability = 0;
++
++ switch (dm->support_ic_type) {
++/*@---------------N Series--------------------*/
++#if (RTL8188E_SUPPORT)
++ case ODM_RTL8188E:
++ support_ability |=
++ ODM_BB_DIG |
++ ODM_BB_RA_MASK |
++ /*ODM_BB_DYNAMIC_TXPWR |*/
++ ODM_BB_FA_CNT |
++ ODM_BB_RSSI_MONITOR |
++ ODM_BB_CCK_PD |
++ /*ODM_BB_PWR_TRAIN |*/
++ ODM_BB_RATE_ADAPTIVE |
++ ODM_BB_CFO_TRACKING |
++ ODM_BB_ENV_MONITOR |
++ ODM_BB_PRIMARY_CCA;
++ break;
++#endif
++
++#if (RTL8192E_SUPPORT)
++ case ODM_RTL8192E:
++ support_ability |=
++ ODM_BB_DIG |
++ ODM_BB_RA_MASK |
++ /*ODM_BB_DYNAMIC_TXPWR |*/
++ ODM_BB_FA_CNT |
++ ODM_BB_RSSI_MONITOR |
++ ODM_BB_CCK_PD |
++ /*ODM_BB_PWR_TRAIN |*/
++ ODM_BB_RATE_ADAPTIVE |
++ ODM_BB_CFO_TRACKING |
++ ODM_BB_ENV_MONITOR |
++ ODM_BB_PRIMARY_CCA;
++ break;
++#endif
++
++#if (RTL8723B_SUPPORT)
++ case ODM_RTL8723B:
++ support_ability |=
++ ODM_BB_DIG |
++ ODM_BB_RA_MASK |
++ /*ODM_BB_DYNAMIC_TXPWR |*/
++ ODM_BB_FA_CNT |
++ ODM_BB_RSSI_MONITOR |
++ ODM_BB_CCK_PD |
++ /*ODM_BB_PWR_TRAIN |*/
++ ODM_BB_RATE_ADAPTIVE |
++ ODM_BB_CFO_TRACKING |
++ ODM_BB_ENV_MONITOR |
++ ODM_BB_PRIMARY_CCA;
++ break;
++#endif
++
++#if (RTL8703B_SUPPORT)
++ case ODM_RTL8703B:
++ support_ability |=
++ ODM_BB_DIG |
++ ODM_BB_RA_MASK |
++ /*ODM_BB_DYNAMIC_TXPWR |*/
++ ODM_BB_FA_CNT |
++ ODM_BB_RSSI_MONITOR |
++ ODM_BB_CCK_PD |
++ /*ODM_BB_PWR_TRAIN |*/
++ ODM_BB_RATE_ADAPTIVE |
++ ODM_BB_CFO_TRACKING |
++ ODM_BB_ENV_MONITOR;
++ break;
++#endif
++
++#if (RTL8723D_SUPPORT)
++ case ODM_RTL8723D:
++ support_ability |=
++ ODM_BB_DIG |
++ ODM_BB_RA_MASK |
++ /*ODM_BB_DYNAMIC_TXPWR |*/
++ ODM_BB_FA_CNT |
++ ODM_BB_RSSI_MONITOR |
++ ODM_BB_CCK_PD |
++ ODM_BB_PWR_TRAIN |
++ ODM_BB_RATE_ADAPTIVE |
++ ODM_BB_CFO_TRACKING |
++ ODM_BB_ENV_MONITOR;
++ break;
++#endif
++
++#if (RTL8710B_SUPPORT)
++ case ODM_RTL8710B:
++ support_ability |=
++ ODM_BB_DIG |
++ ODM_BB_RA_MASK |
++ /*ODM_BB_DYNAMIC_TXPWR |*/
++ ODM_BB_FA_CNT |
++ ODM_BB_RSSI_MONITOR |
++ ODM_BB_CCK_PD |
++ ODM_BB_PWR_TRAIN |
++ ODM_BB_RATE_ADAPTIVE |
++ ODM_BB_CFO_TRACKING |
++ ODM_BB_ENV_MONITOR;
++ break;
++#endif
++
++#if (RTL8188F_SUPPORT)
++ case ODM_RTL8188F:
++ support_ability |=
++ ODM_BB_DIG |
++ ODM_BB_RA_MASK |
++ /*ODM_BB_DYNAMIC_TXPWR |*/
++ ODM_BB_FA_CNT |
++ ODM_BB_RSSI_MONITOR |
++ ODM_BB_CCK_PD |
++ /*ODM_BB_PWR_TRAIN |*/
++ ODM_BB_RATE_ADAPTIVE |
++ ODM_BB_CFO_TRACKING |
++ ODM_BB_ENV_MONITOR;
++ break;
++#endif
++
++#if (RTL8192F_SUPPORT)
++ case ODM_RTL8192F:
++ support_ability |=
++ ODM_BB_DIG |
++ ODM_BB_RA_MASK |
++ ODM_BB_FA_CNT |
++ ODM_BB_RSSI_MONITOR |
++ ODM_BB_CCK_PD |
++ ODM_BB_PWR_TRAIN |
++ ODM_BB_RATE_ADAPTIVE |
++ ODM_BB_CFO_TRACKING |
++ ODM_BB_ADAPTIVE_SOML |
++ ODM_BB_ENV_MONITOR;
++ /*ODM_BB_LNA_SAT_CHK |*/
++ /*ODM_BB_PRIMARY_CCA*/
++
++ break;
++#endif
++
++/*@---------------AC Series-------------------*/
++
++#if (RTL8812A_SUPPORT || RTL8821A_SUPPORT)
++ case ODM_RTL8812:
++ case ODM_RTL8821:
++ support_ability |=
++ ODM_BB_DIG |
++ ODM_BB_RA_MASK |
++ ODM_BB_DYNAMIC_TXPWR |
++ ODM_BB_FA_CNT |
++ ODM_BB_RSSI_MONITOR |
++ ODM_BB_CCK_PD |
++ /*ODM_BB_PWR_TRAIN |*/
++ ODM_BB_RATE_ADAPTIVE |
++ ODM_BB_CFO_TRACKING |
++ ODM_BB_ENV_MONITOR;
++ break;
++#endif
++
++#if (RTL8814A_SUPPORT)
++ case ODM_RTL8814A:
++ support_ability |=
++ ODM_BB_DIG |
++ ODM_BB_RA_MASK |
++ ODM_BB_DYNAMIC_TXPWR |
++ ODM_BB_FA_CNT |
++ ODM_BB_RSSI_MONITOR |
++ ODM_BB_CCK_PD |
++ /*ODM_BB_PWR_TRAIN |*/
++ ODM_BB_RATE_ADAPTIVE |
++ ODM_BB_CFO_TRACKING |
++ ODM_BB_ENV_MONITOR;
++ break;
++#endif
++
++#if (RTL8822B_SUPPORT)
++ case ODM_RTL8822B:
++ support_ability |=
++ ODM_BB_DIG |
++ ODM_BB_RA_MASK |
++ /*ODM_BB_DYNAMIC_TXPWR |*/
++ ODM_BB_FA_CNT |
++ ODM_BB_RSSI_MONITOR |
++ ODM_BB_CCK_PD |
++ /*ODM_BB_PWR_TRAIN |*/
++ /*ODM_BB_ADAPTIVE_SOML |*/
++ ODM_BB_RATE_ADAPTIVE |
++ ODM_BB_CFO_TRACKING |
++ ODM_BB_ENV_MONITOR;
++ break;
++#endif
++
++#if (RTL8821C_SUPPORT)
++ case ODM_RTL8821C:
++ support_ability |=
++ ODM_BB_DIG |
++ ODM_BB_RA_MASK |
++ /*ODM_BB_DYNAMIC_TXPWR |*/
++ ODM_BB_FA_CNT |
++ ODM_BB_RSSI_MONITOR |
++ ODM_BB_CCK_PD |
++ /*ODM_BB_PWR_TRAIN |*/
++ ODM_BB_RATE_ADAPTIVE |
++ ODM_BB_CFO_TRACKING |
++ ODM_BB_ENV_MONITOR;
++ break;
++#endif
++
++/*@---------------JGR3 Series-------------------*/
++
++#if (RTL8822C_SUPPORT)
++ case ODM_RTL8822C:
++ support_ability |=
++ ODM_BB_DIG |
++ ODM_BB_RA_MASK |
++ /* ODM_BB_DYNAMIC_TXPWR |*/
++ ODM_BB_FA_CNT |
++ ODM_BB_RSSI_MONITOR |
++ ODM_BB_CCK_PD |
++ ODM_BB_RATE_ADAPTIVE |
++ ODM_BB_CFO_TRACKING |
++ ODM_BB_ENV_MONITOR;
++ break;
++#endif
++
++#if (RTL8814B_SUPPORT)
++ case ODM_RTL8814B:
++ support_ability |=
++ ODM_BB_DIG |
++ ODM_BB_RA_MASK |
++ /*ODM_BB_DYNAMIC_TXPWR |*/
++ ODM_BB_FA_CNT |
++ ODM_BB_RSSI_MONITOR |
++ /*ODM_BB_CCK_PD |*/
++ /*ODM_BB_PWR_TRAIN |*/
++ ODM_BB_RATE_ADAPTIVE |
++ ODM_BB_CFO_TRACKING;
++ /*ODM_BB_ENV_MONITOR;*/
++ break;
++#endif
++
++ default:
++ support_ability |=
++ ODM_BB_DIG |
++ ODM_BB_RA_MASK |
++ /*ODM_BB_DYNAMIC_TXPWR |*/
++ ODM_BB_FA_CNT |
++ ODM_BB_RSSI_MONITOR |
++ ODM_BB_CCK_PD |
++ /*ODM_BB_PWR_TRAIN |*/
++ ODM_BB_RATE_ADAPTIVE |
++ ODM_BB_CFO_TRACKING |
++ ODM_BB_ENV_MONITOR;
++
++ pr_debug("[Warning] Supportability Init Warning !!!\n");
++ break;
++ }
++
++ return support_ability;
++}
++#endif
++
++#if (DM_ODM_SUPPORT_TYPE & (ODM_CE))
++u64 phydm_supportability_init_ce(void *dm_void)
++{
++ struct dm_struct *dm = (struct dm_struct *)dm_void;
++ u64 support_ability = 0;
++
++ switch (dm->support_ic_type) {
++/*@---------------N Series--------------------*/
++#if (RTL8188E_SUPPORT)
++ case ODM_RTL8188E:
++ support_ability |=
++ ODM_BB_DIG |
++ ODM_BB_RA_MASK |
++ /*@ODM_BB_DYNAMIC_TXPWR |*/
++ ODM_BB_FA_CNT |
++ ODM_BB_RSSI_MONITOR |
++ ODM_BB_CCK_PD |
++ /*@ODM_BB_PWR_TRAIN |*/
++ ODM_BB_RATE_ADAPTIVE |
++ ODM_BB_CFO_TRACKING |
++ ODM_BB_ENV_MONITOR |
++ ODM_BB_PRIMARY_CCA;
++ break;
++#endif
++
++#if (RTL8192E_SUPPORT)
++ case ODM_RTL8192E:
++ support_ability |=
++ ODM_BB_DIG |
++ ODM_BB_RA_MASK |
++ /*@ODM_BB_DYNAMIC_TXPWR |*/
++ ODM_BB_FA_CNT |
++ ODM_BB_RSSI_MONITOR |
++ ODM_BB_CCK_PD |
++ /*@ODM_BB_PWR_TRAIN |*/
++ ODM_BB_RATE_ADAPTIVE |
++ ODM_BB_CFO_TRACKING |
++ ODM_BB_ENV_MONITOR |
++ ODM_BB_PRIMARY_CCA;
++ break;
++#endif
++
++#if (RTL8723B_SUPPORT)
++ case ODM_RTL8723B:
++ support_ability |=
++ ODM_BB_DIG |
++ ODM_BB_RA_MASK |
++ /*@ODM_BB_DYNAMIC_TXPWR |*/
++ ODM_BB_FA_CNT |
++ ODM_BB_RSSI_MONITOR |
++ ODM_BB_CCK_PD |
++ /*@ODM_BB_PWR_TRAIN |*/
++ ODM_BB_RATE_ADAPTIVE |
++ ODM_BB_CFO_TRACKING |
++ ODM_BB_ENV_MONITOR |
++ ODM_BB_PRIMARY_CCA;
++ break;
++#endif
++
++#if (RTL8703B_SUPPORT)
++ case ODM_RTL8703B:
++ support_ability |=
++ ODM_BB_DIG |
++ ODM_BB_RA_MASK |
++ /*@ODM_BB_DYNAMIC_TXPWR |*/
++ ODM_BB_FA_CNT |
++ ODM_BB_RSSI_MONITOR |
++ ODM_BB_CCK_PD |
++ /*@ODM_BB_PWR_TRAIN |*/
++ ODM_BB_RATE_ADAPTIVE |
++ ODM_BB_CFO_TRACKING |
++ ODM_BB_ENV_MONITOR;
++ break;
++#endif
++
++#if (RTL8723D_SUPPORT)
++ case ODM_RTL8723D:
++ support_ability |=
++ ODM_BB_DIG |
++ ODM_BB_RA_MASK |
++ /*@ODM_BB_DYNAMIC_TXPWR |*/
++ ODM_BB_FA_CNT |
++ ODM_BB_RSSI_MONITOR |
++ ODM_BB_CCK_PD |
++ ODM_BB_PWR_TRAIN |
++ ODM_BB_RATE_ADAPTIVE |
++ ODM_BB_CFO_TRACKING |
++ ODM_BB_ENV_MONITOR;
++ break;
++#endif
++
++#if (RTL8710B_SUPPORT)
++ case ODM_RTL8710B:
++ support_ability |=
++ ODM_BB_DIG |
++ ODM_BB_RA_MASK |
++ /*@ODM_BB_DYNAMIC_TXPWR |*/
++ ODM_BB_FA_CNT |
++ ODM_BB_RSSI_MONITOR |
++ ODM_BB_CCK_PD |
++ /*@ODM_BB_PWR_TRAIN |*/
++ ODM_BB_RATE_ADAPTIVE |
++ ODM_BB_CFO_TRACKING |
++ ODM_BB_ENV_MONITOR;
++ break;
++#endif
++
++#if (RTL8188F_SUPPORT)
++ case ODM_RTL8188F:
++ support_ability |=
++ ODM_BB_DIG |
++ ODM_BB_RA_MASK |
++ /*@ODM_BB_DYNAMIC_TXPWR |*/
++ ODM_BB_FA_CNT |
++ ODM_BB_RSSI_MONITOR |
++ ODM_BB_CCK_PD |
++ /*@ODM_BB_PWR_TRAIN |*/
++ ODM_BB_RATE_ADAPTIVE |
++ ODM_BB_CFO_TRACKING |
++ ODM_BB_ENV_MONITOR;
++ break;
++#endif
++
++#if (RTL8192F_SUPPORT)
++ case ODM_RTL8192F:
++ support_ability |=
++ ODM_BB_DIG |
++ ODM_BB_RA_MASK |
++ ODM_BB_FA_CNT |
++ ODM_BB_RSSI_MONITOR |
++ ODM_BB_CCK_PD |
++ ODM_BB_PWR_TRAIN |
++ ODM_BB_RATE_ADAPTIVE |
++ ODM_BB_CFO_TRACKING |
++ /*@ODM_BB_ADAPTIVE_SOML |*/
++ ODM_BB_ENV_MONITOR;
++ /*@ODM_BB_LNA_SAT_CHK |*/
++ /*@ODM_BB_PRIMARY_CCA*/
++ break;
++#endif
++/*@---------------AC Series-------------------*/
++
++#if (RTL8812A_SUPPORT || RTL8821A_SUPPORT)
++ case ODM_RTL8812:
++ case ODM_RTL8821:
++ support_ability |=
++ ODM_BB_DIG |
++ ODM_BB_RA_MASK |
++ /*@ODM_BB_DYNAMIC_TXPWR |*/
++ ODM_BB_FA_CNT |
++ ODM_BB_RSSI_MONITOR |
++ ODM_BB_CCK_PD |
++ /*@ODM_BB_PWR_TRAIN |*/
++ ODM_BB_RATE_ADAPTIVE |
++ ODM_BB_CFO_TRACKING |
++ ODM_BB_ENV_MONITOR;
++ break;
++#endif
++
++#if (RTL8814A_SUPPORT)
++ case ODM_RTL8814A:
++ support_ability |=
++ ODM_BB_DIG |
++ ODM_BB_RA_MASK |
++ /*@ODM_BB_DYNAMIC_TXPWR |*/
++ ODM_BB_FA_CNT |
++ ODM_BB_RSSI_MONITOR |
++ ODM_BB_CCK_PD |
++ /*@ODM_BB_PWR_TRAIN |*/
++ ODM_BB_RATE_ADAPTIVE |
++ ODM_BB_CFO_TRACKING |
++ ODM_BB_ENV_MONITOR;
++ break;
++#endif
++
++#if (RTL8822B_SUPPORT)
++ case ODM_RTL8822B:
++ support_ability |=
++ ODM_BB_DIG |
++ ODM_BB_RA_MASK |
++ /*@ODM_BB_DYNAMIC_TXPWR |*/
++ ODM_BB_FA_CNT |
++ ODM_BB_RSSI_MONITOR |
++ ODM_BB_CCK_PD |
++ /*@ODM_BB_PWR_TRAIN |*/
++ ODM_BB_RATE_ADAPTIVE |
++ ODM_BB_CFO_TRACKING |
++ ODM_BB_ENV_MONITOR;
++ break;
++#endif
++
++#if (RTL8821C_SUPPORT)
++ case ODM_RTL8821C:
++ support_ability |=
++ ODM_BB_DIG |
++ ODM_BB_RA_MASK |
++ /*@ODM_BB_DYNAMIC_TXPWR |*/
++ ODM_BB_FA_CNT |
++ ODM_BB_RSSI_MONITOR |
++ ODM_BB_CCK_PD |
++ /*@ODM_BB_PWR_TRAIN |*/
++ ODM_BB_RATE_ADAPTIVE |
++ ODM_BB_CFO_TRACKING |
++ ODM_BB_ENV_MONITOR;
++ break;
++#endif
++
++/*@---------------JGR3 Series-------------------*/
++
++#if (RTL8822C_SUPPORT)
++ case ODM_RTL8822C:
++ support_ability |=
++ ODM_BB_DIG |
++ ODM_BB_RA_MASK |
++ /* ODM_BB_DYNAMIC_TXPWR |*/
++ ODM_BB_FA_CNT |
++ ODM_BB_RSSI_MONITOR |
++ ODM_BB_CCK_PD |
++ ODM_BB_RATE_ADAPTIVE |
++ ODM_BB_CFO_TRACKING |
++ ODM_BB_ENV_MONITOR;
++ break;
++#endif
++
++#if (RTL8814B_SUPPORT)
++ case ODM_RTL8814B:
++ support_ability |=
++ ODM_BB_DIG |
++ ODM_BB_RA_MASK |
++ /*@ODM_BB_DYNAMIC_TXPWR |*/
++ ODM_BB_FA_CNT |
++ ODM_BB_RSSI_MONITOR;
++ /*ODM_BB_CCK_PD |*/
++ /*@ODM_BB_PWR_TRAIN |*/
++ /*ODM_BB_RATE_ADAPTIVE |*/
++ /*ODM_BB_CFO_TRACKING |*/
++ /*ODM_BB_ENV_MONITOR;*/
++ break;
++#endif
++
++ default:
++ support_ability |=
++ ODM_BB_DIG |
++ ODM_BB_RA_MASK |
++ /*@ODM_BB_DYNAMIC_TXPWR |*/
++ ODM_BB_FA_CNT |
++ ODM_BB_RSSI_MONITOR |
++ ODM_BB_CCK_PD |
++ /*@ODM_BB_PWR_TRAIN |*/
++ ODM_BB_RATE_ADAPTIVE |
++ ODM_BB_CFO_TRACKING |
++ ODM_BB_ENV_MONITOR;
++
++ pr_debug("[Warning] Supportability Init Warning !!!\n");
++ break;
++ }
++
++ return support_ability;
++}
++#endif
++
++#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
++u64 phydm_supportability_init_ap(
++ void *dm_void)
++{
++ struct dm_struct *dm = (struct dm_struct *)dm_void;
++ u64 support_ability = 0;
++
++ switch (dm->support_ic_type) {
++/*@---------------N Series--------------------*/
++#if (RTL8188E_SUPPORT)
++ case ODM_RTL8188E:
++ support_ability |=
++ ODM_BB_DIG |
++ ODM_BB_RA_MASK |
++ ODM_BB_FA_CNT |
++ ODM_BB_RSSI_MONITOR |
++ ODM_BB_CCK_PD |
++ /*ODM_BB_PWR_TRAIN |*/
++ ODM_BB_RATE_ADAPTIVE |
++ ODM_BB_CFO_TRACKING |
++ ODM_BB_ENV_MONITOR |
++ ODM_BB_PRIMARY_CCA;
++ break;
++#endif
++
++#if (RTL8192E_SUPPORT)
++ case ODM_RTL8192E:
++ support_ability |=
++ ODM_BB_DIG |
++ ODM_BB_RA_MASK |
++ ODM_BB_FA_CNT |
++ ODM_BB_RSSI_MONITOR |
++ ODM_BB_CCK_PD |
++ /*ODM_BB_PWR_TRAIN |*/
++ ODM_BB_RATE_ADAPTIVE |
++ ODM_BB_CFO_TRACKING |
++ ODM_BB_ENV_MONITOR |
++ ODM_BB_PRIMARY_CCA;
++ break;
++#endif
++
++#if (RTL8723B_SUPPORT)
++ case ODM_RTL8723B:
++ support_ability |=
++ ODM_BB_DIG |
++ ODM_BB_RA_MASK |
++ ODM_BB_FA_CNT |
++ ODM_BB_RSSI_MONITOR |
++ ODM_BB_CCK_PD |
++ /*ODM_BB_PWR_TRAIN |*/
++ ODM_BB_RATE_ADAPTIVE |
++ ODM_BB_CFO_TRACKING |
++ ODM_BB_ENV_MONITOR;
++ break;
++#endif
++
++#if (RTL8198F_SUPPORT || RTL8197F_SUPPORT)
++ case ODM_RTL8198F:
++ support_ability |=
++ /*ODM_BB_DIG |*/
++ ODM_BB_RA_MASK |
++ ODM_BB_FA_CNT |
++ ODM_BB_RSSI_MONITOR;
++ /*ODM_BB_CCK_PD |*/
++ /*ODM_BB_PWR_TRAIN |*/
++ /*ODM_BB_RATE_ADAPTIVE |*/
++ /*ODM_BB_CFO_TRACKING |*/
++ /*ODM_BB_ADAPTIVE_SOML |*/
++ /*ODM_BB_ENV_MONITOR |*/
++ /*ODM_BB_LNA_SAT_CHK |*/
++ /*ODM_BB_PRIMARY_CCA;*/
++ break;
++ case ODM_RTL8197F:
++ support_ability |=
++ ODM_BB_DIG |
++ ODM_BB_RA_MASK |
++ ODM_BB_FA_CNT |
++ ODM_BB_RSSI_MONITOR |
++ ODM_BB_CCK_PD |
++ /*ODM_BB_PWR_TRAIN |*/
++ ODM_BB_RATE_ADAPTIVE |
++ ODM_BB_CFO_TRACKING |
++ ODM_BB_ADAPTIVE_SOML |
++ ODM_BB_ENV_MONITOR |
++ ODM_BB_LNA_SAT_CHK |
++ ODM_BB_PRIMARY_CCA;
++ break;
++#endif
++
++#if (RTL8192F_SUPPORT)
++ case ODM_RTL8192F:
++ support_ability |=
++ ODM_BB_DIG |
++ ODM_BB_RA_MASK |
++ ODM_BB_FA_CNT |
++ ODM_BB_RSSI_MONITOR |
++ ODM_BB_CCK_PD |
++ /*ODM_BB_PWR_TRAIN |*/
++ ODM_BB_RATE_ADAPTIVE |
++ /*ODM_BB_CFO_TRACKING |*/
++ ODM_BB_ADAPTIVE_SOML |
++ /*ODM_BB_ENV_MONITOR |*/
++ /*ODM_BB_LNA_SAT_CHK |*/
++ /*ODM_BB_PRIMARY_CCA |*/
++ 0;
++ break;
++#endif
++
++/*@---------------AC Series-------------------*/
++
++#if (RTL8881A_SUPPORT)
++ case ODM_RTL8881A:
++ support_ability |=
++ ODM_BB_DIG |
++ ODM_BB_RA_MASK |
++ ODM_BB_FA_CNT |
++ ODM_BB_RSSI_MONITOR |
++ ODM_BB_CCK_PD |
++ /*ODM_BB_PWR_TRAIN |*/
++ ODM_BB_RATE_ADAPTIVE |
++ ODM_BB_CFO_TRACKING |
++ ODM_BB_ENV_MONITOR;
++ break;
++#endif
++
++#if (RTL8814A_SUPPORT)
++ case ODM_RTL8814A:
++ support_ability |=
++ ODM_BB_DIG |
++ ODM_BB_RA_MASK |
++ ODM_BB_FA_CNT |
++ ODM_BB_RSSI_MONITOR |
++ ODM_BB_CCK_PD |
++ /*ODM_BB_PWR_TRAIN |*/
++ ODM_BB_RATE_ADAPTIVE |
++ ODM_BB_CFO_TRACKING |
++ ODM_BB_ENV_MONITOR;
++ break;
++#endif
++
++#if (RTL8822B_SUPPORT)
++ case ODM_RTL8822B:
++ support_ability |=
++ ODM_BB_DIG |
++ ODM_BB_RA_MASK |
++ ODM_BB_FA_CNT |
++ ODM_BB_RSSI_MONITOR |
++ ODM_BB_CCK_PD |
++ /*ODM_BB_PWR_TRAIN |*/
++ /*ODM_BB_ADAPTIVE_SOML |*/
++ ODM_BB_RATE_ADAPTIVE |
++ ODM_BB_CFO_TRACKING |
++ ODM_BB_ENV_MONITOR;
++ break;
++#endif
++
++#if (RTL8821C_SUPPORT)
++ case ODM_RTL8821C:
++ support_ability |=
++ ODM_BB_DIG |
++ ODM_BB_RA_MASK |
++ ODM_BB_FA_CNT |
++ ODM_BB_RSSI_MONITOR |
++ ODM_BB_CCK_PD |
++ /*ODM_BB_PWR_TRAIN |*/
++ ODM_BB_RATE_ADAPTIVE |
++ ODM_BB_CFO_TRACKING |
++ ODM_BB_ENV_MONITOR;
++
++ break;
++#endif
++
++/*@---------------JGR3 Series-------------------*/
++
++#if (RTL8814B_SUPPORT)
++ case ODM_RTL8814B:
++ support_ability |=
++ ODM_BB_DIG |
++ ODM_BB_RA_MASK |
++ ODM_BB_FA_CNT |
++ ODM_BB_RSSI_MONITOR;
++ /*ODM_BB_CCK_PD |*/
++ /*ODM_BB_PWR_TRAIN |*/
++ /*ODM_BB_RATE_ADAPTIVE |*/
++ /*ODM_BB_CFO_TRACKING |*/
++ /*ODM_BB_ENV_MONITOR;*/
++ break;
++#endif
++
++ default:
++ support_ability |=
++ ODM_BB_DIG |
++ ODM_BB_RA_MASK |
++ ODM_BB_FA_CNT |
++ ODM_BB_RSSI_MONITOR |
++ ODM_BB_CCK_PD |
++ /*ODM_BB_PWR_TRAIN |*/
++ ODM_BB_RATE_ADAPTIVE |
++ ODM_BB_CFO_TRACKING |
++ ODM_BB_ENV_MONITOR;
++
++ pr_debug("[Warning] Supportability Init Warning !!!\n");
++ break;
++ }
++
++#if 0
++ /*@[Config Antenna Diveristy]*/
++ if (*dm->enable_antdiv)
++ support_ability |= ODM_BB_ANT_DIV;
++
++ /*@[Config Adaptivity]*/
++ if (*dm->enable_adaptivity)
++ support_ability |= ODM_BB_ADAPTIVITY;
++#endif
++
++ return support_ability;
++}
++#endif
++
++#if (DM_ODM_SUPPORT_TYPE & (ODM_IOT))
++u64 phydm_supportability_init_iot(
++ void *dm_void)
++{
++ struct dm_struct *dm = (struct dm_struct *)dm_void;
++ u64 support_ability = 0;
++
++ switch (dm->support_ic_type) {
++#if (RTL8710B_SUPPORT)
++ case ODM_RTL8710B:
++ support_ability |=
++ ODM_BB_DIG |
++ ODM_BB_RA_MASK |
++ /*ODM_BB_DYNAMIC_TXPWR |*/
++ ODM_BB_FA_CNT |
++ ODM_BB_RSSI_MONITOR |
++ ODM_BB_CCK_PD |
++ /*ODM_BB_PWR_TRAIN |*/
++ ODM_BB_RATE_ADAPTIVE |
++ ODM_BB_CFO_TRACKING |
++ ODM_BB_ENV_MONITOR;
++ break;
++#endif
++
++#if (RTL8195A_SUPPORT)
++ case ODM_RTL8195A:
++ support_ability |=
++ ODM_BB_DIG |
++ ODM_BB_RA_MASK |
++ /*ODM_BB_DYNAMIC_TXPWR |*/
++ ODM_BB_FA_CNT |
++ ODM_BB_RSSI_MONITOR |
++ ODM_BB_CCK_PD |
++ /*ODM_BB_PWR_TRAIN |*/
++ ODM_BB_RATE_ADAPTIVE |
++ ODM_BB_CFO_TRACKING |
++ ODM_BB_ENV_MONITOR;
++ break;
++#endif
++
++#if (RTL8195B_SUPPORT)
++ case ODM_RTL8195B:
++ support_ability |=
++ ODM_BB_DIG |
++ ODM_BB_RA_MASK |
++ /*ODM_BB_DYNAMIC_TXPWR |*/
++ ODM_BB_FA_CNT |
++ ODM_BB_RSSI_MONITOR |
++ ODM_BB_CCK_PD |
++ /*ODM_BB_PWR_TRAIN |*/
++ ODM_BB_RATE_ADAPTIVE |
++ ODM_BB_CFO_TRACKING;
++ /*ODM_BB_ENV_MONITOR*/
++ break;
++#endif
++
++#if (RTL8721D_SUPPORT)
++ case ODM_RTL8721D:
++ support_ability |=
++ ODM_BB_DIG |
++ ODM_BB_RA_MASK |
++ /*ODM_BB_DYNAMIC_TXPWR |*/
++ ODM_BB_FA_CNT |
++ ODM_BB_RSSI_MONITOR |
++ ODM_BB_CCK_PD |
++ /*ODM_BB_PWR_TRAIN |*/
++ ODM_BB_RATE_ADAPTIVE |
++ ODM_BB_CFO_TRACKING |
++ ODM_BB_ENV_MONITOR;
++ break;
++#endif
++
++ default:
++ support_ability |=
++ ODM_BB_DIG |
++ ODM_BB_RA_MASK |
++ /*ODM_BB_DYNAMIC_TXPWR |*/
++ ODM_BB_FA_CNT |
++ ODM_BB_RSSI_MONITOR |
++ ODM_BB_CCK_PD |
++ /*ODM_BB_PWR_TRAIN |*/
++ ODM_BB_RATE_ADAPTIVE |
++ ODM_BB_CFO_TRACKING |
++ ODM_BB_ENV_MONITOR;
++
++ pr_debug("[Warning] Supportability Init Warning !!!\n");
++ break;
++ }
++
++ return support_ability;
++}
++#endif
++
++void phydm_fwoffload_ability_init(struct dm_struct *dm,
++ enum phydm_offload_ability offload_ability)
++{
++ switch (offload_ability) {
++ case PHYDM_PHY_PARAM_OFFLOAD:
++ if (dm->support_ic_type &
++ (ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8821C))
++ dm->fw_offload_ability |= PHYDM_PHY_PARAM_OFFLOAD;
++ break;
++
++ case PHYDM_RF_IQK_OFFLOAD:
++ dm->fw_offload_ability |= PHYDM_RF_IQK_OFFLOAD;
++ break;
++
++ default:
++ PHYDM_DBG(dm, ODM_COMP_INIT, "fwofflad, wrong init type!!\n");
++ break;
++ }
++
++ PHYDM_DBG(dm, ODM_COMP_INIT, "fw_offload_ability = %x\n",
++ dm->fw_offload_ability);
++}
++
++void phydm_fwoffload_ability_clear(struct dm_struct *dm,
++ enum phydm_offload_ability offload_ability)
++{
++ switch (offload_ability) {
++ case PHYDM_PHY_PARAM_OFFLOAD:
++ if (dm->support_ic_type &
++ (ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8821C))
++ dm->fw_offload_ability &= (~PHYDM_PHY_PARAM_OFFLOAD);
++ break;
++
++ case PHYDM_RF_IQK_OFFLOAD:
++ dm->fw_offload_ability &= (~PHYDM_RF_IQK_OFFLOAD);
++ break;
++
++ default:
++ PHYDM_DBG(dm, ODM_COMP_INIT, "fwofflad, wrong init type!!\n");
++ break;
++ }
++
++ PHYDM_DBG(dm, ODM_COMP_INIT, "fw_offload_ability = %x\n",
++ dm->fw_offload_ability);
++}
++
++void phydm_supportability_init(void *dm_void)
++{
++ struct dm_struct *dm = (struct dm_struct *)dm_void;
++ u64 support_ability;
++
++ if (*dm->mp_mode) {
++ support_ability = 0;
++ } else {
++ #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
++ support_ability = phydm_supportability_init_win(dm);
++ #elif (DM_ODM_SUPPORT_TYPE & (ODM_AP))
++ support_ability = phydm_supportability_init_ap(dm);
++ #elif(DM_ODM_SUPPORT_TYPE & (ODM_CE))
++ support_ability = phydm_supportability_init_ce(dm);
++ #elif(DM_ODM_SUPPORT_TYPE & (ODM_IOT))
++ support_ability = phydm_supportability_init_iot(dm);
++ #endif
++
++ /*@[Config Antenna Diversity]*/
++ if (IS_FUNC_EN(dm->enable_antdiv))
++ support_ability |= ODM_BB_ANT_DIV;
++
++ /*@[Config TXpath Diversity]*/
++ if (IS_FUNC_EN(dm->enable_pathdiv))
++ support_ability |= ODM_BB_PATH_DIV;
++
++ /*@[Config Adaptive SOML]*/
++ if (IS_FUNC_EN(dm->en_adap_soml))
++ support_ability |= ODM_BB_ADAPTIVE_SOML;
++
++ /* @[Config Adaptivity]*/
++ if (IS_FUNC_EN(dm->enable_adaptivity))
++ support_ability |= ODM_BB_ADAPTIVITY;
++ }
++ odm_cmn_info_init(dm, ODM_CMNINFO_ABILITY, support_ability);
++ PHYDM_DBG(dm, ODM_COMP_INIT, "IC=0x%x, mp=%d, Supportability=0x%llx\n",
++ dm->support_ic_type, *dm->mp_mode, dm->support_ability);
++}
++
++void phydm_rfe_init(void *dm_void)
++{
++ struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++ PHYDM_DBG(dm, ODM_COMP_INIT, "RFE_Init\n");
++#if (RTL8822B_SUPPORT == 1)
++ if (dm->support_ic_type == ODM_RTL8822B)
++ phydm_rfe_8822b_init(dm);
++#endif
++}
++
++void phydm_dm_early_init(struct dm_struct *dm)
++{
++
++}
++
++void odm_dm_init(struct dm_struct *dm)
++{
++ halrf_init(dm);
++ phydm_supportability_init(dm);
++ phydm_rfe_init(dm);
++ phydm_common_info_self_init(dm);
++ phydm_rx_phy_status_init(dm);
++#ifdef PHYDM_AUTO_DEGBUG
++ phydm_auto_dbg_engine_init(dm);
++#endif
++ phydm_dig_init(dm);
++#ifdef PHYDM_SUPPORT_CCKPD
++ phydm_cck_pd_init(dm);
++#endif
++ phydm_env_monitor_init(dm);
++ phydm_adaptivity_init(dm);
++ phydm_ra_info_init(dm);
++ phydm_rssi_monitor_init(dm);
++ phydm_cfo_tracking_init(dm);
++ phydm_rf_init(dm);
++ phydm_dc_cancellation(dm);
++#ifdef PHYDM_TXA_CALIBRATION
++ phydm_txcurrentcalibration(dm);
++ phydm_get_pa_bias_offset(dm);
++#endif
++#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
++ odm_antenna_diversity_init(dm);
++#endif
++#ifdef CONFIG_ADAPTIVE_SOML
++ phydm_adaptive_soml_init(dm);
++#endif
++#ifdef CONFIG_PATH_DIVERSITY
++ phydm_tx_path_diversity_init(dm);
++#endif
++#ifdef CONFIG_DYNAMIC_TX_TWR
++ phydm_dynamic_tx_power_init(dm);
++#endif
++#if (PHYDM_LA_MODE_SUPPORT == 1)
++ adc_smp_init(dm);
++#endif
++
++#ifdef PHYDM_BEAMFORMING_VERSION1
++ phydm_beamforming_init(dm);
++#endif
++
++#if (RTL8188E_SUPPORT == 1)
++ odm_ra_info_init_all(dm);
++#endif
++#ifdef PHYDM_PRIMARY_CCA
++ phydm_primary_cca_init(dm);
++#endif
++#ifdef CONFIG_PSD_TOOL
++ phydm_psd_init(dm);
++#endif
++
++#ifdef CONFIG_SMART_ANTENNA
++ phydm_smt_ant_init(dm);
++#endif
++#ifdef PHYDM_LNA_SAT_CHK_SUPPORT
++ phydm_lna_sat_check_init(dm);
++#endif
++#ifdef CONFIG_MCC_DM
++ #if (RTL8822B_SUPPORT == 1)
++ phydm_mcc_init(dm);
++ #endif
++#endif
++}
++
++void odm_dm_reset(struct dm_struct *dm)
++{
++ struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
++
++ #ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
++ odm_ant_div_reset(dm);
++ #endif
++ phydm_set_edcca_threshold_api(dm, dig_t->cur_ig_value);
++}
++
++void phydm_supportability_en(void *dm_void, char input[][16], u32 *_used,
++ char *output, u32 *_out_len)
++{
++ struct dm_struct *dm = (struct dm_struct *)dm_void;
++ u32 dm_value[10] = {0};
++ u64 pre_support_ability, one = 1;
++ u64 comp = 0;
++ u32 used = *_used;
++ u32 out_len = *_out_len;
++ u8 i;
++
++ for (i = 0; i < 5; i++) {
++ if (input[i + 1])
++ PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &dm_value[i]);
++ }
++
++ pre_support_ability = dm->support_ability;
++ comp = dm->support_ability;
++
++ PDM_SNPF(out_len, used, output + used, out_len - used,
++ "\n================================\n");
++
++ if (dm_value[0] == 100) {
++ PDM_SNPF(out_len, used, output + used, out_len - used,
++ "[Supportability] PhyDM Selection\n");
++ PDM_SNPF(out_len, used, output + used, out_len - used,
++ "================================\n");
++ PDM_SNPF(out_len, used, output + used, out_len - used,
++ "00. (( %s ))DIG\n",
++ ((comp & ODM_BB_DIG) ? ("V") : (".")));
++ PDM_SNPF(out_len, used, output + used, out_len - used,
++ "01. (( %s ))RA_MASK\n",
++ ((comp & ODM_BB_RA_MASK) ? ("V") : (".")));
++ PDM_SNPF(out_len, used, output + used, out_len - used,
++ "02. (( %s ))DYN_TXPWR\n",
++ ((comp & ODM_BB_DYNAMIC_TXPWR) ? ("V") : (".")));
++ PDM_SNPF(out_len, used, output + used, out_len - used,
++ "03. (( %s ))FA_CNT\n",
++ ((comp & ODM_BB_FA_CNT) ? ("V") : (".")));
++ PDM_SNPF(out_len, used, output + used, out_len - used,
++ "04. (( %s ))RSSI_MNTR\n",
++ ((comp & ODM_BB_RSSI_MONITOR) ? ("V") : (".")));
++ PDM_SNPF(out_len, used, output + used, out_len - used,
++ "05. (( %s ))CCK_PD\n",
++ ((comp & ODM_BB_CCK_PD) ? ("V") : (".")));
++ PDM_SNPF(out_len, used, output + used, out_len - used,
++ "06. (( %s ))ANT_DIV\n",
++ ((comp & ODM_BB_ANT_DIV) ? ("V") : (".")));
++ PDM_SNPF(out_len, used, output + used, out_len - used,
++ "07. (( %s ))SMT_ANT\n",
++ ((comp & ODM_BB_SMT_ANT) ? ("V") : (".")));
++ PDM_SNPF(out_len, used, output + used, out_len - used,
++ "08. (( %s ))PWR_TRAIN\n",
++ ((comp & ODM_BB_PWR_TRAIN) ? ("V") : (".")));
++ PDM_SNPF(out_len, used, output + used, out_len - used,
++ "09. (( %s ))RA\n",
++ ((comp & ODM_BB_RATE_ADAPTIVE) ? ("V") : (".")));
++ PDM_SNPF(out_len, used, output + used, out_len - used,
++ "10. (( %s ))PATH_DIV\n",
++ ((comp & ODM_BB_PATH_DIV) ? ("V") : (".")));
++ PDM_SNPF(out_len, used, output + used, out_len - used,
++ "11. (( %s ))DFS\n",
++ ((comp & ODM_BB_DFS) ? ("V") : (".")));
++ PDM_SNPF(out_len, used, output + used, out_len - used,
++ "12. (( %s ))DYN_ARFR\n",
++ ((comp & ODM_BB_DYNAMIC_ARFR) ? ("V") : (".")));
++ PDM_SNPF(out_len, used, output + used, out_len - used,
++ "13. (( %s ))ADAPTIVITY\n",
++ ((comp & ODM_BB_ADAPTIVITY) ? ("V") : (".")));
++ PDM_SNPF(out_len, used, output + used, out_len - used,
++ "14. (( %s ))CFO_TRACK\n",
++ ((comp & ODM_BB_CFO_TRACKING) ? ("V") : (".")));
++ PDM_SNPF(out_len, used, output + used, out_len - used,
++ "15. (( %s ))ENV_MONITOR\n",
++ ((comp & ODM_BB_ENV_MONITOR) ? ("V") : (".")));
++ PDM_SNPF(out_len, used, output + used, out_len - used,
++ "16. (( %s ))PRI_CCA\n",
++ ((comp & ODM_BB_PRIMARY_CCA) ? ("V") : (".")));
++ PDM_SNPF(out_len, used, output + used, out_len - used,
++ "17. (( %s ))ADPTV_SOML\n",
++ ((comp & ODM_BB_ADAPTIVE_SOML) ? ("V") : (".")));
++ PDM_SNPF(out_len, used, output + used, out_len - used,
++ "18. (( %s ))LNA_SAT_CHK\n",
++ ((comp & ODM_BB_LNA_SAT_CHK) ? ("V") : (".")));
++
++ PDM_SNPF(out_len, used, output + used, out_len - used,
++ "================================\n");
++ PDM_SNPF(out_len, used, output + used, out_len - used,
++ "[Supportability] PhyDM offload ability\n");
++ PDM_SNPF(out_len, used, output + used, out_len - used,
++ "================================\n");
++
++ PDM_SNPF(out_len, used, output + used, out_len - used,
++ "00. (( %s ))PHY PARAM OFFLOAD\n",
++ ((dm->fw_offload_ability & PHYDM_PHY_PARAM_OFFLOAD) ?
++ ("V") : (".")));
++ PDM_SNPF(out_len, used, output + used, out_len - used,
++ "01. (( %s ))RF IQK OFFLOAD\n",
++ ((dm->fw_offload_ability & PHYDM_RF_IQK_OFFLOAD) ?
++ ("V") : (".")));
++ PDM_SNPF(out_len, used, output + used, out_len - used,
++ "================================\n");
++
++ } else if (dm_value[0] == 101) {
++ dm->support_ability = 0;
++ PDM_SNPF(out_len, used, output + used, out_len - used,
++ "Disable all support_ability components\n");
++ } else {
++ if (dm_value[1] == 1) { /* @enable */
++ dm->support_ability |= (one << dm_value[0]);
++ } else if (dm_value[1] == 2) {/* @disable */
++ dm->support_ability &= ~(one << dm_value[0]);
++ } else {
++ PDM_SNPF(out_len, used, output + used, out_len - used,
++ "[Warning!!!] 1:enable, 2:disable\n");
++ }
++ }
++ PDM_SNPF(out_len, used, output + used, out_len - used,
++ "pre-supportability = 0x%llx\n", pre_support_ability);
++ PDM_SNPF(out_len, used, output + used, out_len - used,
++ "Cur-supportability = 0x%llx\n", dm->support_ability);
++ PDM_SNPF(out_len, used, output + used, out_len - used,
++ "================================\n");
++
++ *_used = used;
++ *_out_len = out_len;
++}
++
++void phydm_watchdog_lps_32k(struct dm_struct *dm)
++{
++ PHYDM_DBG(dm, DBG_COMMON_FLOW, "%s ======>\n", __func__);
++
++ phydm_common_info_self_update(dm);
++ phydm_rssi_monitor_check(dm);
++ phydm_dig_lps_32k(dm);
++ phydm_common_info_self_reset(dm);
++}
++
++void phydm_watchdog_lps(struct dm_struct *dm)
++{
++#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE | ODM_IOT))
++ PHYDM_DBG(dm, DBG_COMMON_FLOW, "%s ======>\n", __func__);
++
++ phydm_common_info_self_update(dm);
++ phydm_rssi_monitor_check(dm);
++ phydm_basic_dbg_message(dm);
++ phydm_receiver_blocking(dm);
++ phydm_false_alarm_counter_statistics(dm);
++ phydm_dig_by_rssi_lps(dm);
++ #ifdef PHYDM_SUPPORT_CCKPD
++ phydm_cck_pd_th(dm);
++ #endif
++ phydm_adaptivity(dm);
++ #if (DM_ODM_SUPPORT_TYPE & (ODM_CE))
++ #ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
++ /*@enable AntDiv in PS mode, request from SD4 Jeff*/
++ odm_antenna_diversity(dm);
++ #endif
++ #endif
++ phydm_common_info_self_reset(dm);
++#endif
++}
++
++void phydm_watchdog_mp(struct dm_struct *dm)
++{
++}
++
++void phydm_pause_dm_watchdog(void *dm_void, enum phydm_pause_type pause_type)
++{
++ struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++ if (pause_type == PHYDM_PAUSE) {
++ dm->disable_phydm_watchdog = 1;
++ PHYDM_DBG(dm, ODM_COMP_API, "PHYDM Stop\n");
++ } else {
++ dm->disable_phydm_watchdog = 0;
++ PHYDM_DBG(dm, ODM_COMP_API, "PHYDM Start\n");
++ }
++}
++
++u8 phydm_pause_func(void *dm_void, enum phydm_func_idx pause_func,
++ enum phydm_pause_type pause_type,
++ enum phydm_pause_level pause_lv, u8 val_lehgth,
++ u32 *val_buf)
++{
++ struct dm_struct *dm = (struct dm_struct *)dm_void;
++ struct phydm_func_poiner *func_t = &dm->phydm_func_handler;
++ s8 *pause_lv_pre = &dm->s8_dummy;
++ u32 *bkp_val = &dm->u32_dummy;
++ u32 ori_val[5] = {0};
++ u64 pause_func_bitmap = (u64)BIT(pause_func);
++ u8 i = 0;
++ u8 en_2rcca = 0;
++ u8 en_bw40m = 0;
++ u8 pause_result = PAUSE_FAIL;
++
++ PHYDM_DBG(dm, ODM_COMP_API, "\n");
++ PHYDM_DBG(dm, ODM_COMP_API, "[%s][%s] LV=%d, Len=%d\n", __func__,
++ ((pause_type == PHYDM_PAUSE) ? "Pause" :
++ ((pause_type == PHYDM_RESUME) ? "Resume" : "Pause no_set")),
++ pause_lv, val_lehgth);
++
++ if (pause_lv >= PHYDM_PAUSE_MAX_NUM) {
++ PHYDM_DBG(dm, ODM_COMP_API, "[WARNING]Wrong LV=%d\n", pause_lv);
++ return PAUSE_FAIL;
++ }
++
++ if (pause_func == F00_DIG) {
++ PHYDM_DBG(dm, ODM_COMP_API, "[DIG]\n");
++
++ if (val_lehgth != 1) {
++ PHYDM_DBG(dm, ODM_COMP_API, "[WARNING] length != 1\n");
++ return PAUSE_FAIL;
++ }
++
++ ori_val[0] = (u32)(dm->dm_dig_table.cur_ig_value);
++ pause_lv_pre = &dm->pause_lv_table.lv_dig;
++ bkp_val = (u32 *)(&dm->dm_dig_table.rvrt_val);
++ /*@function pointer hook*/
++ func_t->pause_phydm_handler = phydm_set_dig_val;
++
++#ifdef PHYDM_SUPPORT_CCKPD
++ } else if (pause_func == F05_CCK_PD) {
++ PHYDM_DBG(dm, ODM_COMP_API, "[CCK_PD]\n");
++
++ if (val_lehgth != 1) {
++ PHYDM_DBG(dm, ODM_COMP_API, "[WARNING] length != 1\n");
++ return PAUSE_FAIL;
++ }
++
++ ori_val[0] = (u32)dm->dm_cckpd_table.cck_pd_lv;
++ pause_lv_pre = &dm->pause_lv_table.lv_cckpd;
++ bkp_val = (u32 *)(&dm->dm_cckpd_table.rvrt_val);
++ /*@function pointer hook*/
++ func_t->pause_phydm_handler = phydm_set_cckpd_val;
++#endif
++
++#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
++ } else if (pause_func == F06_ANT_DIV) {
++ PHYDM_DBG(dm, ODM_COMP_API, "[AntDiv]\n");
++
++ if (val_lehgth != 1) {
++ PHYDM_DBG(dm, ODM_COMP_API, "[WARNING] length != 1\n");
++ return PAUSE_FAIL;
++ }
++ /*@default antenna*/
++ ori_val[0] = (u32)(dm->dm_fat_table.rx_idle_ant);
++ pause_lv_pre = &dm->pause_lv_table.lv_antdiv;
++ bkp_val = (u32 *)(&dm->dm_fat_table.rvrt_val);
++ /*@function pointer hook*/
++ func_t->pause_phydm_handler = phydm_set_antdiv_val;
++
++#endif
++#ifdef PHYDM_SUPPORT_ADAPTIVITY
++ } else if (pause_func == F13_ADPTVTY) {
++ PHYDM_DBG(dm, ODM_COMP_API, "[Adaptivity]\n");
++
++ if (val_lehgth != 2) {
++ PHYDM_DBG(dm, ODM_COMP_API, "[WARNING] length != 2\n");
++ return PAUSE_FAIL;
++ }
++
++ ori_val[0] = (u32)(dm->adaptivity.th_l2h); /*th_l2h*/
++ ori_val[1] = (u32)(dm->adaptivity.th_h2l); /*th_h2l*/
++ pause_lv_pre = &dm->pause_lv_table.lv_adapt;
++ bkp_val = (u32 *)(&dm->adaptivity.rvrt_val);
++ /*@function pointer hook*/
++ func_t->pause_phydm_handler = phydm_set_edcca_val;
++
++#endif
++#ifdef CONFIG_ADAPTIVE_SOML
++ } else if (pause_func == F17_ADPTV_SOML) {
++ PHYDM_DBG(dm, ODM_COMP_API, "[AD-SOML]\n");
++
++ if (val_lehgth != 1) {
++ PHYDM_DBG(dm, ODM_COMP_API, "[WARNING] length != 1\n");
++ return PAUSE_FAIL;
++ }
++ /*SOML_ON/OFF*/
++ ori_val[0] = (u32)(dm->dm_soml_table.soml_on_off);
++
++ pause_lv_pre = &dm->pause_lv_table.lv_adsl;
++ bkp_val = (u32 *)(&dm->dm_soml_table.rvrt_val);
++ /*@function pointer hook*/
++ func_t->pause_phydm_handler = phydm_set_adsl_val;
++
++#endif
++ } else {
++ PHYDM_DBG(dm, ODM_COMP_API, "[WARNING] error func idx\n");
++ return PAUSE_FAIL;
++ }
++
++ PHYDM_DBG(dm, ODM_COMP_API, "Pause_LV{new , pre} = {%d ,%d}\n",
++ pause_lv, *pause_lv_pre);
++
++ if (pause_type == PHYDM_PAUSE || pause_type == PHYDM_PAUSE_NO_SET) {
++ if (pause_lv <= *pause_lv_pre) {
++ PHYDM_DBG(dm, ODM_COMP_API,
++ "[PAUSE FAIL] Pre_LV >= Curr_LV\n");
++ return PAUSE_FAIL;
++ }
++
++ if (!(dm->pause_ability & pause_func_bitmap)) {
++ for (i = 0; i < val_lehgth; i++)
++ bkp_val[i] = ori_val[i];
++ }
++
++ dm->pause_ability |= pause_func_bitmap;
++ PHYDM_DBG(dm, ODM_COMP_API, "pause_ability=0x%llx\n",
++ dm->pause_ability);
++
++ if (pause_type == PHYDM_PAUSE) {
++ for (i = 0; i < val_lehgth; i++)
++ PHYDM_DBG(dm, ODM_COMP_API,
++ "[PAUSE SUCCESS] val_idx[%d]{New, Ori}={0x%x, 0x%x}\n",
++ i, val_buf[i], bkp_val[i]);
++ func_t->pause_phydm_handler(dm, val_buf, val_lehgth);
++ } else {
++ for (i = 0; i < val_lehgth; i++)
++ PHYDM_DBG(dm, ODM_COMP_API,
++ "[PAUSE NO Set: SUCCESS] val_idx[%d]{Ori}={0x%x}\n",
++ i, bkp_val[i]);
++ }
++
++ *pause_lv_pre = pause_lv;
++ pause_result = PAUSE_SUCCESS;
++
++ } else if (pause_type == PHYDM_RESUME) {
++ if ((dm->pause_ability & pause_func_bitmap) == 0) {
++ PHYDM_DBG(dm, ODM_COMP_API,
++ "[RESUME] No Need to Revert\n");
++ return PAUSE_SUCCESS;
++ }
++
++ dm->pause_ability &= ~pause_func_bitmap;
++ PHYDM_DBG(dm, ODM_COMP_API, "pause_ability=0x%llx\n",
++ dm->pause_ability);
++
++ *pause_lv_pre = PHYDM_PAUSE_RELEASE;
++
++ for (i = 0; i < val_lehgth; i++) {
++ PHYDM_DBG(dm, ODM_COMP_API,
++ "[RESUME] val_idx[%d]={0x%x}\n", i,
++ bkp_val[i]);
++ }
++
++ func_t->pause_phydm_handler(dm, bkp_val, val_lehgth);
++
++ pause_result = PAUSE_SUCCESS;
++ } else {
++ PHYDM_DBG(dm, ODM_COMP_API, "[WARNING] error pause_type\n");
++ pause_result = PAUSE_FAIL;
++ }
++ return pause_result;
++}
++
++void phydm_pause_func_console(void *dm_void, char input[][16], u32 *_used,
++ char *output, u32 *_out_len)
++{
++ struct dm_struct *dm = (struct dm_struct *)dm_void;
++ char help[] = "-h";
++ u32 var1[10] = {0};
++ u32 used = *_used;
++ u32 out_len = *_out_len;
++ u32 i;
++ u8 length = 0;
++ u32 buf[5] = {0};
++ u8 set_result = 0;
++ enum phydm_func_idx func = 0;
++ enum phydm_pause_type type = 0;
++ enum phydm_pause_level lv = 0;
++
++ if ((strcmp(input[1], help) == 0)) {
++ PDM_SNPF(out_len, used, output + used, out_len - used,
++ "{Func} {1:pause,2:pause no set 3:Resume} {lv:0~3} Val[5:0]\n");
++
++ goto out;
++ }
++
++ for (i = 0; i < 10; i++) {
++ if (input[i + 1])
++ PHYDM_SSCANF(input[i + 1], DCMD_HEX, &var1[i]);
++ }
++
++ func = (enum phydm_func_idx)var1[0];
++ type = (enum phydm_pause_type)var1[1];
++ lv = (enum phydm_pause_level)var1[2];
++
++ for (i = 0; i < 5; i++)
++ buf[i] = var1[3 + i];
++
++ if (func == F00_DIG) {
++ PDM_SNPF(out_len, used, output + used, out_len - used,
++ "[DIG]\n");
++ length = 1;
++
++ } else if (func == F05_CCK_PD) {
++ PDM_SNPF(out_len, used, output + used, out_len - used,
++ "[CCK_PD]\n");
++ length = 1;
++ } else if (func == F06_ANT_DIV) {
++ PDM_SNPF(out_len, used, output + used, out_len - used,
++ "[Ant_Div]\n");
++ length = 1;
++ } else if (func == F13_ADPTVTY) {
++ PDM_SNPF(out_len, used, output + used, out_len - used,
++ "[Adaptivity]\n");
++ length = 2;
++ } else if (func == F17_ADPTV_SOML) {
++ PDM_SNPF(out_len, used, output + used, out_len - used,
++ "[ADSL]\n");
++ length = 1;
++ } else {
++ PDM_SNPF(out_len, used, output + used, out_len - used,
++ "[Set Function Error]\n");
++ length = 0;
++ }
++
++ if (length != 0) {
++ PDM_SNPF(out_len, used, output + used, out_len - used,
++ "{%s, lv=%d} val = %d, %d}\n",
++ ((type == PHYDM_PAUSE) ? "Pause" :
++ ((type == PHYDM_RESUME) ? "Resume" : "Pause no_set")),
++ lv, var1[3], var1[4]);
++
++ set_result = phydm_pause_func(dm, func, type, lv, length, buf);
++ }
++
++ PDM_SNPF(out_len, used, output + used, out_len - used,
++ "set_result = %d\n", set_result);
++
++out:
++ *_used = used;
++ *_out_len = out_len;
++}
++
++u8 phydm_stop_dm_watchdog_check(void *dm_void)
++{
++ struct dm_struct *dm = (struct dm_struct *)dm_void;
++
++ if (dm->disable_phydm_watchdog == 1) {
++ PHYDM_DBG(dm, DBG_COMMON_FLOW, "Disable phydm\n");
++ return true;
++ } else {
++ return false;
++ }
++}
++
++void phydm_watchdog(struct dm_struct *dm)
++{
++ PHYDM_DBG(dm, DBG_COMMON_FLOW, "%s ======>\n", __func__);
++
++ phydm_common_info_self_update(dm);
++ phydm_phy_info_update(dm);
++ phydm_rssi_monitor_check(dm);
++ phydm_basic_dbg_message(dm);
++ phydm_dm_summary(dm, FIRST_MACID);
++#ifdef PHYDM_AUTO_DEGBUG
++ phydm_auto_dbg_engine(dm);
++#endif
++ phydm_receiver_blocking(dm);
++
++ if (phydm_stop_dm_watchdog_check(dm) == true)
++ return;
++
++ phydm_hw_setting(dm);
++
++ #ifdef PHYDM_TDMA_DIG_SUPPORT
++ if (dm->original_dig_restore == 0)
++ phydm_tdma_dig_timer_check(dm);
++ else
++ #endif
++ {
++ phydm_false_alarm_counter_statistics(dm);
++ phydm_noisy_detection(dm);
++ phydm_dig(dm);
++ #ifdef PHYDM_SUPPORT_CCKPD
++ phydm_cck_pd_th(dm);
++ #endif
++ }
++
++#ifdef PHYDM_POWER_TRAINING_SUPPORT
++ phydm_update_power_training_state(dm);
++#endif
++ phydm_adaptivity(dm);
++ phydm_ra_info_watchdog(dm);
++#ifdef CONFIG_PATH_DIVERSITY
++ phydm_tx_path_diversity(dm);
++#endif
++ phydm_cfo_tracking(dm);
++#ifdef CONFIG_DYNAMIC_TX_TWR
++ phydm_dynamic_tx_power(dm);
++#endif
++#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
++ odm_antenna_diversity(dm);
++#endif
++#ifdef CONFIG_ADAPTIVE_SOML
++ phydm_adaptive_soml(dm);
++#endif
++
++#ifdef PHYDM_BEAMFORMING_VERSION1
++ phydm_beamforming_watchdog(dm);
++#endif
++
++ halrf_watchdog(dm);
++#ifdef PHYDM_PRIMARY_CCA
++ phydm_primary_cca(dm);
++#endif
++#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
++ odm_dtc(dm);
++#endif
++
++ phydm_env_mntr_watchdog(dm);
++
++#ifdef PHYDM_LNA_SAT_CHK_SUPPORT
++ phydm_lna_sat_chk_watchdog(dm);
++#endif
++#ifdef CONFIG_MCC_DM
++ #if (RTL8822B_SUPPORT == 1)
++ phydm_mcc_switch(dm);
++ #endif
++#endif
++ phydm_common_info_self_reset(dm);
++}
++
++/*@
++ * Init /.. Fixed HW value. Only init time.
++ */
++void odm_cmn_info_init(struct dm_struct *dm, enum odm_cmninfo cmn_info,
++ u64 value)
++{
++ /* This section is used for init value */
++ switch (cmn_info) {
++ /* @Fixed ODM value. */
++ case ODM_CMNINFO_ABILITY:
++ dm->support_ability = (u64)value;
++ break;
++
++ case ODM_CMNINFO_RF_TYPE:
++ dm->rf_type = (u8)value;
++ break;
++
++ case ODM_CMNINFO_PLATFORM:
++ dm->support_platform = (u8)value;
++ break;
++
++ case ODM_CMNINFO_INTERFACE:
++ dm->support_interface = (u8)value;
++ break;
++
++ case ODM_CMNINFO_IC_TYPE:
++ dm->support_ic_type = (u32)value;
++ break;
++
++ case ODM_CMNINFO_CUT_VER:
++ dm->cut_version = (u8)value;
++ break;
++
++ case ODM_CMNINFO_FAB_VER:
++ dm->fab_version = (u8)value;
++ break;
++ case ODM_CMNINFO_FW_VER:
++ dm->fw_version = (u8)value;
++ break;
++ case ODM_CMNINFO_FW_SUB_VER:
++ dm->fw_sub_version = (u8)value;
++ break;
++ case ODM_CMNINFO_RFE_TYPE:
++#if (RTL8821C_SUPPORT == 1)
++ if (dm->support_ic_type & ODM_RTL8821C)
++ dm->rfe_type_expand = (u8)value;
++ else
++#endif
++ dm->rfe_type = (u8)value;
++ phydm_init_hw_info_by_rfe(dm);
++ break;
++
++ case ODM_CMNINFO_RF_ANTENNA_TYPE:
++ dm->ant_div_type = (u8)value;
++ break;
++
++ case ODM_CMNINFO_WITH_EXT_ANTENNA_SWITCH:
++ dm->with_extenal_ant_switch = (u8)value;
++ break;
++
++#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
++ case ODM_CMNINFO_BE_FIX_TX_ANT:
++ dm->dm_fat_table.b_fix_tx_ant = (u8)value;
++ break;
++#endif
++
++ case ODM_CMNINFO_BOARD_TYPE:
++ if (!dm->is_init_hw_info_by_rfe)
++ dm->board_type = (u8)value;
++ break;
++
++ case ODM_CMNINFO_PACKAGE_TYPE:
++ if (!dm->is_init_hw_info_by_rfe)
++ dm->package_type = (u8)value;
++ break;
++
++ case ODM_CMNINFO_EXT_LNA:
++ if (!dm->is_init_hw_info_by_rfe)
++ dm->ext_lna = (u8)value;
++ break;
++
++ case ODM_CMNINFO_5G_EXT_LNA:
++ if (!dm->is_init_hw_info_by_rfe)
++ dm->ext_lna_5g = (u8)value;
++ break;
++
++ case ODM_CMNINFO_EXT_PA:
++ if (!dm->is_init_hw_info_by_rfe)
++ dm->ext_pa = (u8)value;
++ break;
++
++ case ODM_CMNINFO_5G_EXT_PA:
++ if (!dm->is_init_hw_info_by_rfe)
++ dm->ext_pa_5g = (u8)value;
++ break;
++
++ case ODM_CMNINFO_GPA:
++ if (!dm->is_init_hw_info_by_rfe)
++ dm->type_gpa = (u16)value;
++ break;
++
++ case ODM_CMNINFO_APA:
++ if (!dm->is_init_hw_info_by_rfe)
++ dm->type_apa = (u16)value;
++ break;
++
++ case ODM_CMNINFO_GLNA:
++ if (!dm->is_init_hw_info_by_rfe)
++ dm->type_glna = (u16)value;
++ break;
++
++ case ODM_CMNINFO_ALNA:
++ if (!dm->is_init_hw_info_by_rfe)
++ dm->type_alna = (u16)value;
++ break;
++
++ case ODM_CMNINFO_EXT_TRSW:
++ if (!dm->is_init_hw_info_by_rfe)
++ dm->ext_trsw = (u8)value;
++ break;
++ case ODM_CMNINFO_EXT_LNA_GAIN:
++ dm->ext_lna_gain = (u8)value;
++ break;
++ case ODM_CMNINFO_PATCH_ID:
++ dm->iot_table.win_patch_id = (u8)value;
++ break;
++ case ODM_CMNINFO_BINHCT_TEST:
++ dm->is_in_hct_test = (boolean)value;
++ break;
++ case ODM_CMNINFO_BWIFI_TEST:
++ dm->wifi_test = (u8)value;
++ break;
++ case ODM_CMNINFO_SMART_CONCURRENT:
++ dm->is_dual_mac_smart_concurrent = (boolean)value;
++ break;
++#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
++ case ODM_CMNINFO_CONFIG_BB_RF:
++ dm->config_bbrf = (boolean)value;
++ break;
++#endif
++ case ODM_CMNINFO_IQKPAOFF:
++ dm->rf_calibrate_info.is_iqk_pa_off = (boolean)value;
++ break;
++ case ODM_CMNINFO_REGRFKFREEENABLE:
++ dm->rf_calibrate_info.reg_rf_kfree_enable = (u8)value;
++ break;
++ case ODM_CMNINFO_RFKFREEENABLE:
++ dm->rf_calibrate_info.rf_kfree_enable = (u8)value;
++ break;
++ case ODM_CMNINFO_NORMAL_RX_PATH_CHANGE:
++ dm->normal_rx_path = (u8)value;
++ break;
++ case ODM_CMNINFO_EFUSE0X3D8:
++ dm->efuse0x3d8 = (u8)value;
++ break;
++ case ODM_CMNINFO_EFUSE0X3D7:
++ dm->efuse0x3d7 = (u8)value;
++ break;
++ case ODM_CMNINFO_ADVANCE_OTA:
++ dm->p_advance_ota = (u8)value;
++ break;
++
++#ifdef CONFIG_PHYDM_DFS_MASTER
++ case ODM_CMNINFO_DFS_REGION_DOMAIN:
++ dm->dfs_region_domain = (u8)value;
++ break;
++#endif
++ case ODM_CMNINFO_SOFT_AP_SPECIAL_SETTING:
++ dm->soft_ap_special_setting = (u32)value;
++ break;
++
++ case ODM_CMNINFO_X_CAP_SETTING:
++ dm->dm_cfo_track.crystal_cap_default = (u8)value;
++ break;
++
++ case ODM_CMNINFO_DPK_EN:
++ /*@dm->dpk_en = (u1Byte)value;*/
++ halrf_cmn_info_set(dm, HALRF_CMNINFO_DPK_EN, (u64)value);
++ break;
++
++ case ODM_CMNINFO_HP_HWID:
++ dm->hp_hw_id = (boolean)value;
++ break;
++ default:
++ break;
++ }
++}
++
++void odm_cmn_info_hook(struct dm_struct *dm, enum odm_cmninfo cmn_info,
++ void *value)
++{
++ /* @Hook call by reference pointer. */
++ switch (cmn_info) {
++ /* @Dynamic call by reference pointer. */
++ case ODM_CMNINFO_TX_UNI:
++ dm->num_tx_bytes_unicast = (u64 *)value;
++ break;
++
++ case ODM_CMNINFO_RX_UNI:
++ dm->num_rx_bytes_unicast = (u64 *)value;
++ break;
++
++ case ODM_CMNINFO_BAND:
++ dm->band_type = (u8 *)value;
++ break;
++
++ case ODM_CMNINFO_SEC_CHNL_OFFSET:
++ dm->sec_ch_offset = (u8 *)value;
++ break;
++
++ case ODM_CMNINFO_SEC_MODE:
++ dm->security = (u8 *)value;
++ break;
++
++ case ODM_CMNINFO_BW:
++ dm->band_width = (u8 *)value;
++ break;
++
++ case ODM_CMNINFO_CHNL:
++ dm->channel = (u8 *)value;
++ break;
++
++ case ODM_CMNINFO_SCAN:
++ dm->is_scan_in_process = (boolean *)value;
++ break;
++
++ case ODM_CMNINFO_POWER_SAVING:
++ dm->is_power_saving = (boolean *)value;
++ break;
++
++ case ODM_CMNINFO_TDMA:
++ dm->is_tdma = (boolean *)value;
++ break;
++
++ case ODM_CMNINFO_ONE_PATH_CCA:
++ dm->one_path_cca = (u8 *)value;
++ break;
++
++ case ODM_CMNINFO_DRV_STOP:
++ dm->is_driver_stopped = (boolean *)value;
++ break;
++ case ODM_CMNINFO_INIT_ON:
++ dm->pinit_adpt_in_progress = (boolean *)value;
++ break;
++
++ case ODM_CMNINFO_ANT_TEST:
++ dm->antenna_test = (u8 *)value;
++ break;
++
++ case ODM_CMNINFO_NET_CLOSED:
++ dm->is_net_closed = (boolean *)value;
++ break;
++
++ case ODM_CMNINFO_FORCED_RATE:
++ dm->forced_data_rate = (u16 *)value;
++ break;
++ case ODM_CMNINFO_ANT_DIV:
++ dm->enable_antdiv = (u8 *)value;
++ break;
++ case ODM_CMNINFO_PATH_DIV:
++ dm->enable_pathdiv = (u8 *)value;
++ break;
++ case ODM_CMNINFO_ADAPTIVE_SOML:
++ dm->en_adap_soml = (u8 *)value;
++ break;
++ case ODM_CMNINFO_ADAPTIVITY:
++ dm->enable_adaptivity = (u8 *)value;
++ break;
++
++ case ODM_CMNINFO_P2P_LINK:
++ dm->dm_dig_table.is_p2p_in_process = (u8 *)value;
++ break;
++
++ case ODM_CMNINFO_IS1ANTENNA:
++ dm->is_1_antenna = (boolean *)value;
++ break;
++
++ case ODM_CMNINFO_RFDEFAULTPATH:
++ dm->rf_default_path = (u8 *)value;
++ break;
++
++ case ODM_CMNINFO_FCS_MODE:
++ dm->is_fcs_mode_enable = (boolean *)value;
++ break;
++
++ case ODM_CMNINFO_HUBUSBMODE:
++ dm->hub_usb_mode = (u8 *)value;
++ break;
++ case ODM_CMNINFO_FWDWRSVDPAGEINPROGRESS:
++ dm->is_fw_dw_rsvd_page_in_progress = (boolean *)value;
++ break;
++ case ODM_CMNINFO_TX_TP:
++ dm->current_tx_tp = (u32 *)value;
++ break;
++ case ODM_CMNINFO_RX_TP:
++ dm->current_rx_tp = (u32 *)value;
++ break;
++ case ODM_CMNINFO_SOUNDING_SEQ:
++ dm->sounding_seq = (u8 *)value;
++ break;
++#ifdef CONFIG_PHYDM_DFS_MASTER
++ case ODM_CMNINFO_DFS_MASTER_ENABLE:
++ dm->dfs_master_enabled = (u8 *)value;
++ break;
++#endif
++
++#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
++ case ODM_CMNINFO_FORCE_TX_ANT_BY_TXDESC:
++ dm->dm_fat_table.p_force_tx_by_desc = (u8 *)value;
++ break;
++ case ODM_CMNINFO_SET_S0S1_DEFAULT_ANTENNA:
++ dm->dm_fat_table.p_default_s0_s1 = (u8 *)value;
++ break;
++ case ODM_CMNINFO_BF_ANTDIV_DECISION:
++ dm->dm_fat_table.is_no_csi_feedback = (boolean *)value;
++ break;
++#endif
++
++ case ODM_CMNINFO_SOFT_AP_MODE:
++ dm->soft_ap_mode = (u32 *)value;
++ break;
++ case ODM_CMNINFO_MP_MODE:
++ dm->mp_mode = (u8 *)value;
++ break;
++ case ODM_CMNINFO_INTERRUPT_MASK:
++ dm->interrupt_mask = (u32 *)value;
++ break;
++ case ODM_CMNINFO_BB_OPERATION_MODE:
++ dm->bb_op_mode = (u8 *)value;
++ break;
++ default:
++ /*do nothing*/
++ break;
++ }
++}
++
++/*@
++ * Update band/CHannel/.. The values are dynamic but non-per-packet.
++ */
++void odm_cmn_info_update(struct dm_struct *dm, u32 cmn_info, u64 value)
++{
++ /* This init variable may be changed in run time. */
++ switch (cmn_info) {
++ case ODM_CMNINFO_LINK_IN_PROGRESS:
++ dm->is_link_in_process = (boolean)value;
++ break;
++
++ case ODM_CMNINFO_ABILITY:
++ dm->support_ability = (u64)value;
++ break;
++
++ case ODM_CMNINFO_RF_TYPE:
++ dm->rf_type = (u8)value;
++ break;
++
++ case ODM_CMNINFO_WIFI_DIRECT:
++ dm->is_wifi_direct = (boolean)value;
++ break;
++
++ case ODM_CMNINFO_WIFI_DISPLAY:
++ dm->is_wifi_display = (boolean)value;
++ break;
++
++ case ODM_CMNINFO_LINK:
++ dm->is_linked = (boolean)value;
++ break;
++
++ case ODM_CMNINFO_CMW500LINK:
++ dm->iot_table.is_linked_cmw500 = (boolean)value;
++ break;
++
++ case ODM_CMNINFO_STATION_STATE:
++ dm->bsta_state = (boolean)value;
++ break;
++
++ case ODM_CMNINFO_RSSI_MIN:
++ dm->rssi_min = (u8)value;
++ break;
++
++ case ODM_CMNINFO_RSSI_MIN_BY_PATH:
++ dm->rssi_min_by_path = (u8)value;
++ break;
++
++ case ODM_CMNINFO_DBG_COMP:
++ dm->debug_components = (u64)value;
++ break;
++
++#ifdef ODM_CONFIG_BT_COEXIST
++ /* The following is for BT HS mode and BT coexist mechanism. */
++ case ODM_CMNINFO_BT_ENABLED:
++ dm->bt_info_table.is_bt_enabled = (boolean)value;
++ break;
++
++ case ODM_CMNINFO_BT_HS_CONNECT_PROCESS:
++ dm->bt_info_table.is_bt_connect_process = (boolean)value;
++ break;
++
++ case ODM_CMNINFO_BT_HS_RSSI:
++ dm->bt_info_table.bt_hs_rssi = (u8)value;
++ break;
++
++ case ODM_CMNINFO_BT_OPERATION:
++ dm->bt_info_table.is_bt_hs_operation = (boolean)value;
++ break;
++
++ case ODM_CMNINFO_BT_LIMITED_DIG:
++ dm->bt_info_table.is_bt_limited_dig = (boolean)value;
++ break;
++#endif
++
++ case ODM_CMNINFO_AP_TOTAL_NUM:
++ dm->ap_total_num = (u8)value;
++ break;
++
++#ifdef CONFIG_PHYDM_DFS_MASTER
++ case ODM_CMNINFO_DFS_REGION_DOMAIN:
++ dm->dfs_region_domain = (u8)value;
++ break;
++#endif
++
++ case ODM_CMNINFO_BT_CONTINUOUS_TURN:
++ dm->is_bt_continuous_turn = (boolean)value;
++ break;
++ default:
++ break;
++ }
++}
++
++u32 phydm_cmn_info_query(struct dm_struct *dm, enum phydm_info_query info_type)
++{
++ struct phydm_fa_struct *fa_t = &dm->false_alm_cnt;
++ struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
++ struct ccx_info *ccx_info = &dm->dm_ccx_info;
++
++ switch (info_type) {
++ /*@=== [FA Relative] ===========================================*/
++ case PHYDM_INFO_FA_OFDM:
++ return fa_t->cnt_ofdm_fail;
++
++ case PHYDM_INFO_FA_CCK:
++ return fa_t->cnt_cck_fail;
++
++ case PHYDM_INFO_FA_TOTAL:
++ return fa_t->cnt_all;
++
++ case PHYDM_INFO_CCA_OFDM:
++ return fa_t->cnt_ofdm_cca;
++
++ case PHYDM_INFO_CCA_CCK:
++ return fa_t->cnt_cck_cca;
++
++ case PHYDM_INFO_CCA_ALL:
++ return fa_t->cnt_cca_all;
++
++ case PHYDM_INFO_CRC32_OK_VHT:
++ return fa_t->cnt_vht_crc32_ok;
++
++ case PHYDM_INFO_CRC32_OK_HT:
++ return fa_t->cnt_ht_crc32_ok;
++
++ case PHYDM_INFO_CRC32_OK_LEGACY:
++ return fa_t->cnt_ofdm_crc32_ok;
++
++ case PHYDM_INFO_CRC32_OK_CCK:
++ return fa_t->cnt_cck_crc32_ok;
++
++ case PHYDM_INFO_CRC32_ERROR_VHT:
++ return fa_t->cnt_vht_crc32_error;
++
++ case PHYDM_INFO_CRC32_ERROR_HT:
++ return fa_t->cnt_ht_crc32_error;
++
++ case PHYDM_INFO_CRC32_ERROR_LEGACY:
++ return fa_t->cnt_ofdm_crc32_error;
++
++ case PHYDM_INFO_CRC32_ERROR_CCK:
++ return fa_t->cnt_cck_crc32_error;
++
++ case PHYDM_INFO_EDCCA_FLAG:
++ return fa_t->edcca_flag;
++
++ case PHYDM_INFO_OFDM_ENABLE:
++ return fa_t->ofdm_block_enable;
++
++ case PHYDM_INFO_CCK_ENABLE:
++ return fa_t->cck_block_enable;
++
++ case PHYDM_INFO_DBG_PORT_0:
++ return fa_t->dbg_port0;
++
++ case PHYDM_INFO_CRC32_OK_HT_AGG:
++ return fa_t->cnt_ht_crc32_ok_agg;
++
++ case PHYDM_INFO_CRC32_ERROR_HT_AGG:
++ return fa_t->cnt_ht_crc32_error_agg;
++
++ /*@=== [DIG] ================================================*/
++
++ case PHYDM_INFO_CURR_IGI:
++ return dig_t->cur_ig_value;
++
++ /*@=== [RSSI] ===============================================*/
++ case PHYDM_INFO_RSSI_MIN:
++ return (u32)dm->rssi_min;
++
++ case PHYDM_INFO_RSSI_MAX:
++ return (u32)dm->rssi_max;
++
++ case PHYDM_INFO_CLM_RATIO:
++ return (u32)ccx_info->clm_ratio;
++ case PHYDM_INFO_NHM_RATIO:
++ return (u32)ccx_info->nhm_ratio;
++ default:
++ return 0xffffffff;
++ }
++}
++
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++void odm_init_all_work_items(struct dm_struct *dm)
++{
++ void *adapter = dm->adapter;
++#if USE_WORKITEM
++
++#ifdef CONFIG_ADAPTIVE_SOML
++ odm_initialize_work_item(dm,
++ &dm->dm_soml_table.phydm_adaptive_soml_workitem,
++ (RT_WORKITEM_CALL_BACK)phydm_adaptive_soml_workitem_callback,
++ (void *)adapter,
++ "AdaptiveSOMLWorkitem");
++#endif
++
++#ifdef ODM_EVM_ENHANCE_ANTDIV
++ odm_initialize_work_item(dm,
++ &dm->phydm_evm_antdiv_workitem,
++ (RT_WORKITEM_CALL_BACK)phydm_evm_antdiv_workitem_callback,
++ (void *)adapter,
++ "EvmAntdivWorkitem");
++#endif
++
++#ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY
++ odm_initialize_work_item(dm,
++ &dm->dm_swat_table.phydm_sw_antenna_switch_workitem,
++ (RT_WORKITEM_CALL_BACK)odm_sw_antdiv_workitem_callback,
++ (void *)adapter,
++ "AntennaSwitchWorkitem");
++#endif
++#if (defined(CONFIG_HL_SMART_ANTENNA))
++ odm_initialize_work_item(dm,
++ &dm->dm_sat_table.hl_smart_antenna_workitem,
++ (RT_WORKITEM_CALL_BACK)phydm_beam_switch_workitem_callback,
++ (void *)adapter,
++ "hl_smart_ant_workitem");
++
++ odm_initialize_work_item(dm,
++ &dm->dm_sat_table.hl_smart_antenna_decision_workitem,
++ (RT_WORKITEM_CALL_BACK)phydm_beam_decision_workitem_callback,
++ (void *)adapter,
++ "hl_smart_ant_decision_workitem");
++#endif
++
++ odm_initialize_work_item(
++ dm,
++ &dm->ra_rpt_workitem,
++ (RT_WORKITEM_CALL_BACK)halrf_update_init_rate_work_item_callback,
++ (void *)adapter,
++ "ra_rpt_workitem");
++
++#if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))
++ odm_initialize_work_item(
++ dm,
++ &dm->fast_ant_training_workitem,
++ (RT_WORKITEM_CALL_BACK)odm_fast_ant_training_work_item_callback,
++ (void *)adapter,
++ "fast_ant_training_workitem");
++#endif
++
++#endif /*#if USE_WORKITEM*/
++
++#ifdef PHYDM_BEAMFORMING_SUPPORT
++ odm_initialize_work_item(
++ dm,
++ &dm->beamforming_info.txbf_info.txbf_enter_work_item,
++ (RT_WORKITEM_CALL_BACK)hal_com_txbf_enter_work_item_callback,
++ (void *)adapter,
++ "txbf_enter_work_item");
++
++ odm_initialize_work_item(
++ dm,
++ &dm->beamforming_info.txbf_info.txbf_leave_work_item,
++ (RT_WORKITEM_CALL_BACK)hal_com_txbf_leave_work_item_callback,
++ (void *)adapter,
++ "txbf_leave_work_item");
++
++ odm_initialize_work_item(
++ dm,
++ &dm->beamforming_info.txbf_info.txbf_fw_ndpa_work_item,
++ (RT_WORKITEM_CALL_BACK)hal_com_txbf_fw_ndpa_work_item_callback,
++ (void *)adapter,
++ "txbf_fw_ndpa_work_item");
++
++ odm_initialize_work_item(
++ dm,
++ &dm->beamforming_info.txbf_info.txbf_clk_work_item,
++ (RT_WORKITEM_CALL_BACK)hal_com_txbf_clk_work_item_callback,
++ (void *)adapter,
++ "txbf_clk_work_item");
++
++ odm_initialize_work_item(
++ dm,
++ &dm->beamforming_info.txbf_info.txbf_rate_work_item,
++ (RT_WORKITEM_CALL_BACK)hal_com_txbf_rate_work_item_callback,
++ (void *)adapter,
++ "txbf_rate_work_item");
++
++ odm_initialize_work_item(
++ dm,
++ &dm->beamforming_info.txbf_info.txbf_status_work_item,
++ (RT_WORKITEM_CALL_BACK)hal_com_txbf_status_work_item_callback,
++ (void *)adapter,
++ "txbf_status_work_item");
++
++ odm_initialize_work_item(
++ dm,
++ &dm->beamforming_info.txbf_info.txbf_reset_tx_path_work_item,
++ (RT_WORKITEM_CALL_BACK)hal_com_txbf_reset_tx_path_work_item_callback,
++ (void *)adapter,
++ "txbf_reset_tx_path_work_item");
++
++ odm_initialize_work_item(
++ dm,
++ &dm->beamforming_info.txbf_info.txbf_get_tx_rate_work_item,
++ (RT_WORKITEM_CALL_BACK)hal_com_txbf_get_tx_rate_work_item_callback,
++ (void *)adapter,
++ "txbf_get_tx_rate_work_item");
++#endif
++
++#if (PHYDM_LA_MODE_SUPPORT == 1)
++ odm_initialize_work_item(
++ dm,
++ &dm->adcsmp.adc_smp_work_item,
++ (RT_WORKITEM_CALL_BACK)adc_smp_work_item_callback,
++ (void *)adapter,
++ "adc_smp_work_item");
++
++ odm_initialize_work_item(
++ dm,
++ &dm->adcsmp.adc_smp_work_item_1,
++ (RT_WORKITEM_CALL_BACK)adc_smp_work_item_callback,
++ (void *)adapter,
++ "adc_smp_work_item_1");
++#endif
++}
++
++void odm_free_all_work_items(struct dm_struct *dm)
++{
++#if USE_WORKITEM
++
++#ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY
++ odm_free_work_item(&dm->dm_swat_table.phydm_sw_antenna_switch_workitem);
++#endif
++
++#ifdef CONFIG_ADAPTIVE_SOML
++ odm_free_work_item(&dm->dm_soml_table.phydm_adaptive_soml_workitem);
++#endif
++
++#ifdef ODM_EVM_ENHANCE_ANTDIV
++ odm_free_work_item(&dm->phydm_evm_antdiv_workitem);
++#endif
++
++#if (defined(CONFIG_HL_SMART_ANTENNA))
++ odm_free_work_item(&dm->dm_sat_table.hl_smart_antenna_workitem);
++ odm_free_work_item(&dm->dm_sat_table.hl_smart_antenna_decision_workitem);
++#endif
++
++#if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))
++ odm_free_work_item(&dm->fast_ant_training_workitem);
++#endif
++ odm_free_work_item(&dm->ra_rpt_workitem);
++/*odm_free_work_item((&dm->sbdcnt_workitem));*/
++#endif
++
++#ifdef PHYDM_BEAMFORMING_SUPPORT
++ odm_free_work_item((&dm->beamforming_info.txbf_info.txbf_enter_work_item));
++ odm_free_work_item((&dm->beamforming_info.txbf_info.txbf_leave_work_item));
++ odm_free_work_item((&dm->beamforming_info.txbf_info.txbf_fw_ndpa_work_item));
++ odm_free_work_item((&dm->beamforming_info.txbf_info.txbf_clk_work_item));
++ odm_free_work_item((&dm->beamforming_info.txbf_info.txbf_rate_work_item));
++ odm_free_work_item((&dm->beamforming_info.txbf_info.txbf_status_work_item));
++ odm_free_work_item((&dm->beamforming_info.txbf_info.txbf_reset_tx_path_work_item));
++ odm_free_work_item((&dm->beamforming_info.txbf_info.txbf_get_tx_rate_work_item));
++#endif
++
++#if (PHYDM_LA_MODE_SUPPORT == 1)
++ odm_free_work_item((&dm->adcsmp.adc_smp_work_item));
++ odm_free_work_item((&dm->adcsmp.adc_smp_work_item_1));
++#endif
++}
++#endif /*#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)*/
++
++void odm_init_all_timers(struct dm_struct *dm)
++{
++#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))
++ odm_ant_div_timers(dm, INIT_ANTDIV_TIMMER);
++#endif
++#if (defined(PHYDM_TDMA_DIG_SUPPORT))
++#ifdef IS_USE_NEW_TDMA
++ phydm_tdma_dig_timers(dm, INIT_TDMA_DIG_TIMMER);
++#endif
++#endif
++#ifdef CONFIG_ADAPTIVE_SOML
++ phydm_adaptive_soml_timers(dm, INIT_SOML_TIMMER);
++#endif
++#ifdef PHYDM_LNA_SAT_CHK_SUPPORT
++#ifdef PHYDM_LNA_SAT_CHK_TYPE1
++ phydm_lna_sat_chk_timers(dm, INIT_LNA_SAT_CHK_TIMMER);
++#endif
++#endif
++
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++ odm_initialize_timer(dm, &dm->sbdcnt_timer,
++ (void *)phydm_sbd_callback, NULL, "SbdTimer");
++#ifdef PHYDM_BEAMFORMING_SUPPORT
++ odm_initialize_timer(dm, &dm->beamforming_info.txbf_info.txbf_fw_ndpa_timer,
++ (void *)hal_com_txbf_fw_ndpa_timer_callback, NULL,
++ "txbf_fw_ndpa_timer");
++#endif
++#endif
++
++#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
++#ifdef PHYDM_BEAMFORMING_SUPPORT
++ odm_initialize_timer(dm, &dm->beamforming_info.beamforming_timer,
++ (void *)beamforming_sw_timer_callback, NULL,
++ "beamforming_timer");
++#endif
++#endif
++}
++
++void odm_cancel_all_timers(struct dm_struct *dm)
++{
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++ /* @2012/01/12 MH Temp BSOD fix. We need to find NIC allocate mem fail reason in win7*/
++ if (dm->adapter == NULL)
++ return;
++#endif
++
++#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))
++ odm_ant_div_timers(dm, CANCEL_ANTDIV_TIMMER);
++#endif
++#ifdef PHYDM_TDMA_DIG_SUPPORT
++#ifdef IS_USE_NEW_TDMA
++ phydm_tdma_dig_timers(dm, CANCEL_TDMA_DIG_TIMMER);
++#endif
++#endif
++#ifdef CONFIG_ADAPTIVE_SOML
++ phydm_adaptive_soml_timers(dm, CANCEL_SOML_TIMMER);
++#endif
++#ifdef PHYDM_LNA_SAT_CHK_SUPPORT
++#ifdef PHYDM_LNA_SAT_CHK_TYPE1
++ phydm_lna_sat_chk_timers(dm, CANCEL_LNA_SAT_CHK_TIMMER);
++#endif
++#endif
++
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++ odm_cancel_timer(dm, &dm->sbdcnt_timer);
++#ifdef PHYDM_BEAMFORMING_SUPPORT
++ odm_cancel_timer(dm, &dm->beamforming_info.txbf_info.txbf_fw_ndpa_timer);
++#endif
++#endif
++
++#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
++#ifdef PHYDM_BEAMFORMING_SUPPORT
++ odm_cancel_timer(dm, &dm->beamforming_info.beamforming_timer);
++#endif
++#endif
++}
++
++void odm_release_all_timers(struct dm_struct *dm)
++{
++#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))
++ odm_ant_div_timers(dm, RELEASE_ANTDIV_TIMMER);
++#endif
++#ifdef PHYDM_TDMA_DIG_SUPPORT
++#ifdef IS_USE_NEW_TDMA
++ phydm_tdma_dig_timers(dm, RELEASE_TDMA_DIG_TIMMER);
++#endif
++#endif
++#ifdef CONFIG_ADAPTIVE_SOML
++ phydm_adaptive_soml_timers(dm, RELEASE_SOML_TIMMER);
++#endif
++#ifdef PHYDM_LNA_SAT_CHK_SUPPORT
++#ifdef PHYDM_LNA_SAT_CHK_TYPE1
++ phydm_lna_sat_chk_timers(dm, RELEASE_LNA_SAT_CHK_TIMMER);
++#endif
++#endif
++
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++ odm_release_timer(dm, &dm->sbdcnt_timer);
++#ifdef PHYDM_BEAMFORMING_SUPPORT
++ odm_release_timer(dm, &dm->beamforming_info.txbf_info.txbf_fw_ndpa_timer);
++#endif
++#endif
++
++#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
++#ifdef PHYDM_BEAMFORMING_SUPPORT
++ odm_release_timer(dm, &dm->beamforming_info.beamforming_timer);
++#endif
++#endif
++}
++
++#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
++void odm_init_all_threads(
++ struct dm_struct *dm)
++{
++#ifdef TPT_THREAD
++ k_tpt_task_init(dm->priv);
++#endif
++}
++
++void odm_stop_all_threads(
++ struct dm_struct *dm)
++{
++#ifdef TPT_THREAD
++ k_tpt_task_stop(dm->priv);
++#endif
++}
++#endif
++
++#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
++/* @Justin: According to the current RRSI to adjust Response Frame TX power,
++ * 2012/11/05
++ */
++void odm_dtc(struct dm_struct *dm)
++{
++#ifdef CONFIG_DM_RESP_TXAGC
++/* RSSI higher than this value, start to decade TX power */
++#define DTC_BASE 35
++
++/* RSSI lower than this value, start to increase TX power */
++#define DTC_DWN_BASE (DTC_BASE - 5)
++
++ /* RSSI vs TX power step mapping: decade TX power */
++ static const u8 dtc_table_down[] = {
++ DTC_BASE,
++ (DTC_BASE + 5),
++ (DTC_BASE + 10),
++ (DTC_BASE + 15),
++ (DTC_BASE + 20),
++ (DTC_BASE + 25)};
++
++ /* RSSI vs TX power step mapping: increase TX power */
++ static const u8 dtc_table_up[] = {
++ DTC_DWN_BASE,
++ (DTC_DWN_BASE - 5),
++ (DTC_DWN_BASE - 10),
++ (DTC_DWN_BASE - 15),
++ (DTC_DWN_BASE - 15),
++ (DTC_DWN_BASE - 20),
++ (DTC_DWN_BASE - 20),
++ (DTC_DWN_BASE - 25),
++ (DTC_DWN_BASE - 25),
++ (DTC_DWN_BASE - 30),
++ (DTC_DWN_BASE - 35)};
++
++ u8 i;
++ u8 dtc_steps = 0;
++ u8 sign;
++ u8 resp_txagc = 0;
++
++#if 0
++ /* @As DIG is disabled, DTC is also disable */
++ if (!(dm->support_ability & ODM_XXXXXX))
++ return;
++#endif
++
++ if (dm->rssi_min > DTC_BASE) {
++ /* need to decade the CTS TX power */
++ sign = 1;
++ for (i = 0; i < ARRAY_SIZE(dtc_table_down); i++) {
++ if (dtc_table_down[i] >= dm->rssi_min || dtc_steps >= 6)
++ break;
++ else
++ dtc_steps++;
++ }
++ }
++#if 0
++ else if (dm->rssi_min > DTC_DWN_BASE) {
++ /* needs to increase the CTS TX power */
++ sign = 0;
++ dtc_steps = 1;
++ for (i = 0; i < ARRAY_SIZE(dtc_table_up); i++) {
++ if (dtc_table_up[i] <= dm->rssi_min || dtc_steps >= 10)
++ break;
++ else
++ dtc_steps++;
++ }
++ }
++#endif
++ else {
++ sign = 0;
++ dtc_steps = 0;
++ }
++
++ resp_txagc = dtc_steps | (sign << 4);
++ resp_txagc = resp_txagc | (resp_txagc << 5);
++ odm_write_1byte(dm, 0x06d9, resp_txagc);
++
++ PHYDM_DBG(dm, ODM_COMP_PWR_TRAIN,
++ "%s rssi_min:%u, set RESP_TXAGC to %s %u\n", __func__,
++ dm->rssi_min, sign ? "minus" : "plus", dtc_steps);
++#endif /* @CONFIG_RESP_TXAGC_ADJUST */
++}
++
++#endif /* @#if (DM_ODM_SUPPORT_TYPE == ODM_CE) */
++
++/*@<20170126, BB-Kevin>8188F D-CUT DC cancellation and 8821C*/
++void phydm_dc_cancellation(struct dm_struct *dm)
++{
++#ifdef PHYDM_DC_CANCELLATION
++ u32 offset_i_hex[PHYDM_MAX_RF_PATH] = {0};
++ u32 offset_q_hex[PHYDM_MAX_RF_PATH] = {0};
++ u32 reg_value32[PHYDM_MAX_RF_PATH] = {0};
++ u8 path = RF_PATH_A;
++ u8 set_result;
++
++ if (!(dm->support_ic_type & ODM_DC_CANCELLATION_SUPPORT))
++ return;
++ if ((dm->support_ic_type & ODM_RTL8188F) &&
++ dm->cut_version < ODM_CUT_D)
++ return;
++ if ((dm->support_ic_type & ODM_RTL8192F) &&
++ dm->cut_version == ODM_CUT_A)
++ return;
++
++ PHYDM_DBG(dm, ODM_COMP_API, "%s ======>\n", __func__);
++
++ /*@DC_Estimation (only for 2x2 ic now) */
++
++ for (path = RF_PATH_A; path < PHYDM_MAX_RF_PATH; path++) {
++ if (path > RF_PATH_A &&
++ dm->support_ic_type & (ODM_RTL8821C | ODM_RTL8188F |
++ ODM_RTL8710B | ODM_RTL8721D))
++ break;
++ else if (path > RF_PATH_B &&
++ dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8192F))
++ break;
++ if (phydm_stop_ic_trx(dm, PHYDM_SET) == PHYDM_SET_FAIL) {
++ PHYDM_DBG(dm, ODM_COMP_API, "STOP_TRX_FAIL\n");
++ return;
++ }
++ odm_write_dig(dm, 0x7e);
++ /*@Disable LNA*/
++ if (dm->support_ic_type & ODM_RTL8821C)
++ halrf_rf_lna_setting(dm, HALRF_LNA_DISABLE);
++ /*Turn off 3-wire*/
++ phydm_stop_3_wire(dm, PHYDM_SET);
++ if (dm->support_ic_type & (ODM_RTL8188F | ODM_RTL8710B)) {
++ /*set debug port to 0x235*/
++ if (!phydm_set_bb_dbg_port(dm, DBGPORT_PRI_1, 0x235)) {
++ PHYDM_DBG(dm, ODM_COMP_API,
++ "Set Debug port Fail\n");
++ return;
++ }
++ } else if (dm->support_ic_type & ODM_RTL8721D) {
++ /*set debug port to 0x200*/
++ if (!phydm_set_bb_dbg_port(dm, DBGPORT_PRI_2, 0x200)) {
++ PHYDM_DBG(dm, ODM_COMP_API,
++ "Set Debug port Fail\n");
++ return;
++ }
++ } else if (dm->support_ic_type & ODM_RTL8821C) {
++ if (!phydm_set_bb_dbg_port(dm, DBGPORT_PRI_1, 0x200)) {
++ /*set debug port to 0x200*/
++ PHYDM_DBG(dm, ODM_COMP_API,
++ "Set Debug port Fail\n");
++ return;
++ }
++ phydm_bb_dbg_port_header_sel(dm, 0x0);
++ } else if (dm->support_ic_type & ODM_RTL8822B) {
++ if (path == RF_PATH_A &&
++ !phydm_set_bb_dbg_port(dm, DBGPORT_PRI_1, 0x200)) {
++ /*set debug port to 0x200*/
++ PHYDM_DBG(dm, ODM_COMP_API,
++ "Set Debug port Fail\n");
++ return;
++ }
++ if (path == RF_PATH_B &&
++ !phydm_set_bb_dbg_port(dm, DBGPORT_PRI_1, 0x202)) {
++ /*set debug port to 0x200*/
++ PHYDM_DBG(dm, ODM_COMP_API,
++ "Set Debug port Fail\n");
++ return;
++ }
++ phydm_bb_dbg_port_header_sel(dm, 0x0);
++ } else if (dm->support_ic_type & ODM_RTL8192F) {
++ if (path == RF_PATH_A &&
++ !phydm_set_bb_dbg_port(dm, DBGPORT_PRI_1, 0x235)) {
++ /*set debug port to 0x235*/
++ PHYDM_DBG(dm, ODM_COMP_API,
++ "Set Debug port Fail\n");
++ return;
++ }
++ if (path == RF_PATH_B &&
++ !phydm_set_bb_dbg_port(dm, DBGPORT_PRI_1, 0x23d)) {
++ /*set debug port to 0x23d*/
++ PHYDM_DBG(dm, ODM_COMP_API,
++ "Set Debug port Fail\n");
++ return;
++ }
++ }
++
++ /*@disable CCK DCNF*/
++ odm_set_bb_reg(dm, R_0xa78, MASKBYTE1, 0x0);
++
++ PHYDM_DBG(dm, ODM_COMP_API, "DC cancellation Begin!!!\n");
++
++ phydm_stop_ck320(dm, true); /*stop ck320*/
++
++ /* the same debug port both for path-a and path-b*/
++ reg_value32[path] = phydm_get_bb_dbg_port_val(dm);
++
++ phydm_stop_ck320(dm, false); /*start ck320*/
++
++ phydm_release_bb_dbg_port(dm);
++ /* @Turn on 3-wire*/
++ phydm_stop_3_wire(dm, PHYDM_REVERT);
++ /* @Enable LNA*/
++ if (dm->support_ic_type & ODM_RTL8821C)
++ halrf_rf_lna_setting(dm, HALRF_LNA_ENABLE);
++
++ odm_write_dig(dm, 0x20);
++
++ set_result = phydm_stop_ic_trx(dm, PHYDM_REVERT);
++
++ PHYDM_DBG(dm, ODM_COMP_API, "DC cancellation OK!!!\n");
++ }
++
++ /*@DC_Cancellation*/
++ /*@DC compensation to CCK data path*/
++ odm_set_bb_reg(dm, R_0xa9c, BIT(20), 0x1);
++ if (dm->support_ic_type & (ODM_RTL8188F | ODM_RTL8710B)) {
++ offset_i_hex[0] = (reg_value32[0] & 0xffc0000) >> 18;
++ offset_q_hex[0] = (reg_value32[0] & 0x3ff00) >> 8;
++
++ /*@Before filling into registers,
++ *offset should be multiplexed (-1)
++ */
++ offset_i_hex[0] = (offset_i_hex[0] >= 0x200) ?
++ (0x400 - offset_i_hex[0]) :
++ (0x1ff - offset_i_hex[0]);
++ offset_q_hex[0] = (offset_q_hex[0] >= 0x200) ?
++ (0x400 - offset_q_hex[0]) :
++ (0x1ff - offset_q_hex[0]);
++
++ odm_set_bb_reg(dm, R_0x950, 0x1ff, offset_i_hex[0]);
++ odm_set_bb_reg(dm, R_0x950, 0x1ff0000, offset_q_hex[0]);
++ } else if (dm->support_ic_type & (ODM_RTL8821C | ODM_RTL8822B)) {
++ /* Path-a */
++ offset_i_hex[0] = (reg_value32[0] & 0xffc00) >> 10;
++ offset_q_hex[0] = reg_value32[0] & 0x3ff;
++
++ /*@Before filling into registers,
++ *offset should be multiplexed (-1)
++ */
++ offset_i_hex[0] = 0x400 - offset_i_hex[0];
++ offset_q_hex[0] = 0x400 - offset_q_hex[0];
++
++ odm_set_bb_reg(dm, R_0xc10, 0x3c000000,
++ (0x3c0 & offset_i_hex[0]) >> 6);
++ odm_set_bb_reg(dm, R_0xc10, 0xfc00, 0x3f & offset_i_hex[0]);
++ odm_set_bb_reg(dm, R_0xc14, 0x3c000000,
++ (0x3c0 & offset_q_hex[0]) >> 6);
++ odm_set_bb_reg(dm, R_0xc14, 0xfc00, 0x3f & offset_q_hex[0]);
++
++ /* Path-b */
++ if (dm->rf_type > RF_1T1R) {
++ offset_i_hex[1] = (reg_value32[1] & 0xffc00) >> 10;
++ offset_q_hex[1] = reg_value32[1] & 0x3ff;
++
++ /*@Before filling into registers,
++ *offset should be multiplexed (-1)
++ */
++ offset_i_hex[1] = 0x400 - offset_i_hex[1];
++ offset_q_hex[1] = 0x400 - offset_q_hex[1];
++
++ odm_set_bb_reg(dm, R_0xe10, 0x3c000000,
++ (0x3c0 & offset_i_hex[1]) >> 6);
++ odm_set_bb_reg(dm, R_0xe10, 0xfc00,
++ 0x3f & offset_i_hex[1]);
++ odm_set_bb_reg(dm, R_0xe14, 0x3c000000,
++ (0x3c0 & offset_q_hex[1]) >> 6);
++ odm_set_bb_reg(dm, R_0xe14, 0xfc00,
++ 0x3f & offset_q_hex[1]);
++ }
++ } else if (dm->support_ic_type & (ODM_RTL8192F)) {
++ /* Path-a I:df4[27:18],Q:df4[17:8]*/
++ offset_i_hex[0] = (reg_value32[0] & 0xffc0000) >> 18;
++ offset_q_hex[0] = (reg_value32[0] & 0x3ff00) >> 8;
++
++ /*@Before filling into registers,
++ *offset should be multiplexed (-1)
++ */
++ offset_i_hex[0] = (offset_i_hex[0] >= 0x200) ?
++ (0x400 - offset_i_hex[0]) :
++ (0xff - offset_i_hex[0]);
++ offset_q_hex[0] = (offset_q_hex[0] >= 0x200) ?
++ (0x400 - offset_q_hex[0]) :
++ (0xff - offset_q_hex[0]);
++ /*Path-a I:c10[7:0],Q:c10[15:8]*/
++ odm_set_bb_reg(dm, R_0xc10, 0xff, offset_i_hex[0]);
++ odm_set_bb_reg(dm, R_0xc10, 0xff00, offset_q_hex[0]);
++
++ /* Path-b */
++ if (dm->rf_type > RF_1T1R) {
++ /* @I:df4[27:18],Q:df4[17:8]*/
++ offset_i_hex[1] = (reg_value32[1] & 0xffc0000) >> 18;
++ offset_q_hex[1] = (reg_value32[1] & 0x3ff00) >> 8;
++
++ /*@Before filling into registers,
++ *offset should be multiplexed (-1)
++ */
++ offset_i_hex[1] = (offset_i_hex[1] >= 0x200) ?
++ (0x400 - offset_i_hex[1]) :
++ (0xff - offset_i_hex[1]);
++ offset_q_hex[1] = (offset_q_hex[1] >= 0x200) ?
++ (0x400 - offset_q_hex[1]) :
++ (0xff - offset_q_hex[1]);
++ /*Path-b I:c18[7:0],Q:c18[15:8]*/
++ odm_set_bb_reg(dm, R_0xc18, 0xff, offset_i_hex[1]);
++ odm_set_bb_reg(dm, R_0xc18, 0xff00, offset_q_hex[1]);
++ }
++ } else if (dm->support_ic_type & (ODM_RTL8721D)) {
++ /*judy modified 20180517*/
++ offset_i_hex[0] = (reg_value32[0] & 0xff800) >> 11;
++ offset_q_hex[0] = (reg_value32[0] & 0x3fe) >> 1;
++
++ /*@Before filling into registers,
++ *offset should be multiplexed (-1)
++ */
++ offset_i_hex[0] = 0x200 - offset_i_hex[0];
++ offset_q_hex[0] = 0x200 - offset_q_hex[0];
++
++ odm_set_bb_reg(dm, R_0x950, 0x1ff, offset_i_hex[0]);
++ odm_set_bb_reg(dm, R_0x950, 0x1ff0000, offset_q_hex[0]);
++ }
++#endif
++}
++
++void phydm_receiver_blocking(void *dm_void)
++{
++#ifdef CONFIG_RECEIVER_BLOCKING
++ struct dm_struct *dm = (struct dm_struct *)dm_void;
++ u32 chnl = *dm->channel;
++ u8 bw = *dm->band_width;
++ u32 bb_regf0 = odm_get_bb_reg(dm, R_0xf0, 0xf000);
++
++ if (!(dm->support_ic_type & ODM_RECEIVER_BLOCKING_SUPPORT) ||
++ !(dm->support_ability & ODM_BB_ADAPTIVITY))
++ return;
++
++ if ((dm->support_ic_type & ODM_RTL8188E && bb_regf0 < 8) ||
++ dm->support_ic_type & ODM_RTL8192E) {
++ /*@8188E_T version*/
++ if (dm->consecutive_idlel_time <= 10 || *dm->mp_mode)
++ goto end;
++
++ if (bw == CHANNEL_WIDTH_20 && chnl == 1) {
++ phydm_nbi_setting(dm, FUNC_ENABLE, chnl, 20, 2410,
++ PHYDM_DONT_CARE);
++ dm->is_rx_blocking_en = true;
++ } else if ((bw == CHANNEL_WIDTH_20) && (chnl == 13)) {
++ phydm_nbi_setting(dm, FUNC_ENABLE, chnl, 20, 2473,
++ PHYDM_DONT_CARE);
++ dm->is_rx_blocking_en = true;
++ } else if (dm->is_rx_blocking_en && chnl != 1 && chnl != 13) {
++ phydm_nbi_enable(dm, FUNC_DISABLE);
++ odm_set_bb_reg(dm, R_0xc40, 0x1f000000, 0x1f);
++ dm->is_rx_blocking_en = false;
++ }
++ return;
++ } else if ((dm->support_ic_type & ODM_RTL8188E && bb_regf0 >= 8)) {
++ /*@8188E_S version*/
++ if (dm->consecutive_idlel_time <= 10 || *dm->mp_mode)
++ goto end;
++
++ if (bw == CHANNEL_WIDTH_20 && chnl == 13) {
++ phydm_nbi_setting(dm, FUNC_ENABLE, chnl, 20, 2473,
++ PHYDM_DONT_CARE);
++ dm->is_rx_blocking_en = true;
++ } else if (dm->is_rx_blocking_en && chnl != 13) {
++ phydm_nbi_enable(dm, FUNC_DISABLE);
++ odm_set_bb_reg(dm, R_0xc40, 0x1f000000, 0x1f);
++ dm->is_rx_blocking_en = false;
++ }
++ return;
++ }
++
++end:
++ if (dm->is_rx_blocking_en) {
++ phydm_nbi_enable(dm, FUNC_DISABLE);
++ odm_set_bb_reg(dm, R_0xc40, 0x1f000000, 0x1f);
++ dm->is_rx_blocking_en = false;
++ }
++#endif
++}
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/phydm_cck_pd.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/phydm_cck_pd.c
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/phydm_cck_pd.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/phydm_cck_pd.c 2021-03-07 18:16:17.061956384 +0200
@@ -0,0 +1,1086 @@
+/******************************************************************************
+ *
@@ -222434,11 +217752,9 @@ index 000000000..8f5229abf
+}
+#endif /*#ifdef PHYDM_SUPPORT_CCKPD*/
+
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_cck_pd.h linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_cck_pd.h
-new file mode 100644
-index 000000000..f8c8625df
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_cck_pd.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/phydm_cck_pd.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/phydm_cck_pd.h
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/phydm_cck_pd.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/phydm_cck_pd.h 2021-03-07 18:16:17.061956384 +0200
@@ -0,0 +1,155 @@
+/******************************************************************************
+ *
@@ -222595,11 +217911,9 @@ index 000000000..f8c8625df
+
+void phydm_cck_pd_init(void *dm_void);
+#endif
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_ccx.c linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_ccx.c
-new file mode 100644
-index 000000000..f9ea9bb99
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_ccx.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/phydm_ccx.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/phydm_ccx.c
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/phydm_ccx.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/phydm_ccx.c 2021-03-07 18:16:17.061956384 +0200
@@ -0,0 +1,1802 @@
+/******************************************************************************
+ *
@@ -224403,11 +219717,9 @@ index 000000000..f9ea9bb99
+ *_out_len = out_len;
+}
+
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_ccx.h linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_ccx.h
-new file mode 100644
-index 000000000..2b3d1da6b
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_ccx.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/phydm_ccx.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/phydm_ccx.h
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/phydm_ccx.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/phydm_ccx.h 2021-03-07 18:16:17.061956384 +0200
@@ -0,0 +1,268 @@
+/******************************************************************************
+ *
@@ -224677,11 +219989,9 @@ index 000000000..2b3d1da6b
+ char *output, u32 *_out_len);
+
+#endif
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_cfotracking.c linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_cfotracking.c
-new file mode 100644
-index 000000000..95d89e379
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_cfotracking.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/phydm_cfotracking.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/phydm_cfotracking.c
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/phydm_cfotracking.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/phydm_cfotracking.c 2021-03-07 18:16:17.061956384 +0200
@@ -0,0 +1,594 @@
+/******************************************************************************
+ *
@@ -225277,11 +220587,9 @@ index 000000000..95d89e379
+ *_out_len = out_len;
+}
+
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_cfotracking.h linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_cfotracking.h
-new file mode 100644
-index 000000000..080c29316
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_cfotracking.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/phydm_cfotracking.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/phydm_cfotracking.h
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/phydm_cfotracking.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/phydm_cfotracking.h 2021-03-07 18:16:17.061956384 +0200
@@ -0,0 +1,73 @@
+/******************************************************************************
+ *
@@ -225356,11 +220664,9 @@ index 000000000..080c29316
+void phy_Init_crystal_capacity(void *dm_void, u8 crystal_cap);
+#endif
+#endif
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_debug.c linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_debug.c
-new file mode 100644
-index 000000000..57d24e0e6
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_debug.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/phydm_debug.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/phydm_debug.c
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/phydm_debug.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/phydm_debug.c 2021-03-07 18:16:17.062956431 +0200
@@ -0,0 +1,4728 @@
+/******************************************************************************
+ *
@@ -230090,11 +225396,9 @@ index 000000000..57d24e0e6
+#endif
+#endif /*@#ifdef CONFIG_PHYDM_DEBUG_FUNCTION*/
+}
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_debug.h linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_debug.h
-new file mode 100644
-index 000000000..a795f30d7
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_debug.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/phydm_debug.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/phydm_debug.h
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/phydm_debug.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/phydm_debug.h 2021-03-07 18:16:17.062956431 +0200
@@ -0,0 +1,480 @@
+/******************************************************************************
+ *
@@ -230576,11 +225880,9 @@ index 000000000..a795f30d7
+void phydm_fw_trace_handler_8051(void *dm_void, u8 *cmd_buf, u8 cmd_len);
+
+#endif /* @__ODM_DBG_H__ */
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_dfs.c linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_dfs.c
-new file mode 100644
-index 000000000..39c387942
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_dfs.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/phydm_dfs.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/phydm_dfs.c
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/phydm_dfs.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/phydm_dfs.c 2021-03-07 18:16:17.062956431 +0200
@@ -0,0 +1,2323 @@
+/******************************************************************************
+ *
@@ -232905,11 +228207,9 @@ index 000000000..39c387942
+}
+#endif
+#endif
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_dfs.h linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_dfs.h
-new file mode 100644
-index 000000000..a1a96db5f
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_dfs.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/phydm_dfs.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/phydm_dfs.h
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/phydm_dfs.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/phydm_dfs.h 2021-03-07 18:16:17.062956431 +0200
@@ -0,0 +1,190 @@
+/******************************************************************************
+ *
@@ -233101,11 +228401,9 @@ index 000000000..a1a96db5f
+#endif
+
+#endif /*@#ifndef __PHYDM_DFS_H__ */
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_dig.c linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_dig.c
-new file mode 100644
-index 000000000..eea6dcee4
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_dig.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/phydm_dig.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/phydm_dig.c
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/phydm_dig.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/phydm_dig.c 2021-03-07 18:16:17.062956431 +0200
@@ -0,0 +1,2858 @@
+/******************************************************************************
+ *
@@ -235965,11 +231263,9 @@ index 000000000..eea6dcee4
+}
+#endif /*#if (RTL8822B_SUPPORT)*/
+#endif /*#ifdef CONFIG_MCC_DM*/
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_dig.h linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_dig.h
-new file mode 100644
-index 000000000..9800980af
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_dig.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/phydm_dig.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/phydm_dig.h
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/phydm_dig.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/phydm_dig.h 2021-03-07 18:16:17.062956431 +0200
@@ -0,0 +1,337 @@
+/******************************************************************************
+ *
@@ -236308,11 +231604,9 @@ index 000000000..9800980af
+
+
+#endif
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_dynamictxpower.c linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_dynamictxpower.c
-new file mode 100644
-index 000000000..ceed35fe8
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_dynamictxpower.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/phydm_dynamictxpower.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/phydm_dynamictxpower.c
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/phydm_dynamictxpower.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/phydm_dynamictxpower.c 2021-03-07 18:16:17.062956431 +0200
@@ -0,0 +1,517 @@
+/******************************************************************************
+ *
@@ -236831,11 +232125,9 @@ index 000000000..ceed35fe8
+}
+#endif /*@#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)*/
+#endif /* @#ifdef CONFIG_DYNAMIC_TX_TWR */
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_dynamictxpower.h linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_dynamictxpower.h
-new file mode 100644
-index 000000000..3906b72c1
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_dynamictxpower.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/phydm_dynamictxpower.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/phydm_dynamictxpower.h
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/phydm_dynamictxpower.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/phydm_dynamictxpower.h 2021-03-07 18:16:17.062956431 +0200
@@ -0,0 +1,103 @@
+/******************************************************************************
+ *
@@ -236940,89 +232232,9 @@ index 000000000..3906b72c1
+
+#endif
+#endif
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_features.h linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_features.h
-new file mode 100644
-index 000000000..afb18393e
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_features.h
-@@ -0,0 +1,72 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ * The full GNU General Public License is included in this distribution in the
-+ * file called LICENSE.
-+ *
-+ * Contact Information:
-+ * wlanfae
-+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
-+ * Hsinchu 300, Taiwan.
-+ *
-+ * Larry Finger
-+ *
-+ *****************************************************************************/
-+
-+#ifndef __PHYDM_FEATURES_H__
-+#define __PHYDM_FEATURES_H__
-+
-+#define CONFIG_RUN_IN_DRV
-+#define ODM_DC_CANCELLATION_SUPPORT (ODM_RTL8188F | \
-+ ODM_RTL8710B | \
-+ ODM_RTL8192F | \
-+ ODM_RTL8821C | \
-+ ODM_RTL8721D)
-+#define ODM_RECEIVER_BLOCKING_SUPPORT (ODM_RTL8188E | ODM_RTL8192E)
-+
-+/*@20170103 YuChen add for FW API*/
-+#define PHYDM_FW_API_ENABLE_8822B 1
-+#define PHYDM_FW_API_FUNC_ENABLE_8822B 1
-+#define PHYDM_FW_API_ENABLE_8821C 1
-+#define PHYDM_FW_API_FUNC_ENABLE_8821C 1
-+#define PHYDM_FW_API_ENABLE_8195B 1
-+#define PHYDM_FW_API_FUNC_ENABLE_8195B 1
-+#define PHYDM_FW_API_ENABLE_8198F 1
-+#define PHYDM_FW_API_FUNC_ENABLE_8198F 1
-+#define PHYDM_FW_API_ENABLE_8822C 1
-+#define PHYDM_FW_API_FUNC_ENABLE_8822C 1
-+#define PHYDM_FW_API_ENABLE_8814B 1
-+#define PHYDM_FW_API_FUNC_ENABLE_8814B 1
-+#define PHYDM_FW_API_ENABLE_8812F 1
-+#define PHYDM_FW_API_FUNC_ENABLE_8812F 1
-+
-+#define CONFIG_POWERSAVING 0
-+
-+#ifdef BEAMFORMING_SUPPORT
-+#if (BEAMFORMING_SUPPORT)
-+ #define PHYDM_BEAMFORMING_SUPPORT
-+#endif
-+#endif
-+
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+ #include "phydm_features_win.h"
-+#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
-+ #include "phydm_features_ce.h"
-+ /*@#include "phydm_features_ce2_kernel.h"*/
-+#elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
-+ #include "phydm_features_ap.h"
-+#elif (DM_ODM_SUPPORT_TYPE == ODM_IOT)
-+ #include "phydm_features_iot.h"
-+#endif
-+
-+#endif
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_features_ap.h linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_features_ap.h
-new file mode 100644
-index 000000000..db2c3d27e
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_features_ap.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/phydm_features_ap.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/phydm_features_ap.h
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/phydm_features_ap.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/phydm_features_ap.h 2021-03-07 18:16:17.062956431 +0200
@@ -0,0 +1,196 @@
+/******************************************************************************
+ *
@@ -237220,11 +232432,97 @@ index 000000000..db2c3d27e
+#endif
+
+#endif
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_features_ce.h linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_features_ce.h
-new file mode 100644
-index 000000000..6c12436c8
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_features_ce.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/phydm_features_ce2_kernel.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/phydm_features_ce2_kernel.h
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/phydm_features_ce2_kernel.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/phydm_features_ce2_kernel.h 2021-03-07 18:16:17.062956431 +0200
+@@ -0,0 +1,84 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * The full GNU General Public License is included in this distribution in the
++ * file called LICENSE.
++ *
++ * Contact Information:
++ * wlanfae
++ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
++ * Hsinchu 300, Taiwan.
++ *
++ * Larry Finger
++ *
++ *****************************************************************************/
++
++#ifndef __PHYDM_FEATURES_CE_H__
++#define __PHYDM_FEATURES_CE_H__
++
++#define PHYDM_LA_MODE_SUPPORT 0
++
++#if (RTL8822B_SUPPORT || RTL8812A_SUPPORT || RTL8197F_SUPPORT ||\
++ RTL8192F_SUPPORT)
++ #define DYN_ANT_WEIGHTING_SUPPORT
++#endif
++
++#if (RTL8822B_SUPPORT || RTL8821C_SUPPORT)
++ #define FAHM_SUPPORT
++#endif
++ #define NHM_SUPPORT
++ #define CLM_SUPPORT
++
++#if (RTL8822B_SUPPORT)
++ #define PHYDM_TXA_CALIBRATION
++#endif
++
++#if (RTL8188F_SUPPORT || RTL8710B_SUPPORT || RTL8821C_SUPPORT ||\
++ RTL8822B_SUPPORT || RTL8192F_SUPPORT)
++ #define PHYDM_DC_CANCELLATION
++#endif
++
++#if (RTL8192F_SUPPORT == 1)
++ /*#define CONFIG_8912F_SPUR_CALIBRATION*/
++#endif
++
++#if (RTL8822B_SUPPORT == 1)
++ /* #define CONFIG_8822B_SPUR_CALIBRATION */
++#endif
++
++#define PHYDM_SUPPORT_CCKPD
++#define PHYDM_SUPPORT_ADAPTIVITY
++
++#ifdef CONFIG_DFS_MASTER
++ #define CONFIG_PHYDM_DFS_MASTER
++#endif
++
++#define CONFIG_BB_TXBF_API
++#define CONFIG_PHYDM_DEBUG_FUNCTION
++
++#ifdef CONFIG_BT_COEXIST
++ #define ODM_CONFIG_BT_COEXIST
++#endif
++#define PHYDM_SUPPORT_RSSI_MONITOR
++#define CFG_DIG_DAMPING_CHK
++
++
++#ifdef PHYDM_BEAMFORMING_SUPPORT
++ #if (RTL8192F_SUPPORT || RTL8195B_SUPPORT || RTL8821C_SUPPORT ||\
++ RTL8822B_SUPPORT || RTL8197F_SUPPORT || RTL8198F_SUPPORT ||\
++ RTL8822C_SUPPORT || RTL8814B_SUPPORT)
++ #define DRIVER_BEAMFORMING_VERSION2
++ #endif
++#endif
++
++#endif
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/phydm_features_ce.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/phydm_features_ce.h
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/phydm_features_ce.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/phydm_features_ce.h 2021-03-07 18:16:17.062956431 +0200
@@ -0,0 +1,214 @@
+/******************************************************************************
+ *
@@ -237440,12 +232738,10 @@ index 000000000..6c12436c8
+
+
+#endif
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_features_ce2_kernel.h linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_features_ce2_kernel.h
-new file mode 100644
-index 000000000..c206ea605
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_features_ce2_kernel.h
-@@ -0,0 +1,84 @@
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/phydm_features.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/phydm_features.h
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/phydm_features.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/phydm_features.h 2021-03-07 18:16:17.062956431 +0200
+@@ -0,0 +1,72 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
@@ -237471,70 +232767,56 @@ index 000000000..c206ea605
+ *
+ *****************************************************************************/
+
-+#ifndef __PHYDM_FEATURES_CE_H__
-+#define __PHYDM_FEATURES_CE_H__
++#ifndef __PHYDM_FEATURES_H__
++#define __PHYDM_FEATURES_H__
+
-+#define PHYDM_LA_MODE_SUPPORT 0
++#define CONFIG_RUN_IN_DRV
++#define ODM_DC_CANCELLATION_SUPPORT (ODM_RTL8188F | \
++ ODM_RTL8710B | \
++ ODM_RTL8192F | \
++ ODM_RTL8821C | \
++ ODM_RTL8721D)
++#define ODM_RECEIVER_BLOCKING_SUPPORT (ODM_RTL8188E | ODM_RTL8192E)
+
-+#if (RTL8822B_SUPPORT || RTL8812A_SUPPORT || RTL8197F_SUPPORT ||\
-+ RTL8192F_SUPPORT)
-+ #define DYN_ANT_WEIGHTING_SUPPORT
++/*@20170103 YuChen add for FW API*/
++#define PHYDM_FW_API_ENABLE_8822B 1
++#define PHYDM_FW_API_FUNC_ENABLE_8822B 1
++#define PHYDM_FW_API_ENABLE_8821C 1
++#define PHYDM_FW_API_FUNC_ENABLE_8821C 1
++#define PHYDM_FW_API_ENABLE_8195B 1
++#define PHYDM_FW_API_FUNC_ENABLE_8195B 1
++#define PHYDM_FW_API_ENABLE_8198F 1
++#define PHYDM_FW_API_FUNC_ENABLE_8198F 1
++#define PHYDM_FW_API_ENABLE_8822C 1
++#define PHYDM_FW_API_FUNC_ENABLE_8822C 1
++#define PHYDM_FW_API_ENABLE_8814B 1
++#define PHYDM_FW_API_FUNC_ENABLE_8814B 1
++#define PHYDM_FW_API_ENABLE_8812F 1
++#define PHYDM_FW_API_FUNC_ENABLE_8812F 1
++
++#define CONFIG_POWERSAVING 0
++
++#ifdef BEAMFORMING_SUPPORT
++#if (BEAMFORMING_SUPPORT)
++ #define PHYDM_BEAMFORMING_SUPPORT
++#endif
+#endif
+
-+#if (RTL8822B_SUPPORT || RTL8821C_SUPPORT)
-+ #define FAHM_SUPPORT
-+#endif
-+ #define NHM_SUPPORT
-+ #define CLM_SUPPORT
-+
-+#if (RTL8822B_SUPPORT)
-+ #define PHYDM_TXA_CALIBRATION
-+#endif
-+
-+#if (RTL8188F_SUPPORT || RTL8710B_SUPPORT || RTL8821C_SUPPORT ||\
-+ RTL8822B_SUPPORT || RTL8192F_SUPPORT)
-+ #define PHYDM_DC_CANCELLATION
-+#endif
-+
-+#if (RTL8192F_SUPPORT == 1)
-+ /*#define CONFIG_8912F_SPUR_CALIBRATION*/
-+#endif
-+
-+#if (RTL8822B_SUPPORT == 1)
-+ /* #define CONFIG_8822B_SPUR_CALIBRATION */
-+#endif
-+
-+#define PHYDM_SUPPORT_CCKPD
-+#define PHYDM_SUPPORT_ADAPTIVITY
-+
-+#ifdef CONFIG_DFS_MASTER
-+ #define CONFIG_PHYDM_DFS_MASTER
-+#endif
-+
-+#define CONFIG_BB_TXBF_API
-+#define CONFIG_PHYDM_DEBUG_FUNCTION
-+
-+#ifdef CONFIG_BT_COEXIST
-+ #define ODM_CONFIG_BT_COEXIST
-+#endif
-+#define PHYDM_SUPPORT_RSSI_MONITOR
-+#define CFG_DIG_DAMPING_CHK
-+
-+
-+#ifdef PHYDM_BEAMFORMING_SUPPORT
-+ #if (RTL8192F_SUPPORT || RTL8195B_SUPPORT || RTL8821C_SUPPORT ||\
-+ RTL8822B_SUPPORT || RTL8197F_SUPPORT || RTL8198F_SUPPORT ||\
-+ RTL8822C_SUPPORT || RTL8814B_SUPPORT)
-+ #define DRIVER_BEAMFORMING_VERSION2
-+ #endif
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++ #include "phydm_features_win.h"
++#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
++ #include "phydm_features_ce.h"
++ /*@#include "phydm_features_ce2_kernel.h"*/
++#elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
++ #include "phydm_features_ap.h"
++#elif (DM_ODM_SUPPORT_TYPE == ODM_IOT)
++ #include "phydm_features_iot.h"
+#endif
+
+#endif
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_features_iot.h linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_features_iot.h
-new file mode 100644
-index 000000000..a74d571a1
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_features_iot.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/phydm_features_iot.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/phydm_features_iot.h
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/phydm_features_iot.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/phydm_features_iot.h 2021-03-07 18:16:17.062956431 +0200
@@ -0,0 +1,174 @@
+/******************************************************************************
+ *
@@ -237710,11 +232992,9 @@ index 000000000..a74d571a1
+#endif
+
+#endif
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_features_win.h linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_features_win.h
-new file mode 100644
-index 000000000..8d2d13109
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_features_win.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/phydm_features_win.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/phydm_features_win.h
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/phydm_features_win.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/phydm_features_win.h 2021-03-07 18:16:17.062956431 +0200
@@ -0,0 +1,185 @@
+/******************************************************************************
+ *
@@ -237901,11 +233181,1369 @@ index 000000000..8d2d13109
+#endif
+
+#endif
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_hwconfig.c linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_hwconfig.c
-new file mode 100644
-index 000000000..4c4d9386e
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_hwconfig.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/phydm.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/phydm.h
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/phydm.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/phydm.h 2021-03-07 18:16:17.059956289 +0200
+@@ -0,0 +1,1356 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * The full GNU General Public License is included in this distribution in the
++ * file called LICENSE.
++ *
++ * Contact Information:
++ * wlanfae
++ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
++ * Hsinchu 300, Taiwan.
++ *
++ * Larry Finger
++ *
++ *****************************************************************************/
++
++#ifndef __HALDMOUTSRC_H__
++#define __HALDMOUTSRC_H__
++
++/*@============================================================*/
++/*@include files*/
++/*@============================================================*/
++/*PHYDM header*/
++#include "phydm_pre_define.h"
++#include "phydm_features.h"
++#include "phydm_dig.h"
++#ifdef CONFIG_PATH_DIVERSITY
++#include "phydm_pathdiv.h"
++#endif
++#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
++#include "phydm_antdiv.h"
++#endif
++
++#include "phydm_soml.h"
++
++#ifdef CONFIG_SMART_ANTENNA
++#include "phydm_smt_ant.h"
++#endif
++#ifdef CONFIG_ANT_DETECTION
++#include "phydm_antdect.h"
++#endif
++#include "phydm_rainfo.h"
++#ifdef CONFIG_DYNAMIC_TX_TWR
++#include "phydm_dynamictxpower.h"
++#endif
++#include "phydm_cfotracking.h"
++#include "phydm_adaptivity.h"
++#include "phydm_dfs.h"
++#include "phydm_ccx.h"
++#include "txbf/phydm_hal_txbf_api.h"
++#if (PHYDM_LA_MODE_SUPPORT == 1)
++#include "phydm_adc_sampling.h"
++#endif
++#ifdef CONFIG_PSD_TOOL
++#include "phydm_psd.h"
++#endif
++#ifdef PHYDM_PRIMARY_CCA
++#include "phydm_primary_cca.h"
++#endif
++#include "phydm_cck_pd.h"
++#include "phydm_rssi_monitor.h"
++#ifdef PHYDM_AUTO_DEGBUG
++#include "phydm_auto_dbg.h"
++#endif
++#include "phydm_math_lib.h"
++#include "phydm_noisemonitor.h"
++#include "phydm_api.h"
++#ifdef PHYDM_POWER_TRAINING_SUPPORT
++#include "phydm_pow_train.h"
++#endif
++#ifdef PHYDM_LNA_SAT_CHK_SUPPORT
++#include "phydm_lna_sat.h"
++#endif
++#ifdef PHYDM_PMAC_TX_SETTING_SUPPORT
++#include "phydm_pmac_tx_setting.h"
++#endif
++#ifdef PHYDM_MP_SUPPORT
++#include "phydm_mp.h"
++#endif
++#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
++ #include "phydm_beamforming.h"
++#endif
++
++#include "phydm_regtable.h"
++
++/*@HALRF header*/
++#include "halrf/halrf_iqk.h"
++#include "halrf/halrf_dpk.h"
++#include "halrf/halrf.h"
++#include "halrf/halrf_powertracking.h"
++#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
++ #include "halrf/halphyrf_ap.h"
++#elif(DM_ODM_SUPPORT_TYPE & (ODM_CE))
++ #include "halrf/halphyrf_ce.h"
++#elif (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
++ #include "halrf/halphyrf_win.h"
++#elif(DM_ODM_SUPPORT_TYPE & (ODM_IOT))
++ #include "halrf/halphyrf_iot.h"
++#endif
++
++extern const u16 phy_rate_table[28];
++
++/*@============================================================*/
++/*@Definition */
++/*@============================================================*/
++
++/* Traffic load decision */
++#define TRAFFIC_NO_TP 0
++#define TRAFFIC_ULTRA_LOW 1
++#define TRAFFIC_LOW 2
++#define TRAFFIC_MID 3
++#define TRAFFIC_HIGH 4
++
++#define NONE 0
++
++#if defined(DM_ODM_CE_MAC80211)
++#define MAX_2(x, y) \
++ __max2(typeof(x), typeof(y), \
++ x, y)
++#define __max2(t1, t2, x, y) ({ \
++ t1 m80211_max1 = (x); \
++ t2 m80211_max2 = (y); \
++ m80211_max1 > m80211_max2 ? m80211_max1 : m80211_max2; })
++
++#define MIN_2(x, y) \
++ __min2(typeof(x), typeof(y), \
++ x, y)
++#define __min2(t1, t2, x, y) ({ \
++ t1 m80211_min1 = (x); \
++ t2 m80211_min2 = (y); \
++ m80211_min1 < m80211_min2 ? m80211_min1 : m80211_min2; })
++
++#define DIFF_2(x, y) \
++ __diff2(typeof(x), typeof(y), \
++ x, y)
++#define __diff2(t1, t2, x, y) ({ \
++ t1 __d1 = (x); \
++ t2 __d2 = (y); \
++ (__d1 >= __d2) ? (__d1 - __d2) : (__d2 - __d1); })
++#else
++#define MAX_2(_x_, _y_) (((_x_) > (_y_)) ? (_x_) : (_y_))
++#define MIN_2(_x_, _y_) (((_x_) < (_y_)) ? (_x_) : (_y_))
++#define DIFF_2(_x_, _y_) ((_x_ >= _y_) ? (_x_ - _y_) : (_y_ - _x_))
++#endif
++
++#define IS_GREATER(_x_, _y_) (((_x_) >= (_y_)) ? true : false)
++#define IS_LESS(_x_, _y_) (((_x_) < (_y_)) ? true : false)
++
++#if defined(DM_ODM_CE_MAC80211)
++#define BYTE_DUPLICATE_2_DWORD(B0) ({ \
++ u32 __b_dup = (B0);\
++ (((__b_dup) << 24) | ((__b_dup) << 16) | ((__b_dup) << 8) | (__b_dup));\
++ })
++#else
++#define BYTE_DUPLICATE_2_DWORD(B0) \
++ (((B0) << 24) | ((B0) << 16) | ((B0) << 8) | (B0))
++#endif
++#define BYTE_2_DWORD(B3, B2, B1, B0) \
++ (((B3) << 24) | ((B2) << 16) | ((B1) << 8) | (B0))
++#define BIT_2_BYTE(B3, B2, B1, B0) \
++ (((B3) << 3) | ((B2) << 2) | ((B1) << 1) | (B0))
++
++/*@For cmn sta info*/
++#if defined(DM_ODM_CE_MAC80211)
++#define is_sta_active(sta) ({ \
++ struct cmn_sta_info *__sta = (sta); \
++ ((__sta) && (__sta->dm_ctrl & STA_DM_CTRL_ACTIVE)); \
++ })
++
++#define IS_FUNC_EN(name) ({ \
++ u8 *__is_func_name = (name); \
++ (__is_func_name) && (*__is_func_name); \
++ })
++#else
++#define is_sta_active(sta) ((sta) && (sta->dm_ctrl & STA_DM_CTRL_ACTIVE))
++
++#define IS_FUNC_EN(name) ((name) && (*name))
++#endif
++
++#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
++ #define PHYDM_WATCH_DOG_PERIOD 1 /*second*/
++#else
++ #define PHYDM_WATCH_DOG_PERIOD 2 /*second*/
++#endif
++
++#define PHY_HIST_SIZE 12
++
++/*@============================================================*/
++/*structure and define*/
++/*@============================================================*/
++
++#define dm_type_by_fw 0
++#define dm_type_by_driver 1
++
++#ifdef BB_RAM_SUPPORT
++
++struct phydm_bb_ram_per_sta {
++ /* @Reg0x1E84 for RAM I/O*/
++ boolean hw_igi_en;
++ boolean tx_pwr_offset0_en;
++ boolean tx_pwr_offset1_en;
++ /* @ macid from 0 to 63, above 63 => mapping to 63*/
++ u8 macid_addr;
++ /* @hw_igi value for paths after packet Tx in a period of time*/
++ u8 hw_igi;
++ /* @tx_pwr_offset0 offset for Tx power index*/
++ s8 tx_pwr_offset0;
++ s8 tx_pwr_offset1;
++
++};
++
++struct phydm_bb_ram_ctrl {
++ /*@ For 98F/14B/22C/12F, each TxAGC step will be 0.25dB*/
++ struct phydm_bb_ram_per_sta pram_sta_ctrl[ODM_ASSOCIATE_ENTRY_NUM];
++ /*------------ For table2 do not set power offset by macid --------*/
++ /* For type == 2'b10, 0x1e70[22:16] = tx_pwr_offset_reg0, 0x1e70[23] = enable */
++ boolean tx_pwr_offset_reg0_en;
++ u8 tx_pwr_offset_reg0;
++ /* For type == 2'b11, 0x1e70[30:24] = tx_pwr_offset_reg1, 0x1e70[31] = enable */
++ boolean tx_pwr_offset_reg1_en;
++ u8 tx_pwr_offset_reg1;
++};
++
++#endif
++
++struct phydm_phystatus_statistic {
++ /*@[CCK]*/
++ u32 rssi_cck_sum;
++ u32 rssi_cck_cnt;
++ /*@[OFDM]*/
++ u32 rssi_ofdm_sum;
++ u32 rssi_ofdm_cnt;
++ u32 evm_ofdm_sum;
++ u32 snr_ofdm_sum;
++ u16 evm_ofdm_hist[PHY_HIST_SIZE];
++ u16 snr_ofdm_hist[PHY_HIST_SIZE];
++ /*@[1SS]*/
++ u32 rssi_1ss_cnt;
++ u32 rssi_1ss_sum;
++ u32 evm_1ss_sum;
++ u32 snr_1ss_sum;
++ u16 evm_1ss_hist[PHY_HIST_SIZE];
++ u16 snr_1ss_hist[PHY_HIST_SIZE];
++ /*@[2SS]*/
++ #if (defined(PHYDM_COMPILE_ABOVE_2SS))
++ u32 rssi_2ss_cnt;
++ u32 rssi_2ss_sum[2];
++ u32 evm_2ss_sum[2];
++ u32 snr_2ss_sum[2];
++ u16 evm_2ss_hist[2][PHY_HIST_SIZE];
++ u16 snr_2ss_hist[2][PHY_HIST_SIZE];
++ #endif
++ /*@[3SS]*/
++ #if (defined(PHYDM_COMPILE_ABOVE_3SS))
++ u32 rssi_3ss_cnt;
++ u32 rssi_3ss_sum[3];
++ u32 evm_3ss_sum[3];
++ u32 snr_3ss_sum[3];
++ u16 evm_3ss_hist[3][PHY_HIST_SIZE];
++ u16 snr_3ss_hist[3][PHY_HIST_SIZE];
++ #endif
++ /*@[4SS]*/
++ #if (defined(PHYDM_COMPILE_ABOVE_4SS))
++ u32 rssi_4ss_cnt;
++ u32 rssi_4ss_sum[4];
++ u32 evm_4ss_sum[4];
++ u32 snr_4ss_sum[4];
++ u16 evm_4ss_hist[4][PHY_HIST_SIZE];
++ u16 snr_4ss_hist[4][PHY_HIST_SIZE];
++ #endif
++};
++
++struct phydm_phystatus_avg {
++ /*@[CCK]*/
++ u8 rssi_cck_avg;
++ /*@[OFDM]*/
++ u8 rssi_ofdm_avg;
++ u8 evm_ofdm_avg;
++ u8 snr_ofdm_avg;
++ /*@[1SS]*/
++ u8 rssi_1ss_avg;
++ u8 evm_1ss_avg;
++ u8 snr_1ss_avg;
++ /*@[2SS]*/
++ #if (defined(PHYDM_COMPILE_ABOVE_2SS))
++ u8 rssi_2ss_avg[2];
++ u8 evm_2ss_avg[2];
++ u8 snr_2ss_avg[2];
++ #endif
++ /*@[3SS]*/
++ #if (defined(PHYDM_COMPILE_ABOVE_3SS))
++ u8 rssi_3ss_avg[3];
++ u8 evm_3ss_avg[3];
++ u8 snr_3ss_avg[3];
++ #endif
++ /*@[4SS]*/
++ #if (defined(PHYDM_COMPILE_ABOVE_4SS))
++ u8 rssi_4ss_avg[4];
++ u8 evm_4ss_avg[4];
++ u8 snr_4ss_avg[4];
++ #endif
++};
++
++struct odm_phy_dbg_info {
++ /*@ODM Write,debug info*/
++ u32 num_qry_phy_status_cck;
++ u32 num_qry_phy_status_ofdm;
++#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1) || (defined(PHYSTS_3RD_TYPE_SUPPORT))
++ u32 num_qry_mu_pkt;
++ u32 num_qry_bf_pkt;
++ u16 num_mu_vht_pkt[VHT_RATE_NUM];
++ boolean is_ldpc_pkt;
++ boolean is_stbc_pkt;
++ u8 num_of_ppdu[4];
++ u8 gid_num[4];
++#endif
++ u32 condi_num; /*@condition number U(18,4)*/
++ u8 condi_num_cdf[CN_CNT_MAX];
++ u8 num_qry_beacon_pkt;
++ u8 beacon_cnt_in_period; /*@beacon cnt within watchdog period*/
++ u8 beacon_phy_rate;
++ u8 show_phy_sts_all_pkt; /*@Show phy status witch not match BSSID*/
++ u16 show_phy_sts_max_cnt; /*@show number of phy-status row data per PHYDM watchdog*/
++ u16 show_phy_sts_cnt;
++ u16 num_qry_legacy_pkt[LEGACY_RATE_NUM];
++ u16 num_qry_ht_pkt[HT_RATE_NUM];
++ u16 num_qry_pkt_sc_20m[LOW_BW_RATE_NUM]; /*@20M SC*/
++ boolean ht_pkt_not_zero;
++ boolean low_bw_20_occur;
++ #if ODM_IC_11AC_SERIES_SUPPORT || defined(PHYDM_IC_JGR3_SERIES_SUPPORT)
++ u16 num_qry_vht_pkt[VHT_RATE_NUM];
++ u16 num_qry_pkt_sc_40m[LOW_BW_RATE_NUM]; /*@40M SC*/
++ boolean vht_pkt_not_zero;
++ boolean low_bw_40_occur;
++ #endif
++ u16 snr_hist_th[PHY_HIST_SIZE - 1];
++ u16 evm_hist_th[PHY_HIST_SIZE - 1];
++ #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
++ s16 cfo_tail[4]; /* per-path's cfo_tail */
++ #endif
++ struct phydm_phystatus_statistic physts_statistic_info;
++ struct phydm_phystatus_avg phystatus_statistic_avg;
++};
++
++enum odm_cmninfo {
++ /*@Fixed value*/
++ /*@-----------HOOK BEFORE REG INIT-----------*/
++ ODM_CMNINFO_PLATFORM = 0,
++ ODM_CMNINFO_ABILITY,
++ ODM_CMNINFO_INTERFACE,
++ ODM_CMNINFO_MP_TEST_CHIP,
++ ODM_CMNINFO_IC_TYPE,
++ ODM_CMNINFO_CUT_VER,
++ ODM_CMNINFO_FAB_VER,
++ ODM_CMNINFO_FW_VER,
++ ODM_CMNINFO_FW_SUB_VER,
++ ODM_CMNINFO_RF_TYPE,
++ ODM_CMNINFO_RFE_TYPE,
++ ODM_CMNINFO_DPK_EN,
++ ODM_CMNINFO_BOARD_TYPE,
++ ODM_CMNINFO_PACKAGE_TYPE,
++ ODM_CMNINFO_EXT_LNA,
++ ODM_CMNINFO_5G_EXT_LNA,
++ ODM_CMNINFO_EXT_PA,
++ ODM_CMNINFO_5G_EXT_PA,
++ ODM_CMNINFO_GPA,
++ ODM_CMNINFO_APA,
++ ODM_CMNINFO_GLNA,
++ ODM_CMNINFO_ALNA,
++ ODM_CMNINFO_TDMA,
++ ODM_CMNINFO_EXT_TRSW,
++ ODM_CMNINFO_EXT_LNA_GAIN,
++ ODM_CMNINFO_PATCH_ID,
++ ODM_CMNINFO_BINHCT_TEST,
++ ODM_CMNINFO_BWIFI_TEST,
++ ODM_CMNINFO_SMART_CONCURRENT,
++ ODM_CMNINFO_CONFIG_BB_RF,
++ ODM_CMNINFO_IQKPAOFF,
++ ODM_CMNINFO_HUBUSBMODE,
++ ODM_CMNINFO_FWDWRSVDPAGEINPROGRESS,
++ ODM_CMNINFO_TX_TP,
++ ODM_CMNINFO_RX_TP,
++ ODM_CMNINFO_SOUNDING_SEQ,
++ ODM_CMNINFO_REGRFKFREEENABLE,
++ ODM_CMNINFO_RFKFREEENABLE,
++ ODM_CMNINFO_NORMAL_RX_PATH_CHANGE,
++ ODM_CMNINFO_EFUSE0X3D8,
++ ODM_CMNINFO_EFUSE0X3D7,
++ ODM_CMNINFO_SOFT_AP_SPECIAL_SETTING,
++ ODM_CMNINFO_X_CAP_SETTING,
++ ODM_CMNINFO_ADVANCE_OTA,
++ ODM_CMNINFO_HP_HWID,
++ /*@-----------HOOK BEFORE REG INIT-----------*/
++
++ /*@Dynamic value:*/
++
++ /*@--------- POINTER REFERENCE-----------*/
++ ODM_CMNINFO_TX_UNI,
++ ODM_CMNINFO_RX_UNI,
++ ODM_CMNINFO_BAND,
++ ODM_CMNINFO_SEC_CHNL_OFFSET,
++ ODM_CMNINFO_SEC_MODE,
++ ODM_CMNINFO_BW,
++ ODM_CMNINFO_CHNL,
++ ODM_CMNINFO_FORCED_RATE,
++ ODM_CMNINFO_ANT_DIV,
++ ODM_CMNINFO_PATH_DIV,
++ ODM_CMNINFO_ADAPTIVE_SOML,
++ ODM_CMNINFO_ADAPTIVITY,
++ ODM_CMNINFO_SCAN,
++ ODM_CMNINFO_POWER_SAVING,
++ ODM_CMNINFO_ONE_PATH_CCA,
++ ODM_CMNINFO_DRV_STOP,
++ ODM_CMNINFO_PNP_IN,
++ ODM_CMNINFO_INIT_ON,
++ ODM_CMNINFO_ANT_TEST,
++ ODM_CMNINFO_NET_CLOSED,
++ ODM_CMNINFO_P2P_LINK,
++ ODM_CMNINFO_FCS_MODE,
++ ODM_CMNINFO_IS1ANTENNA,
++ ODM_CMNINFO_RFDEFAULTPATH,
++ ODM_CMNINFO_DFS_MASTER_ENABLE,
++ ODM_CMNINFO_FORCE_TX_ANT_BY_TXDESC,
++ ODM_CMNINFO_SET_S0S1_DEFAULT_ANTENNA,
++ ODM_CMNINFO_SOFT_AP_MODE,
++ ODM_CMNINFO_MP_MODE,
++ ODM_CMNINFO_INTERRUPT_MASK,
++ ODM_CMNINFO_BB_OPERATION_MODE,
++ ODM_CMNINFO_BF_ANTDIV_DECISION,
++ /*@--------- POINTER REFERENCE-----------*/
++
++ /*@------------CALL BY VALUE-------------*/
++ ODM_CMNINFO_WIFI_DIRECT,
++ ODM_CMNINFO_WIFI_DISPLAY,
++ ODM_CMNINFO_LINK_IN_PROGRESS,
++ ODM_CMNINFO_LINK,
++ ODM_CMNINFO_CMW500LINK,
++ ODM_CMNINFO_STATION_STATE,
++ ODM_CMNINFO_RSSI_MIN,
++ ODM_CMNINFO_RSSI_MIN_BY_PATH,
++ ODM_CMNINFO_DBG_COMP,
++ ODM_CMNINFO_RA_THRESHOLD_HIGH, /*to be removed*/
++ ODM_CMNINFO_RA_THRESHOLD_LOW, /*to be removed*/
++ ODM_CMNINFO_RF_ANTENNA_TYPE,
++ ODM_CMNINFO_WITH_EXT_ANTENNA_SWITCH,
++ ODM_CMNINFO_BE_FIX_TX_ANT,
++ ODM_CMNINFO_BT_ENABLED,
++ ODM_CMNINFO_BT_HS_CONNECT_PROCESS,
++ ODM_CMNINFO_BT_HS_RSSI,
++ ODM_CMNINFO_BT_OPERATION,
++ ODM_CMNINFO_BT_LIMITED_DIG,
++ ODM_CMNINFO_AP_TOTAL_NUM,
++ ODM_CMNINFO_POWER_TRAINING,
++ ODM_CMNINFO_DFS_REGION_DOMAIN,
++ ODM_CMNINFO_BT_CONTINUOUS_TURN,
++ /*@------------CALL BY VALUE-------------*/
++
++ /*@Dynamic ptr array hook itms.*/
++ ODM_CMNINFO_STA_STATUS,
++ ODM_CMNINFO_MAX,
++
++};
++
++enum phydm_rfe_bb_source_sel {
++ PAPE_2G = 0,
++ PAPE_5G = 1,
++ LNA0N_2G = 2,
++ LNAON_5G = 3,
++ TRSW = 4,
++ TRSW_B = 5,
++ GNT_BT = 6,
++ ZERO = 7,
++ ANTSEL_0 = 8,
++ ANTSEL_1 = 9,
++ ANTSEL_2 = 0xa,
++ ANTSEL_3 = 0xb,
++ ANTSEL_4 = 0xc,
++ ANTSEL_5 = 0xd,
++ ANTSEL_6 = 0xe,
++ ANTSEL_7 = 0xf
++};
++
++enum phydm_info_query {
++ PHYDM_INFO_FA_OFDM,
++ PHYDM_INFO_FA_CCK,
++ PHYDM_INFO_FA_TOTAL,
++ PHYDM_INFO_CCA_OFDM,
++ PHYDM_INFO_CCA_CCK,
++ PHYDM_INFO_CCA_ALL,
++ PHYDM_INFO_CRC32_OK_VHT,
++ PHYDM_INFO_CRC32_OK_HT,
++ PHYDM_INFO_CRC32_OK_LEGACY,
++ PHYDM_INFO_CRC32_OK_CCK,
++ PHYDM_INFO_CRC32_ERROR_VHT,
++ PHYDM_INFO_CRC32_ERROR_HT,
++ PHYDM_INFO_CRC32_ERROR_LEGACY,
++ PHYDM_INFO_CRC32_ERROR_CCK,
++ PHYDM_INFO_EDCCA_FLAG,
++ PHYDM_INFO_OFDM_ENABLE,
++ PHYDM_INFO_CCK_ENABLE,
++ PHYDM_INFO_CRC32_OK_HT_AGG,
++ PHYDM_INFO_CRC32_ERROR_HT_AGG,
++ PHYDM_INFO_DBG_PORT_0,
++ PHYDM_INFO_CURR_IGI,
++ PHYDM_INFO_RSSI_MIN,
++ PHYDM_INFO_RSSI_MAX,
++ PHYDM_INFO_CLM_RATIO,
++ PHYDM_INFO_NHM_RATIO,
++};
++
++enum phydm_api {
++ PHYDM_API_NBI = 1,
++ PHYDM_API_CSI_MASK = 2,
++};
++
++enum phydm_func_idx { /*@F_XXX = PHYDM XXX function*/
++
++ F00_DIG = 0,
++ F01_RA_MASK = 1,
++ F02_DYN_TXPWR = 2,
++ F03_FA_CNT = 3,
++ F04_RSSI_MNTR = 4,
++ F05_CCK_PD = 5,
++ F06_ANT_DIV = 6,
++ F07_SMT_ANT = 7,
++ F08_PWR_TRAIN = 8,
++ F09_RA = 9,
++ F10_PATH_DIV = 10,
++ F11_DFS = 11,
++ F12_DYN_ARFR = 12,
++ F13_ADPTVTY = 13,
++ F14_CFO_TRK = 14,
++ F15_ENV_MNTR = 15,
++ F16_PRI_CCA = 16,
++ F17_ADPTV_SOML = 17,
++ F18_LNA_SAT_CHK = 18,
++};
++
++/*@=[PHYDM supportability]==========================================*/
++enum odm_ability {
++ ODM_BB_DIG = BIT(F00_DIG),
++ ODM_BB_RA_MASK = BIT(F01_RA_MASK),
++ ODM_BB_DYNAMIC_TXPWR = BIT(F02_DYN_TXPWR),
++ ODM_BB_FA_CNT = BIT(F03_FA_CNT),
++ ODM_BB_RSSI_MONITOR = BIT(F04_RSSI_MNTR),
++ ODM_BB_CCK_PD = BIT(F05_CCK_PD),
++ ODM_BB_ANT_DIV = BIT(F06_ANT_DIV),
++ ODM_BB_SMT_ANT = BIT(F07_SMT_ANT),
++ ODM_BB_PWR_TRAIN = BIT(F08_PWR_TRAIN),
++ ODM_BB_RATE_ADAPTIVE = BIT(F09_RA),
++ ODM_BB_PATH_DIV = BIT(F10_PATH_DIV),
++ ODM_BB_DFS = BIT(F11_DFS),
++ ODM_BB_DYNAMIC_ARFR = BIT(F12_DYN_ARFR),
++ ODM_BB_ADAPTIVITY = BIT(F13_ADPTVTY),
++ ODM_BB_CFO_TRACKING = BIT(F14_CFO_TRK),
++ ODM_BB_ENV_MONITOR = BIT(F15_ENV_MNTR),
++ ODM_BB_PRIMARY_CCA = BIT(F16_PRI_CCA),
++ ODM_BB_ADAPTIVE_SOML = BIT(F17_ADPTV_SOML),
++ ODM_BB_LNA_SAT_CHK = BIT(F18_LNA_SAT_CHK),
++};
++
++/*@=[PHYDM Debug Component]=====================================*/
++enum phydm_dbg_comp {
++ /*@BB Driver Functions*/
++ DBG_DIG = BIT(F00_DIG),
++ DBG_RA_MASK = BIT(F01_RA_MASK),
++ DBG_DYN_TXPWR = BIT(F02_DYN_TXPWR),
++ DBG_FA_CNT = BIT(F03_FA_CNT),
++ DBG_RSSI_MNTR = BIT(F04_RSSI_MNTR),
++ DBG_CCKPD = BIT(F05_CCK_PD),
++ DBG_ANT_DIV = BIT(F06_ANT_DIV),
++ DBG_SMT_ANT = BIT(F07_SMT_ANT),
++ DBG_PWR_TRAIN = BIT(F08_PWR_TRAIN),
++ DBG_RA = BIT(F09_RA),
++ DBG_PATH_DIV = BIT(F10_PATH_DIV),
++ DBG_DFS = BIT(F11_DFS),
++ DBG_DYN_ARFR = BIT(F12_DYN_ARFR),
++ DBG_ADPTVTY = BIT(F13_ADPTVTY),
++ DBG_CFO_TRK = BIT(F14_CFO_TRK),
++ DBG_ENV_MNTR = BIT(F15_ENV_MNTR),
++ DBG_PRI_CCA = BIT(F16_PRI_CCA),
++ DBG_ADPTV_SOML = BIT(F17_ADPTV_SOML),
++ DBG_LNA_SAT_CHK = BIT(F18_LNA_SAT_CHK),
++ /*BIT(19)*/
++ /*Neet to re-arrange*/
++ DBG_PHY_STATUS = BIT(20),
++ DBG_TMP = BIT(21),
++ DBG_FW_TRACE = BIT(22),
++ DBG_TXBF = BIT(23),
++ DBG_COMMON_FLOW = BIT(24),
++ DBG_COMP_MCC = BIT(25),
++ /*BIT(26)*/
++ DBG_DM_SUMMARY = BIT(27),
++ ODM_PHY_CONFIG = BIT(28),
++ ODM_COMP_INIT = BIT(29),
++ DBG_CMN = BIT(30),/*@common*/
++ ODM_COMP_API = BIT(31)
++};
++
++/*@=========================================================*/
++
++/*@ODM_CMNINFO_ONE_PATH_CCA*/
++enum odm_cca_path {
++ ODM_CCA_2R = 0,
++ ODM_CCA_1R_A = 1,
++ ODM_CCA_1R_B = 2,
++};
++
++enum phy_reg_pg_type {
++ PHY_REG_PG_RELATIVE_VALUE = 0,
++ PHY_REG_PG_EXACT_VALUE = 1
++};
++
++enum phydm_offload_ability {
++ PHYDM_PHY_PARAM_OFFLOAD = BIT(0),
++ PHYDM_RF_IQK_OFFLOAD = BIT(1),
++};
++
++struct phydm_pause_lv {
++ s8 lv_dig;
++ s8 lv_cckpd;
++ s8 lv_antdiv;
++ s8 lv_adapt;
++ s8 lv_adsl;
++};
++
++struct phydm_func_poiner {
++ void (*pause_phydm_handler)(void *dm_void, u32 *val_buf, u8 val_len);
++};
++
++struct pkt_process_info {
++ u8 phystatus_smp_mode_en; /*@send phystatus every sampling time*/
++ u8 pre_ppdu_cnt;
++ u8 lna_idx;
++ u8 vga_idx;
++};
++
++#ifdef ODM_CONFIG_BT_COEXIST
++struct phydm_bt_info {
++ boolean is_bt_enabled; /*@BT is enabled*/
++ boolean is_bt_connect_process; /*@BT HS is under connection progress.*/
++ u8 bt_hs_rssi; /*@BT HS mode wifi rssi value.*/
++ boolean is_bt_hs_operation; /*@BT HS mode is under progress*/
++ boolean is_bt_limited_dig; /*@BT is busy.*/
++};
++#endif
++
++struct phydm_iot_center {
++ boolean is_linked_cmw500;
++ u8 win_patch_id; /*@Customer ID*/
++ u32 phydm_patch_id;
++
++};
++
++#if (RTL8822B_SUPPORT == 1)
++struct drp_rtl8822b_struct {
++ enum bb_path path_judge;
++ u16 path_a_cck_fa;
++ u16 path_b_cck_fa;
++};
++#endif
++
++#ifdef CONFIG_MCC_DM
++#define MCC_DM_REG_NUM 32
++struct _phydm_mcc_dm_ {
++ u8 mcc_pre_status;
++ u8 mcc_reg_id[MCC_DM_REG_NUM];
++ u16 mcc_dm_reg[MCC_DM_REG_NUM];
++ u8 mcc_dm_val[MCC_DM_REG_NUM][2];
++ /*mcc DIG*/
++ u8 mcc_rssi[2];
++ /*u8 mcc_igi[2];*/
++
++ /* need to be config by driver*/
++ u8 mcc_status;
++ u8 sta_macid[2][NUM_STA];
++ u16 mcc_rf_channel[2];
++
++};
++#endif
++
++
++#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
++ #if (RT_PLATFORM != PLATFORM_LINUX)
++ typedef
++ #endif
++
++struct dm_struct {
++#else/*for AP, CE Team*/
++struct dm_struct {
++#endif
++ /*@Add for different team use temporarily*/
++ void *adapter; /*@For CE/NIC team*/
++ struct rtl8192cd_priv *priv; /*@For AP team*/
++ boolean odm_ready;
++ enum phy_reg_pg_type phy_reg_pg_value_type;
++ u8 phy_reg_pg_version;
++ u64 support_ability; /*@PHYDM function Supportability*/
++ u64 pause_ability; /*@PHYDM function pause Supportability*/
++ u64 debug_components;
++ u8 cmn_dbg_msg_period;
++ u8 cmn_dbg_msg_cnt;
++ u32 fw_debug_components;
++ u32 num_qry_phy_status_all; /*@CCK + OFDM*/
++ u32 last_num_qry_phy_status_all;
++ u32 rx_pwdb_ave;
++ boolean is_init_hw_info_by_rfe;
++
++ /*@------ ODM HANDLE, DRIVER NEEDS NOT TO HOOK------*/
++ boolean is_cck_high_power;
++ u8 rf_path_rx_enable;
++ /*@------ ODM HANDLE, DRIVER NEEDS NOT TO HOOK------*/
++
++ /* @COMMON INFORMATION */
++
++ /*@Init value*/
++ /*@-----------HOOK BEFORE REG INIT-----------*/
++
++ u8 support_platform; /*@PHYDM Platform info WIN/AP/CE = 1/2/3 */
++ u8 normal_rx_path;
++ boolean brxagcswitch; /* @for rx AGC table switch in Microsoft case */
++ u8 support_interface; /*@PHYDM PCIE/USB/SDIO = 1/2/3*/
++ u32 support_ic_type; /*@PHYDM supported IC*/
++ u8 ic_ip_series; /*N/AC/JGR3*/
++ enum phydm_phy_sts_type ic_phy_sts_type; /*@Type1/type2/type3*/
++ u8 cut_version; /*@cut version TestChip/A-cut/B-cut... = 0/1/2/3/...*/
++ u8 fab_version; /*@Fab version TSMC/UMC = 0/1*/
++ u8 fw_version;
++ u8 fw_sub_version;
++ u8 rf_type; /*@RF type 4T4R/3T3R/2T2R/1T2R/1T1R/...*/
++ u8 rfe_type;
++ u8 board_type;
++ u8 package_type;
++ u16 type_glna;
++ u16 type_gpa;
++ u16 type_alna;
++ u16 type_apa;
++ u8 ext_lna; /*@with 2G external LNA NO/Yes = 0/1*/
++ u8 ext_lna_5g; /*@with 5G external LNA NO/Yes = 0/1*/
++ u8 ext_pa; /*@with 2G external PNA NO/Yes = 0/1*/
++ u8 ext_pa_5g; /*@with 5G external PNA NO/Yes = 0/1*/
++ u8 efuse0x3d7; /*@with Efuse number*/
++ u8 efuse0x3d8;
++ u8 ext_trsw; /*@with external TRSW NO/Yes = 0/1*/
++ u8 ext_lna_gain; /*@gain of external lna*/
++ boolean is_in_hct_test;
++ u8 wifi_test;
++ boolean is_dual_mac_smart_concurrent;
++ u32 bk_support_ability; /*SD4 only*/
++ u8 with_extenal_ant_switch;
++ /*@cck agc relative*/
++ boolean cck_new_agc;
++ s8 cck_lna_gain_table[8];
++ /*@-------------------------------------*/
++ u32 phydm_sys_up_time;
++ u8 num_rf_path; /*@ex: 8821C=1, 8192E=2, 8814B=4*/
++ u32 soft_ap_special_setting;
++ s8 s8_dummy;
++ u8 u8_dummy;
++ u16 u16_dummy;
++ u32 u32_dummy;
++ u8 rfe_hwsetting_band;
++ u8 p_advance_ota;
++ boolean hp_hw_id;
++ boolean BOOLEAN_temp;
++ boolean is_dfs_band;
++ u8 is_rx_blocking_en;
++ u16 fw_offload_ability;
++/*@-----------HOOK BEFORE REG INIT-----------*/
++/*@===========================================================*/
++/*@====[ CALL BY Reference ]=========================================*/
++/*@===========================================================*/
++
++ u64 *num_tx_bytes_unicast; /*@TX Unicast byte cnt*/
++ u64 *num_rx_bytes_unicast; /*@RX Unicast byte cnt*/
++ u8 *band_type; /*@2.4G/5G = 0/1*/
++ u8 *sec_ch_offset; /*@Secondary channel offset don't_care/below/above = 0/1/2*/
++ u8 *security; /*@security mode Open/WEP/AES/TKIP = 0/1/2/3*/
++ u8 *band_width; /*@20M/40M/80M = 0/1/2*/
++ u8 *channel; /*@central CH number*/
++ boolean *is_scan_in_process;
++ boolean *is_power_saving;
++ boolean *is_tdma;
++ u8 *one_path_cca; /*@CCA path 2-path/path-A/path-B = 0/1/2; using enum odm_cca_path.*/
++ u8 *antenna_test;
++ boolean *is_net_closed;
++ boolean *is_fcs_mode_enable;
++ /*@--------- For 8723B IQK-------------------------------------*/
++ boolean *is_1_antenna;
++ u8 *rf_default_path; /* @0:S1, 1:S0 */
++ /*@-----------------------------------------------------------*/
++
++ u16 *forced_data_rate;
++ u8 *enable_antdiv;
++ u8 *enable_pathdiv;
++ u8 *en_adap_soml;
++ u8 *enable_adaptivity;
++ u8 *hub_usb_mode; /*@1:USB2.0, 2:USB3.0*/
++ boolean *is_fw_dw_rsvd_page_in_progress;
++ u32 *current_tx_tp;
++ u32 *current_rx_tp;
++ u8 *sounding_seq;
++ u32 *soft_ap_mode;
++ u8 *mp_mode;
++ u32 *interrupt_mask;
++ u8 *bb_op_mode;
++/*@===========================================================*/
++/*@====[ CALL BY VALUE ]===========================================*/
++/*@===========================================================*/
++
++ u8 disable_phydm_watchdog;
++ boolean is_link_in_process;
++ boolean is_wifi_direct;
++ boolean is_wifi_display;
++ boolean is_linked;
++ boolean bsta_state;
++ u8 rssi_min;
++ u8 rssi_min_macid;
++ u8 pre_rssi_min;
++ u8 rssi_max;
++ u8 rssi_max_macid;
++ u8 rssi_min_by_path;
++ boolean is_one_entry_only;
++ u32 one_entry_macid;
++ u32 one_entry_tp;
++ u32 pre_one_entry_tp;
++ u8 pre_number_linked_client;
++ u8 number_linked_client;
++ u8 pre_number_active_client;
++ u8 number_active_client;
++ boolean is_disable_phy_api;
++ u8 rssi_a;
++ u8 rssi_b;
++ u8 rssi_c;
++ u8 rssi_d;
++ s8 rxsc_80;
++ s8 rxsc_40;
++ s8 rxsc_20;
++ s8 rxsc_l;
++ u64 rssi_trsw;
++ u64 rssi_trsw_h;
++ u64 rssi_trsw_l;
++ u64 rssi_trsw_iso;
++ u8 tx_ant_status;
++ u8 rx_ant_status;
++ u8 cck_lna_idx;
++ u8 cck_vga_idx;
++ u8 curr_station_id;
++ u8 ofdm_agc_idx[4];
++ u8 rx_rate;
++ u8 rate_ss;
++ u8 tx_rate;
++ u8 linked_interval;
++ u8 pre_channel;
++ u32 txagc_offset_value_a;
++ boolean is_txagc_offset_positive_a;
++ u32 txagc_offset_value_b;
++ boolean is_txagc_offset_positive_b;
++ u8 ap_total_num;
++ /*@[traffic]*/
++ u8 traffic_load;
++ u8 pre_traffic_load;
++ u32 tx_tp; /*@Mbps*/
++ u32 rx_tp; /*@Mbps*/
++ u32 total_tp; /*@Mbps*/
++ u8 txrx_state_all; /*@0:tx, 1:rx, 2:bi-dir*/
++ u64 cur_tx_ok_cnt;
++ u64 cur_rx_ok_cnt;
++ u64 last_tx_ok_cnt;
++ u64 last_rx_ok_cnt;
++ u16 consecutive_idlel_time; /*@unit: second*/
++ /*@---------------------------*/
++ boolean is_bb_swing_offset_positive_a;
++ boolean is_bb_swing_offset_positive_b;
++
++ /*@[DIG]*/
++ boolean MPDIG_2G; /*off MPDIG*/
++ u8 times_2g; /*@for MP DIG*/
++ u8 force_igi; /*@for debug*/
++
++ /*@[TDMA-DIG]*/
++ u8 tdma_dig_timer_ms;
++ u8 tdma_dig_state_number;
++ u8 tdma_dig_low_upper_bond;
++ u8 force_tdma_low_igi;
++ u8 force_tdma_high_igi;
++ u8 fix_expire_to_zero;
++ boolean original_dig_restore;
++ /*@---------------------------*/
++
++ /*@[AntDiv]*/
++ u8 ant_div_type;
++ u8 antdiv_rssi;
++ u8 fat_comb_a;
++ u8 fat_comb_b;
++ u8 antdiv_intvl;
++ u8 ant_type;
++ u8 ant_type2;
++ u8 pre_ant_type;
++ u8 pre_ant_type2;
++ u8 antdiv_period;
++ u8 evm_antdiv_period;
++ u8 antdiv_select;
++ u8 antdiv_train_num; /*@training time for each antenna in EVM method*/
++ u8 stop_antdiv_rssi_th;
++ u16 stop_antdiv_tp_diff_th;
++ u16 stop_antdiv_tp_th;
++ u8 antdiv_tp_period;
++ u16 tp_active_th;
++ u8 tp_active_occur;
++ u8 path_select;
++ u8 antdiv_evm_en;
++ u8 bdc_holdstate;
++ u8 antdiv_counter;
++ /*@---------------------------*/
++
++ u8 ndpa_period;
++ boolean h2c_rarpt_connect;
++ boolean cck_agc_report_type; /*@1:4bit LNA, 0:3bit LNA */
++ u8 print_agc;
++ u8 la_mode;
++ /*@---8821C Antenna and RF Set BTG/WLG/WLA Select---------------*/
++ u8 current_rf_set_8821c;
++ u8 default_rf_set_8821c;
++ u8 current_ant_num_8821c;
++ u8 default_ant_num_8821c;
++ u8 rfe_type_expand;
++ /*@-----------------------------------------------------------*/
++ /*@---For Adaptivtiy---------------------------------------------*/
++ s8 TH_L2H_default;
++ s8 th_edcca_hl_diff_default;
++ s8 th_l2h_ini;
++ s8 th_edcca_hl_diff;
++ boolean carrier_sense_enable;
++ /*@-----------------------------------------------------------*/
++
++ u8 pre_dbg_priority;
++ u8 nbi_set_result;
++ u8 c2h_cmd_start;
++ u8 fw_debug_trace[60];
++ u8 pre_c2h_seq;
++ boolean fw_buff_is_enpty;
++ u32 data_frame_num;
++
++ /*@--- for noise detection ---------------------------------------*/
++ boolean is_noisy_state;
++ boolean noisy_decision; /*@b_noisy*/
++ boolean pre_b_noisy;
++ u32 noisy_decision_smooth;
++ /*@-----------------------------------------------------------*/
++
++ /*@--- for MCC ant weighting ------------------------------------*/
++ boolean is_stop_dym_ant_weighting;
++ /*@-----------------------------------------------------------*/
++
++ boolean is_disable_dym_ecs;
++ boolean is_disable_dym_ant_weighting;
++ struct cmn_sta_info *phydm_sta_info[ODM_ASSOCIATE_ENTRY_NUM];
++ u8 phydm_macid_table[ODM_ASSOCIATE_ENTRY_NUM];/*@sta_idx = phydm_macid_table[HW_macid]*/
++
++#if (RATE_ADAPTIVE_SUPPORT == 1)
++ u16 currmin_rpt_time;
++ struct _phydm_txstatistic_ hw_stats;
++ struct _odm_ra_info_ ra_info[ODM_ASSOCIATE_ENTRY_NUM];
++/*Use mac_id as array index. STA mac_id=0*/
++/*VWiFi Client mac_id={1, ODM_ASSOCIATE_ENTRY_NUM-1} //YJ,add,120119*/
++#endif
++ /*@2012/02/14 MH Add to share 88E ra with other SW team*/
++ /*We need to colelct all support abilit to a proper area.*/
++ boolean ra_support88e;
++ boolean *is_driver_stopped;
++ boolean *is_driver_is_going_to_pnp_set_power_sleep;
++ boolean *pinit_adpt_in_progress;
++ boolean is_user_assign_level;
++ u8 RSSI_BT; /*@come from BT*/
++
++ /*@---PSD Relative ---------------------------------------------*/
++ boolean is_psd_in_process;
++ boolean is_psd_active;
++ /*@-----------------------------------------------------------*/
++
++ boolean bsomlenabled; /* @D-SoML control */
++ boolean bhtstfdisabled; /* @dynamic HTSTF gain control*/
++ u32 n_iqk_cnt;
++ u32 n_iqk_ok_cnt;
++ u32 n_iqk_fail_cnt;
++
++#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
++ boolean config_bbrf;
++#endif
++ boolean is_disable_power_training;
++ boolean is_bt_continuous_turn;
++ u8 enhance_pwr_th[3];
++ u8 set_pwr_th[3];
++ /*@----------Dyn Tx Pwr ---------------------------------------*/
++#ifdef BB_RAM_SUPPORT
++ struct phydm_bb_ram_ctrl p_bb_ram_ctrl;
++#endif
++ u8 dynamic_tx_high_power_lvl;
++ void (*fill_desc_dyntxpwr)(void *dm, u8 *desc, u8 dyn_tx_power);
++ u8 last_dtp_lvl;
++ u8 min_power_index;
++ u32 tx_agc_ofdm_18_6;
++ /*-------------------------------------------------------------*/
++ u8 rx_pkt_type;
++
++#ifdef CONFIG_PHYDM_DFS_MASTER
++ u8 dfs_region_domain;
++ u8 *dfs_master_enabled;
++ /*@---phydm_radar_detect_with_dbg_parm start --------------------*/
++ u8 radar_detect_dbg_parm_en;
++ u32 radar_detect_reg_918;
++ u32 radar_detect_reg_91c;
++ u32 radar_detect_reg_920;
++ u32 radar_detect_reg_924;
++ u32 radar_detect_reg_f54;
++ u32 radar_detect_reg_f58;
++ u32 radar_detect_reg_f5c;
++ u32 radar_detect_reg_f70;
++ u32 radar_detect_reg_f74;
++/*@-----------------------------------------------------------*/
++#endif
++
++/*@=== PHYDM Timer ========================================== (start)*/
++
++ struct phydm_timer_list mpt_dig_timer;
++ struct phydm_timer_list fast_ant_training_timer;
++#ifdef ODM_EVM_ENHANCE_ANTDIV
++ struct phydm_timer_list evm_fast_ant_training_timer;
++#endif
++#ifdef PHYDM_TDMA_DIG_SUPPORT
++ struct phydm_timer_list tdma_dig_timer;
++#endif
++ struct phydm_timer_list sbdcnt_timer;
++
++/*@=== PHYDM Workitem ======================================= (start)*/
++
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++#if USE_WORKITEM
++ RT_WORK_ITEM fast_ant_training_workitem;
++ RT_WORK_ITEM ra_rpt_workitem;
++ RT_WORK_ITEM sbdcnt_workitem;
++ RT_WORK_ITEM phydm_evm_antdiv_workitem;
++#endif
++#endif
++
++/*@=== PHYDM Structure ======================================== (start)*/
++ struct phydm_func_poiner phydm_func_handler;
++ struct phydm_iot_center iot_table;
++
++#ifdef ODM_CONFIG_BT_COEXIST
++ struct phydm_bt_info bt_info_table;
++#endif
++
++ struct pkt_process_info pkt_proc_struct;
++ struct phydm_adaptivity_struct adaptivity;
++ struct _DFS_STATISTICS dfs;
++ struct odm_noise_monitor noise_level;
++ struct odm_phy_dbg_info phy_dbg_info;
++
++#ifdef CONFIG_ADAPTIVE_SOML
++ struct adaptive_soml dm_soml_table;
++#endif
++
++#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))
++ #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
++ struct _BF_DIV_COEX_ dm_bdc_table;
++ #endif
++
++ #if (defined(CONFIG_HL_SMART_ANTENNA))
++ struct smt_ant_honbo dm_sat_table;
++ #endif
++#endif
++
++#if (defined(CONFIG_SMART_ANTENNA))
++ struct smt_ant smtant_table;
++#endif
++
++ struct _hal_rf_ rf_table; /*@for HALRF function*/
++ struct dm_rf_calibration_struct rf_calibrate_info;
++ struct dm_iqk_info IQK_info;
++ struct dm_dpk_info dpk_info;
++
++#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
++ struct phydm_fat_struct dm_fat_table;
++ struct sw_antenna_switch dm_swat_table;
++#endif
++ struct phydm_dig_struct dm_dig_table;
++#ifdef PHYDM_LNA_SAT_CHK_SUPPORT
++ struct phydm_lna_sat_t dm_lna_sat_info;
++#endif
++
++#ifdef CONFIG_MCC_DM
++ struct _phydm_mcc_dm_ mcc_dm;
++#endif
++
++#ifdef PHYDM_SUPPORT_CCKPD
++ struct phydm_cckpd_struct dm_cckpd_table;
++#endif
++
++#ifdef PHYDM_PRIMARY_CCA
++ struct phydm_pricca_struct dm_pri_cca;
++#endif
++
++ struct ra_table dm_ra_table;
++ struct phydm_fa_struct false_alm_cnt;
++#ifdef PHYDM_TDMA_DIG_SUPPORT
++ struct phydm_fa_acc_struct false_alm_cnt_acc;
++#ifdef IS_USE_NEW_TDMA
++ struct phydm_fa_acc_struct false_alm_cnt_acc_low;
++#endif
++#endif
++ struct phydm_cfo_track_struct dm_cfo_track;
++ struct ccx_info dm_ccx_info;
++
++ struct odm_power_trim_data power_trim_data;
++#if (RTL8822B_SUPPORT == 1)
++ struct drp_rtl8822b_struct phydm_rtl8822b;
++#endif
++
++#ifdef CONFIG_PSD_TOOL
++ struct psd_info dm_psd_table;
++#endif
++
++#if (PHYDM_LA_MODE_SUPPORT == 1)
++ struct rt_adcsmp adcsmp;
++#endif
++
++#if (defined(CONFIG_PATH_DIVERSITY))
++ struct _ODM_PATH_DIVERSITY_ dm_path_div;
++#endif
++
++#if (defined(CONFIG_ANT_DETECTION))
++ struct _ANT_DETECTED_INFO ant_detected_info;
++#endif
++
++#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
++#ifdef PHYDM_BEAMFORMING_SUPPORT
++ struct _RT_BEAMFORMING_INFO beamforming_info;
++#endif
++#endif
++#ifdef PHYDM_AUTO_DEGBUG
++ struct phydm_auto_dbg_struct auto_dbg_table;
++#endif
++
++ struct phydm_pause_lv pause_lv_table;
++ struct phydm_api_stuc api_table;
++#ifdef PHYDM_POWER_TRAINING_SUPPORT
++ struct phydm_pow_train_stuc pow_train_table;
++#endif
++
++#ifdef PHYDM_PMAC_TX_SETTING_SUPPORT
++ struct phydm_pmac_tx dm_pmac_tx_table;
++#endif
++
++#ifdef PHYDM_MP_SUPPORT
++ struct phydm_mp dm_mp_table;
++#endif
++/*@==========================================================*/
++
++#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
++
++#if (RT_PLATFORM != PLATFORM_LINUX)
++} dm_struct; /*@DM_Dynamic_Mechanism_Structure*/
++#else
++};
++#endif
++
++#else /*@for AP,CE Team*/
++};
++#endif
++
++enum phydm_adv_ota {
++ PHYDM_PATHB_1RCCA = BIT(0),
++ PHYDM_HP_OTA_SETTING_A = BIT(1),
++ PHYDM_HP_OTA_SETTING_B = BIT(2),
++ PHYDM_ASUS_OTA_SETTING = BIT(3),
++ PHYDM_ASUS_OTA_SETTING_CCK_PATH = BIT(4),
++ PHYDM_HP_OTA_SETTING_CCK_PATH = BIT(5),
++ PHYDM_LENOVO_OTA_SETTING_NBI_CSI = BIT(6),
++
++};
++
++enum phydm_bb_op_mode {
++ PHYDM_PERFORMANCE_MODE = 0, /*Service one device*/
++ PHYDM_BALANCE_MODE = 1, /*@Service more than one device*/
++};
++
++enum phydm_structure_type {
++ PHYDM_FALSEALMCNT,
++ PHYDM_CFOTRACK,
++ PHYDM_ADAPTIVITY,
++ PHYDM_DFS,
++ PHYDM_ROMINFO,
++
++};
++
++enum odm_bb_config_type {
++ CONFIG_BB_PHY_REG,
++ CONFIG_BB_AGC_TAB,
++ CONFIG_BB_AGC_TAB_2G,
++ CONFIG_BB_AGC_TAB_5G,
++ CONFIG_BB_PHY_REG_PG,
++ CONFIG_BB_PHY_REG_MP,
++ CONFIG_BB_AGC_TAB_DIFF,
++ CONFIG_BB_RF_CAL_INIT,
++};
++
++enum odm_rf_config_type {
++ CONFIG_RF_RADIO,
++ CONFIG_RF_TXPWR_LMT,
++ CONFIG_RF_SYN_RADIO,
++};
++
++enum odm_fw_config_type {
++ CONFIG_FW_NIC,
++ CONFIG_FW_NIC_2,
++ CONFIG_FW_AP,
++ CONFIG_FW_AP_2,
++ CONFIG_FW_MP,
++ CONFIG_FW_WOWLAN,
++ CONFIG_FW_WOWLAN_2,
++ CONFIG_FW_AP_WOWLAN,
++ CONFIG_FW_BT,
++};
++
++/*status code*/
++#if (DM_ODM_SUPPORT_TYPE != ODM_WIN)
++enum rt_status {
++ RT_STATUS_SUCCESS,
++ RT_STATUS_FAILURE,
++ RT_STATUS_PENDING,
++ RT_STATUS_RESOURCE,
++ RT_STATUS_INVALID_CONTEXT,
++ RT_STATUS_INVALID_PARAMETER,
++ RT_STATUS_NOT_SUPPORT,
++ RT_STATUS_OS_API_FAILED,
++};
++#endif /*@end of enum rt_status definition*/
++
++void
++phydm_watchdog_lps(struct dm_struct *dm);
++
++void
++phydm_watchdog_lps_32k(struct dm_struct *dm);
++
++void
++phydm_txcurrentcalibration(struct dm_struct *dm);
++
++void
++phydm_dm_early_init(struct dm_struct *dm);
++
++void
++odm_dm_init(struct dm_struct *dm);
++
++void
++odm_dm_reset(struct dm_struct *dm);
++
++void
++phydm_fwoffload_ability_init(struct dm_struct *dm,
++ enum phydm_offload_ability offload_ability);
++
++void
++phydm_fwoffload_ability_clear(struct dm_struct *dm,
++ enum phydm_offload_ability offload_ability);
++
++void
++phydm_supportability_en(void *dm_void, char input[][16], u32 *_used,
++ char *output, u32 *_out_len);
++
++void
++phydm_pause_dm_watchdog(void *dm_void, enum phydm_pause_type pause_type);
++
++void
++phydm_watchdog(struct dm_struct *dm);
++
++void
++phydm_watchdog_mp(struct dm_struct *dm);
++
++u8
++phydm_pause_func(void *dm_void, enum phydm_func_idx pause_func,
++ enum phydm_pause_type pause_type,
++ enum phydm_pause_level pause_lv, u8 val_lehgth, u32 *val_buf);
++
++void
++phydm_pause_func_console(void *dm_void, char input[][16], u32 *_used,
++ char *output, u32 *_out_len);
++
++void
++odm_cmn_info_init(struct dm_struct *dm, enum odm_cmninfo cmn_info, u64 value);
++
++void
++odm_cmn_info_hook(struct dm_struct *dm, enum odm_cmninfo cmn_info, void *value);
++
++void
++odm_cmn_info_update(struct dm_struct *dm, u32 cmn_info, u64 value);
++
++u32
++phydm_cmn_info_query(struct dm_struct *dm, enum phydm_info_query info_type);
++
++void
++odm_init_all_timers(struct dm_struct *dm);
++
++void
++odm_cancel_all_timers(struct dm_struct *dm);
++
++void
++odm_release_all_timers(struct dm_struct *dm);
++
++void *
++phydm_get_structure(struct dm_struct *dm, u8 structure_type);
++
++void
++phydm_dc_cancellation(struct dm_struct *dm);
++
++void
++phydm_receiver_blocking(void *dm_void);
++
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++void
++odm_init_all_work_items(
++ struct dm_struct *dm
++);
++void
++odm_free_all_work_items(
++ struct dm_struct *dm
++);
++#endif /*@#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)*/
++
++#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
++void
++odm_dtc(struct dm_struct *dm);
++#endif
++
++#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
++void
++odm_init_all_threads(
++ struct dm_struct *dm
++);
++
++void
++odm_stop_all_threads(
++ struct dm_struct *dm
++);
++#endif
++
++#endif
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/phydm_hwconfig.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/phydm_hwconfig.c
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/phydm_hwconfig.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/phydm_hwconfig.c 2021-03-07 18:16:17.063956478 +0200
@@ -0,0 +1,1419 @@
+/******************************************************************************
+ *
@@ -239326,11 +235964,9 @@ index 000000000..4c4d9386e
+#endif
+ return value32;
+}
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_hwconfig.h linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_hwconfig.h
-new file mode 100644
-index 000000000..7c4d1e38c
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_hwconfig.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/phydm_hwconfig.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/phydm_hwconfig.h
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/phydm_hwconfig.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/phydm_hwconfig.h 2021-03-07 18:16:17.063956478 +0200
@@ -0,0 +1,79 @@
+/******************************************************************************
+ *
@@ -239411,11 +236047,9 @@ index 000000000..7c4d1e38c
+u32 query_phydm_txbf_capability(struct dm_struct *dm);
+
+#endif /*@#ifndef __HALHWOUTSRC_H__*/
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_interface.c linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_interface.c
-new file mode 100644
-index 000000000..fe0f5c220
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_interface.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/phydm_interface.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/phydm_interface.c
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/phydm_interface.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/phydm_interface.c 2021-03-07 18:16:17.063956478 +0200
@@ -0,0 +1,1468 @@
+/******************************************************************************
+ *
@@ -240885,11 +237519,9 @@ index 000000000..fe0f5c220
+ return tx_rate;
+}
+
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_interface.h linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_interface.h
-new file mode 100644
-index 000000000..38edfb498
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_interface.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/phydm_interface.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/phydm_interface.h
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/phydm_interface.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/phydm_interface.h 2021-03-07 18:16:17.063956478 +0200
@@ -0,0 +1,343 @@
+/******************************************************************************
+ *
@@ -241234,11 +237866,9 @@ index 000000000..38edfb498
+ void *context);
+u32 phydm_get_tx_rate(struct dm_struct *dm);
+#endif /* @__ODM_INTERFACE_H__ */
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_lna_sat.c linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_lna_sat.c
-new file mode 100644
-index 000000000..5320468b3
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_lna_sat.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/phydm_lna_sat.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/phydm_lna_sat.c
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/phydm_lna_sat.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/phydm_lna_sat.c 2021-03-07 18:16:17.063956478 +0200
@@ -0,0 +1,1343 @@
+/******************************************************************************
+ *
@@ -242583,11 +239213,9 @@ index 000000000..5320468b3
+}
+
+#endif /*@#ifdef PHYDM_LNA_SAT_CHK_SUPPORT*/
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_lna_sat.h linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_lna_sat.h
-new file mode 100644
-index 000000000..c9345b86f
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_lna_sat.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/phydm_lna_sat.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/phydm_lna_sat.h
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/phydm_lna_sat.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/phydm_lna_sat.h 2021-03-07 18:16:17.063956478 +0200
@@ -0,0 +1,173 @@
+/******************************************************************************
+ *
@@ -242762,11 +239390,9 @@ index 000000000..c9345b86f
+
+#endif /*@#if (PHYDM_LNA_SAT_CHK_SUPPORT == 1)*/
+#endif
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_math_lib.c linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_math_lib.c
-new file mode 100644
-index 000000000..cf1568ca4
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_math_lib.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/phydm_math_lib.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/phydm_math_lib.c
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/phydm_math_lib.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/phydm_math_lib.c 2021-03-07 18:16:17.063956478 +0200
@@ -0,0 +1,248 @@
+/******************************************************************************
+ *
@@ -243016,11 +239642,9 @@ index 000000000..cf1568ca4
+ return val;
+}
+
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_math_lib.h linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_math_lib.h
-new file mode 100644
-index 000000000..daee35207
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_math_lib.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/phydm_math_lib.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/phydm_math_lib.h
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/phydm_math_lib.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/phydm_math_lib.h 2021-03-07 18:16:17.063956478 +0200
@@ -0,0 +1,114 @@
+/******************************************************************************
+ *
@@ -243136,11 +239760,240 @@ index 000000000..daee35207
+
+s32 phydm_cnvrt_2_sign(u32 val, u8 bit_num);
+#endif
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_mp.c linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_mp.c
-new file mode 100644
-index 000000000..7d964f5d6
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_mp.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/phydm.mk linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/phydm.mk
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/phydm.mk 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/phydm.mk 2021-03-07 18:16:17.059956289 +0200
+@@ -0,0 +1,226 @@
++EXTRA_CFLAGS += -I$(src)/hal/phydm
++
++_PHYDM_FILES := hal/phydm/phydm_debug.o \
++ hal/phydm/phydm_antdiv.o\
++ hal/phydm/phydm_soml.o\
++ hal/phydm/phydm_smt_ant.o\
++ hal/phydm/phydm_antdect.o\
++ hal/phydm/phydm_interface.o\
++ hal/phydm/phydm_phystatus.o\
++ hal/phydm/phydm_hwconfig.o\
++ hal/phydm/phydm.o\
++ hal/phydm/phydm_dig.o\
++ hal/phydm/phydm_pathdiv.o\
++ hal/phydm/phydm_rainfo.o\
++ hal/phydm/phydm_dynamictxpower.o\
++ hal/phydm/phydm_adaptivity.o\
++ hal/phydm/phydm_cfotracking.o\
++ hal/phydm/phydm_noisemonitor.o\
++ hal/phydm/phydm_beamforming.o\
++ hal/phydm/phydm_dfs.o\
++ hal/phydm/txbf/halcomtxbf.o\
++ hal/phydm/txbf/haltxbfinterface.o\
++ hal/phydm/txbf/phydm_hal_txbf_api.o\
++ hal/phydm/phydm_adc_sampling.o\
++ hal/phydm/phydm_ccx.o\
++ hal/phydm/phydm_psd.o\
++ hal/phydm/phydm_primary_cca.o\
++ hal/phydm/phydm_cck_pd.o\
++ hal/phydm/phydm_rssi_monitor.o\
++ hal/phydm/phydm_auto_dbg.o\
++ hal/phydm/phydm_math_lib.o\
++ hal/phydm/phydm_api.o\
++ hal/phydm/phydm_pow_train.o\
++ hal/phydm/phydm_lna_sat.o\
++ hal/phydm/phydm_pmac_tx_setting.o\
++ hal/phydm/phydm_mp.o\
++ hal/phydm/halrf/halrf.o\
++ hal/phydm/halrf/halrf_debug.o\
++ hal/phydm/halrf/halphyrf_ce.o\
++ hal/phydm/halrf/halrf_powertracking_ce.o\
++ hal/phydm/halrf/halrf_powertracking.o\
++ hal/phydm/halrf/halrf_kfree.o
++
++ifeq ($(CONFIG_RTL8188E), y)
++RTL871X = rtl8188e
++_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8188e_mac.o\
++ hal/phydm/$(RTL871X)/halhwimg8188e_bb.o\
++ hal/phydm/$(RTL871X)/halhwimg8188e_rf.o\
++ hal/phydm/halrf/$(RTL871X)/halrf_8188e_ce.o\
++ hal/phydm/$(RTL871X)/phydm_regconfig8188e.o\
++ hal/phydm/$(RTL871X)/hal8188erateadaptive.o\
++ hal/phydm/$(RTL871X)/phydm_rtl8188e.o
++endif
++
++ifeq ($(CONFIG_RTL8192E), y)
++RTL871X = rtl8192e
++_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8192e_mac.o\
++ hal/phydm/$(RTL871X)/halhwimg8192e_bb.o\
++ hal/phydm/$(RTL871X)/halhwimg8192e_rf.o\
++ hal/phydm/halrf/$(RTL871X)/halrf_8192e_ce.o\
++ hal/phydm/$(RTL871X)/phydm_regconfig8192e.o\
++ hal/phydm/$(RTL871X)/phydm_rtl8192e.o
++endif
++
++
++ifeq ($(CONFIG_RTL8812A), y)
++RTL871X = rtl8812a
++_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8812a_mac.o\
++ hal/phydm/$(RTL871X)/halhwimg8812a_bb.o\
++ hal/phydm/$(RTL871X)/halhwimg8812a_rf.o\
++ hal/phydm/halrf/$(RTL871X)/halrf_8812a_ce.o\
++ hal/phydm/$(RTL871X)/phydm_regconfig8812a.o\
++ hal/phydm/$(RTL871X)/phydm_rtl8812a.o\
++ hal/phydm/txbf/haltxbfjaguar.o
++endif
++
++ifeq ($(CONFIG_RTL8821A), y)
++RTL871X = rtl8821a
++_PHYDM_FILES += hal/phydm/rtl8821a/halhwimg8821a_mac.o\
++ hal/phydm/rtl8821a/halhwimg8821a_bb.o\
++ hal/phydm/rtl8821a/halhwimg8821a_rf.o\
++ hal/phydm/halrf/rtl8812a/halrf_8812a_ce.o\
++ hal/phydm/halrf/rtl8821a/halrf_8821a_ce.o\
++ hal/phydm/rtl8821a/phydm_regconfig8821a.o\
++ hal/phydm/rtl8821a/phydm_rtl8821a.o\
++ hal/phydm/halrf/rtl8821a/halrf_iqk_8821a_ce.o\
++ hal/phydm/txbf/haltxbfjaguar.o
++endif
++
++
++ifeq ($(CONFIG_RTL8723B), y)
++RTL871X = rtl8723b
++_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8723b_bb.o\
++ hal/phydm/$(RTL871X)/halhwimg8723b_mac.o\
++ hal/phydm/$(RTL871X)/halhwimg8723b_rf.o\
++ hal/phydm/$(RTL871X)/halhwimg8723b_mp.o\
++ hal/phydm/$(RTL871X)/phydm_regconfig8723b.o\
++ hal/phydm/halrf/$(RTL871X)/halrf_8723b_ce.o\
++ hal/phydm/$(RTL871X)/phydm_rtl8723b.o
++endif
++
++
++ifeq ($(CONFIG_RTL8814A), y)
++RTL871X = rtl8814a
++_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8814a_bb.o\
++ hal/phydm/$(RTL871X)/halhwimg8814a_mac.o\
++ hal/phydm/$(RTL871X)/halhwimg8814a_rf.o\
++ hal/phydm/halrf/$(RTL871X)/halrf_iqk_8814a.o\
++ hal/phydm/$(RTL871X)/phydm_regconfig8814a.o\
++ hal/phydm/halrf/$(RTL871X)/halrf_8814a_ce.o\
++ hal/phydm/$(RTL871X)/phydm_rtl8814a.o\
++ hal/phydm/txbf/haltxbf8814a.o
++endif
++
++
++ifeq ($(CONFIG_RTL8723C), y)
++RTL871X = rtl8703b
++_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8703b_bb.o\
++ hal/phydm/$(RTL871X)/halhwimg8703b_mac.o\
++ hal/phydm/$(RTL871X)/halhwimg8703b_rf.o\
++ hal/phydm/$(RTL871X)/phydm_regconfig8703b.o\
++ hal/phydm/$(RTL871X)/phydm_rtl8703b.o\
++ hal/phydm/halrf/$(RTL871X)/halrf_8703b.o
++endif
++
++ifeq ($(CONFIG_RTL8723D), y)
++RTL871X = rtl8723d
++_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8723d_bb.o\
++ hal/phydm/$(RTL871X)/halhwimg8723d_mac.o\
++ hal/phydm/$(RTL871X)/halhwimg8723d_rf.o\
++ hal/phydm/$(RTL871X)/phydm_regconfig8723d.o\
++ hal/phydm/$(RTL871X)/phydm_rtl8723d.o\
++ hal/phydm/halrf/$(RTL871X)/halrf_8723d.o
++endif
++
++
++ifeq ($(CONFIG_RTL8710B), y)
++RTL871X = rtl8710b
++_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8710b_bb.o\
++ hal/phydm/$(RTL871X)/halhwimg8710b_mac.o\
++ hal/phydm/$(RTL871X)/halhwimg8710b_rf.o\
++ hal/phydm/$(RTL871X)/phydm_regconfig8710b.o\
++ hal/phydm/$(RTL871X)/phydm_rtl8710b.o\
++ hal/phydm/halrf/$(RTL871X)/halrf_8710b.o
++endif
++
++
++ifeq ($(CONFIG_RTL8188F), y)
++RTL871X = rtl8188f
++_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8188f_bb.o\
++ hal/phydm/$(RTL871X)/halhwimg8188f_mac.o\
++ hal/phydm/$(RTL871X)/halhwimg8188f_rf.o\
++ hal/phydm/$(RTL871X)/phydm_regconfig8188f.o\
++ hal/phydm/halrf/$(RTL871X)/halrf_8188f.o \
++ hal/phydm/$(RTL871X)/phydm_rtl8188f.o
++endif
++
++ifeq ($(CONFIG_RTL8822B), y)
++RTL871X = rtl8822b
++_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8822b_bb.o \
++ hal/phydm/$(RTL871X)/halhwimg8822b_mac.o \
++ hal/phydm/$(RTL871X)/halhwimg8822b_rf.o \
++ hal/phydm/halrf/$(RTL871X)/halrf_8822b.o \
++ hal/phydm/$(RTL871X)/phydm_hal_api8822b.o \
++ hal/phydm/halrf/$(RTL871X)/halrf_iqk_8822b.o \
++ hal/phydm/halrf/$(RTL871X)/halrf_rfk_init_8822b.o \
++ hal/phydm/$(RTL871X)/phydm_regconfig8822b.o \
++ hal/phydm/$(RTL871X)/phydm_rtl8822b.o
++
++_PHYDM_FILES += hal/phydm/txbf/haltxbf8822b.o
++endif
++
++
++ifeq ($(CONFIG_RTL8821C), y)
++RTL871X = rtl8821c
++_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8821c_bb.o \
++ hal/phydm/$(RTL871X)/halhwimg8821c_mac.o \
++ hal/phydm/$(RTL871X)/halhwimg8821c_rf.o \
++ hal/phydm/$(RTL871X)/phydm_hal_api8821c.o \
++ hal/phydm/$(RTL871X)/phydm_regconfig8821c.o\
++ hal/phydm/halrf/$(RTL871X)/halrf_8821c.o\
++ hal/phydm/halrf/$(RTL871X)/halrf_iqk_8821c.o
++endif
++ifeq ($(CONFIG_RTL8192F), y)
++RTL871X = rtl8192f
++_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8192f_bb.o\
++ hal/phydm/$(RTL871X)/halhwimg8192f_mac.o\
++ hal/phydm/$(RTL871X)/halhwimg8192f_rf.o\
++ hal/phydm/$(RTL871X)/phydm_hal_api8192f.o\
++ hal/phydm/$(RTL871X)/phydm_regconfig8192f.o\
++ hal/phydm/$(RTL871X)/phydm_rtl8192f.o\
++ hal/phydm/halrf/$(RTL871X)/halrf_8192f.o
++endif
++
++ifeq ($(CONFIG_RTL8198F), y)
++RTL871X = rtl8198f
++_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8198f_bb.o\
++ hal/phydm/$(RTL871X)/halhwimg8198f_mac.o\
++ hal/phydm/$(RTL871X)/halhwimg8198f_rf.o\
++ hal/phydm/$(RTL871X)/phydm_hal_api8198f.o\
++ hal/phydm/$(RTL871X)/phydm_regconfig8198f.o
++endif
++
++ifeq ($(CONFIG_RTL8822C), y)
++RTL871X = rtl8822c
++_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8822c_bb.o\
++ hal/phydm/$(RTL871X)/halhwimg8822c_mac.o\
++ hal/phydm/$(RTL871X)/halhwimg8822c_rf.o\
++ hal/phydm/$(RTL871X)/phydm_hal_api8822c.o\
++ hal/phydm/$(RTL871X)/phydm_regconfig8822c.o\
++ hal/phydm/halrf/$(RTL871X)/halrf_8822c.o\
++ hal/phydm/halrf/$(RTL871X)/halrf_iqk_8822c.o\
++ hal/phydm/halrf/$(RTL871X)/halrf_tssi_8822c.o\
++ hal/phydm/halrf/$(RTL871X)/halrf_dpk_8822c.o\
++ hal/phydm/halrf/$(RTL871X)/halrf_rfk_init_8822c.o
++endif
++
++ifeq ($(CONFIG_RTL8814B), y)
++RTL871X = rtl8814b
++_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8814b_bb.o\
++ hal/phydm/$(RTL871X)/phydm_hal_api8814b.o\
++ hal/phydm/$(RTL871X)/phydm_regconfig8814b.o\
++ hal/phydm/halrf/$(RTL871X)/halrf_8814b.o \
++ hal/phydm/halrf/$(RTL871X)/halrf_iqk_8814b.o \
++ hal/phydm/halrf/$(RTL871X)/halrf_rfk_init_8814b.o
++endif
+\ Ingen nyrad vid filslut
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/phydm_mp.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/phydm_mp.c
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/phydm_mp.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/phydm_mp.c 2021-03-07 18:16:17.063956478 +0200
@@ -0,0 +1,348 @@
+/******************************************************************************
+ *
@@ -243490,11 +240343,9 @@ index 000000000..7d964f5d6
+ mp->io_value = (u32)mp->rx_phy_ok_cnt;
+}
+#endif
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_mp.h linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_mp.h
-new file mode 100644
-index 000000000..40088c6ce
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_mp.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/phydm_mp.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/phydm_mp.h
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/phydm_mp.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/phydm_mp.h 2021-03-07 18:16:17.063956478 +0200
@@ -0,0 +1,94 @@
+/******************************************************************************
+ *
@@ -243590,11 +240441,9 @@ index 000000000..40088c6ce
+
+void phydm_mp_get_rx_ok(void *dm_void);
+#endif
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_noisemonitor.c linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_noisemonitor.c
-new file mode 100644
-index 000000000..77fe94e3f
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_noisemonitor.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/phydm_noisemonitor.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/phydm_noisemonitor.c
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/phydm_noisemonitor.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/phydm_noisemonitor.c 2021-03-07 18:16:17.063956478 +0200
@@ -0,0 +1,457 @@
+/******************************************************************************
+ *
@@ -244053,11 +240902,9 @@ index 000000000..77fe94e3f
+ total_cca_cnt, total_fa_cnt, dm->noisy_decision_smooth, score,
+ score_smooth, dm->noisy_decision);
+}
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_noisemonitor.h linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_noisemonitor.h
-new file mode 100644
-index 000000000..507285adb
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_noisemonitor.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/phydm_noisemonitor.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/phydm_noisemonitor.h
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/phydm_noisemonitor.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/phydm_noisemonitor.h 2021-03-07 18:16:17.063956478 +0200
@@ -0,0 +1,48 @@
+/******************************************************************************
+ *
@@ -244107,11 +240954,9 @@ index 000000000..507285adb
+void phydm_noisy_detection(void *dm_void);
+
+#endif
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_pathdiv.c linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_pathdiv.c
-new file mode 100644
-index 000000000..b3c46d295
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_pathdiv.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/phydm_pathdiv.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/phydm_pathdiv.c
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/phydm_pathdiv.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/phydm_pathdiv.c 2021-03-07 18:16:17.063956478 +0200
@@ -0,0 +1,928 @@
+/******************************************************************************
+ *
@@ -245041,11 +241886,9 @@ index 000000000..b3c46d295
+}
+
+#endif /* @#ifdef CONFIG_PATH_DIVERSITY */
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_pathdiv.h linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_pathdiv.h
-new file mode 100644
-index 000000000..132e9cddb
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_pathdiv.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/phydm_pathdiv.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/phydm_pathdiv.h
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/phydm_pathdiv.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/phydm_pathdiv.h 2021-03-07 18:16:17.063956478 +0200
@@ -0,0 +1,123 @@
+/******************************************************************************
+ *
@@ -245170,12 +242013,10 @@ index 000000000..132e9cddb
+#endif /* @#ifdef CONFIG_PATH_DIVERSITY */
+#endif /* @#ifndef __PHYDMPATHDIV_H__ */
+
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_phystatus.c linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_phystatus.c
-new file mode 100644
-index 000000000..bbcb6bd7b
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_phystatus.c
-@@ -0,0 +1,3183 @@
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/phydm_phystatus.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/phydm_phystatus.c
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/phydm_phystatus.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/phydm_phystatus.c 2021-03-07 18:16:17.064956526 +0200
+@@ -0,0 +1,3192 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
@@ -246249,7 +243090,6 @@ index 000000000..bbcb6bd7b
+#endif
+
+#if ODM_IC_11AC_SERIES_SUPPORT
-+
+void phydm_rx_physts_bw_parsing(struct phydm_phyinfo_struct *phy_info,
+ struct phydm_perpkt_info_struct *
+ pktinfo,
@@ -246367,6 +243207,16 @@ index 000000000..bbcb6bd7b
+
+ phy_info->rx_pwdb_all = rssi;
+ phy_info->rx_mimo_signal_strength[0] = rssi;
++
++ // fill per path rx power info
++ for (i = RF_PATH_A; i < dm->num_rf_path; i++) {
++ if (i < RF_PATH_C)
++ val = phy_sts->gain_trsw[i];
++ else
++ val = phy_sts->gain_trsw_cd[i - 2];
++
++ phy_info->rx_pwr[i] = (val & 0x7F) - 110;
++ }
+ } else {
+ /* @== [OFDM rate] ===================================================*/
+ for (i = RF_PATH_A; i < dm->num_rf_path; i++) {
@@ -248359,11 +245209,9 @@ index 000000000..bbcb6bd7b
+
+ phydm_avg_phystatus_init(dm);
+}
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_phystatus.h linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_phystatus.h
-new file mode 100644
-index 000000000..333fa89bf
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_phystatus.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/phydm_phystatus.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/phydm_phystatus.h
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/phydm_phystatus.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/phydm_phystatus.h 2021-03-07 18:16:17.064956526 +0200
@@ -0,0 +1,1137 @@
+/******************************************************************************
+ *
@@ -249502,11 +246350,9 @@ index 000000000..333fa89bf
+void phydm_rx_phy_status_init(void *dm_void);
+
+#endif /*@#ifndef __HALHWOUTSRC_H__*/
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_pmac_tx_setting.c linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_pmac_tx_setting.c
-new file mode 100644
-index 000000000..882283c7b
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_pmac_tx_setting.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/phydm_pmac_tx_setting.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/phydm_pmac_tx_setting.c
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/phydm_pmac_tx_setting.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/phydm_pmac_tx_setting.c 2021-03-07 18:16:17.064956526 +0200
@@ -0,0 +1,543 @@
+/******************************************************************************
+ *
@@ -250051,11 +246897,9 @@ index 000000000..882283c7b
+}
+
+#endif
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_pmac_tx_setting.h linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_pmac_tx_setting.h
-new file mode 100644
-index 000000000..982733c09
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_pmac_tx_setting.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/phydm_pmac_tx_setting.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/phydm_pmac_tx_setting.h
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/phydm_pmac_tx_setting.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/phydm_pmac_tx_setting.h 2021-03-07 18:16:17.064956526 +0200
@@ -0,0 +1,152 @@
+/******************************************************************************
+ *
@@ -250209,11 +247053,9 @@ index 000000000..982733c09
+void phydm_set_tmac_tx(void *dm_void);
+
+#endif
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_pow_train.c linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_pow_train.c
-new file mode 100644
-index 000000000..56bc2411d
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_pow_train.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/phydm_pow_train.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/phydm_pow_train.c
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/phydm_pow_train.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/phydm_pow_train.c 2021-03-07 18:16:17.064956526 +0200
@@ -0,0 +1,171 @@
+/******************************************************************************
+ *
@@ -250386,11 +247228,9 @@ index 000000000..56bc2411d
+}
+
+#endif
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_pow_train.h linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_pow_train.h
-new file mode 100644
-index 000000000..f966607aa
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_pow_train.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/phydm_pow_train.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/phydm_pow_train.h
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/phydm_pow_train.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/phydm_pow_train.h 2021-03-07 18:16:17.064956526 +0200
@@ -0,0 +1,84 @@
+/******************************************************************************
+ *
@@ -250476,11 +247316,527 @@ index 000000000..f966607aa
+
+#endif
+#endif
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_pre_define.h linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_pre_define.h
-new file mode 100644
-index 000000000..d8d7313b1
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_pre_define.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/phydm_precomp.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/phydm_precomp.h
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/phydm_precomp.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/phydm_precomp.h 2021-03-07 18:16:17.064956526 +0200
+@@ -0,0 +1,514 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * The full GNU General Public License is included in this distribution in the
++ * file called LICENSE.
++ *
++ * Contact Information:
++ * wlanfae
++ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
++ * Hsinchu 300, Taiwan.
++ *
++ * Larry Finger
++ *
++ *****************************************************************************/
++
++#ifndef __ODM_PRECOMP_H__
++#define __ODM_PRECOMP_H__
++
++#include "phydm_types.h"
++#include "halrf/halrf_features.h"
++
++#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++ #include "Precomp.h" /* @We need to include mp_precomp.h due to batch file setting. */
++#else
++ #define TEST_FALG___ 1
++#endif
++
++/* @2 Config Flags and Structs - defined by each ODM type */
++
++#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
++ #include "../8192cd_cfg.h"
++ #include "../odm_inc.h"
++
++ #include "../8192cd.h"
++ #include "../8192cd_util.h"
++ #include "../8192cd_hw.h"
++ #ifdef _BIG_ENDIAN_
++ #define ODM_ENDIAN_TYPE ODM_ENDIAN_BIG
++ #else
++ #define ODM_ENDIAN_TYPE ODM_ENDIAN_LITTLE
++ #endif
++
++ #include "../8192cd_headers.h"
++ #include "../8192cd_debug.h"
++
++#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
++ #ifdef DM_ODM_CE_MAC80211
++ #include "../wifi.h"
++ #include "rtl_phydm.h"
++ #elif defined(DM_ODM_CE_MAC80211_V2)
++ #include "../main.h"
++ #include "../hw.h"
++ #include "../fw.h"
++ #endif
++ #define __PACK
++ #define __WLAN_ATTRIB_PACK__
++#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++ #include "mp_precomp.h"
++ #define ODM_ENDIAN_TYPE ODM_ENDIAN_LITTLE
++ #define __PACK
++ #define __WLAN_ATTRIB_PACK__
++#elif (DM_ODM_SUPPORT_TYPE == ODM_IOT)
++ #include
++ #include
++ #define ODM_ENDIAN_TYPE ODM_ENDIAN_LITTLE
++ #define __PACK
++#endif
++
++/* @2 OutSrc Header Files */
++
++#include "phydm.h"
++#include "phydm_hwconfig.h"
++#include "phydm_phystatus.h"
++#include "phydm_debug.h"
++#include "phydm_regdefine11ac.h"
++#include "phydm_regdefine11n.h"
++#include "phydm_interface.h"
++#include "phydm_reg.h"
++#include "halrf/halrf_debug.h"
++
++#if (DM_ODM_SUPPORT_TYPE & ODM_CE) && \
++ (!defined(DM_ODM_CE_MAC80211) && !defined(DM_ODM_CE_MAC80211_V2))
++
++void phy_set_tx_power_limit(
++ struct dm_struct *dm,
++ u8 *regulation,
++ u8 *band,
++ u8 *bandwidth,
++ u8 *rate_section,
++ u8 *rf_path,
++ u8 *channel,
++ u8 *power_limit);
++
++enum hal_status
++rtw_phydm_fw_iqk(
++ struct dm_struct *dm,
++ u8 clear,
++ u8 segment);
++
++enum hal_status
++rtw_phydm_cfg_phy_para(
++ struct dm_struct *dm,
++ enum phydm_halmac_param config_type,
++ u32 offset,
++ u32 data,
++ u32 mask,
++ enum rf_path e_rf_path,
++ u32 delay_time);
++
++#endif
++
++/* @Judy ADD 20180125 */
++#if (DM_ODM_SUPPORT_TYPE & (ODM_AP | ODM_IOT))
++#define RTL8710B_SUPPORT 0
++#endif
++
++#if RTL8188E_SUPPORT == 1
++ #define RTL8188E_T_SUPPORT 1
++ #ifdef CONFIG_SFW_SUPPORTED
++ #define RTL8188E_S_SUPPORT 1
++ #else
++ #define RTL8188E_S_SUPPORT 0
++ #endif
++#endif
++
++#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
++#define RTL8197F_SUPPORT 0 /*@Just for PHYDM API development*/
++#define RTL8195B_SUPPORT 0 /*@Just for PHYDM API development*/
++#define RTL8198F_SUPPORT 0 /*@Just for PHYDM API development*/
++#define RTL8812F_SUPPORT 0 /*@Just for PHYDM API development*/
++#define RTL8197G_SUPPORT 0 /*@Just for PHYDM API development*/
++#endif
++
++#if (RTL8188E_SUPPORT == 1)
++ #include "rtl8188e/hal8188erateadaptive.h" /* @for RA,Power training */
++ #include "rtl8188e/halhwimg8188e_mac.h"
++ #include "rtl8188e/halhwimg8188e_rf.h"
++ #include "rtl8188e/halhwimg8188e_bb.h"
++ #include "rtl8188e/phydm_regconfig8188e.h"
++ #include "rtl8188e/phydm_rtl8188e.h"
++ #include "rtl8188e/hal8188ereg.h"
++ #include "rtl8188e/version_rtl8188e.h"
++ #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
++ #include "rtl8188e_hal.h"
++ #include "halrf/rtl8188e/halrf_8188e_ce.h"
++ #endif
++ #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++ #include "halrf/rtl8188e/halrf_8188e_win.h"
++ #endif
++ #if (DM_ODM_SUPPORT_TYPE == ODM_AP)
++ #include "halrf/rtl8188e/halrf_8188e_ap.h"
++ #endif
++#endif /* @88E END */
++
++#if (RTL8192E_SUPPORT == 1)
++
++ #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++ #include "halrf/rtl8192e/halrf_8192e_win.h" /*@FOR_8192E_IQK*/
++ #elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
++ #include "halrf/rtl8192e/halrf_8192e_ap.h" /*@FOR_8192E_IQK*/
++ #elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
++ #include "halrf/rtl8192e/halrf_8192e_ce.h" /*@FOR_8192E_IQK*/
++ #endif
++
++ #include "rtl8192e/phydm_rtl8192e.h" /* @FOR_8192E_IQK */
++ #include "rtl8192e/version_rtl8192e.h"
++ #if (DM_ODM_SUPPORT_TYPE != ODM_AP)
++ #include "rtl8192e/halhwimg8192e_bb.h"
++ #include "rtl8192e/halhwimg8192e_mac.h"
++ #include "rtl8192e/halhwimg8192e_rf.h"
++ #include "rtl8192e/phydm_regconfig8192e.h"
++ #include "rtl8192e/hal8192ereg.h"
++ #endif
++ #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
++ #include "rtl8192e_hal.h"
++ #endif
++#endif /* @92E END */
++
++#if (RTL8812A_SUPPORT == 1)
++
++ #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++ #include "halrf/rtl8812a/halrf_8812a_win.h"
++ #elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
++ #include "halrf/rtl8812a/halrf_8812a_ap.h"
++ #elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
++ #include "halrf/rtl8812a/halrf_8812a_ce.h"
++ #endif
++
++ /* @#include "halrf/rtl8812a/halrf_8812a.h" */ /* @FOR_8812_IQK */
++ #if (DM_ODM_SUPPORT_TYPE != ODM_AP)
++ #include "rtl8812a/halhwimg8812a_bb.h"
++ #include "rtl8812a/halhwimg8812a_mac.h"
++ #include "rtl8812a/halhwimg8812a_rf.h"
++ #include "rtl8812a/phydm_regconfig8812a.h"
++ #endif
++ #include "rtl8812a/phydm_rtl8812a.h"
++
++ #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
++ #include "rtl8812a_hal.h"
++ #endif
++ #include "rtl8812a/version_rtl8812a.h"
++
++#endif /* @8812 END */
++
++#if (RTL8814A_SUPPORT == 1)
++
++ #include "rtl8814a/halhwimg8814a_mac.h"
++ #include "rtl8814a/halhwimg8814a_rf.h"
++ #include "rtl8814a/halhwimg8814a_bb.h"
++ #include "rtl8814a/version_rtl8814a.h"
++ #include "rtl8814a/phydm_rtl8814a.h"
++ #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++ #include "halrf/rtl8814a/halrf_8814a_win.h"
++ #elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
++ #include "halrf/rtl8814a/halrf_8814a_ce.h"
++ #elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
++ #include "halrf/rtl8814a/halrf_8814a_ap.h"
++ #endif
++ #include "rtl8814a/phydm_regconfig8814a.h"
++ #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
++ #include "rtl8814a_hal.h"
++ #include "halrf/rtl8814a/halrf_iqk_8814a.h"
++ #endif
++#endif /* @8814 END */
++
++#if (RTL8881A_SUPPORT == 1)/* @FOR_8881_IQK */
++ #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++ #include "halrf/rtl8821a/halrf_iqk_8821a_win.h"
++ #elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
++ #include "halrf/rtl8821a/halrf_iqk_8821a_ce.h"
++ #else
++ #include "halrf/rtl8821a/halrf_iqk_8821a_ap.h"
++ #endif
++ /* @#include "rtl8881a/HalHWImg8881A_BB.h" */
++ /* @#include "rtl8881a/HalHWImg8881A_MAC.h" */
++ /* @#include "rtl8881a/HalHWImg8881A_RF.h" */
++ /* @#include "rtl8881a/odm_RegConfig8881A.h" */
++#endif
++
++#if (RTL8723B_SUPPORT == 1)
++ #include "rtl8723b/halhwimg8723b_mac.h"
++ #include "rtl8723b/halhwimg8723b_rf.h"
++ #include "rtl8723b/halhwimg8723b_bb.h"
++ #include "rtl8723b/phydm_regconfig8723b.h"
++ #include "rtl8723b/phydm_rtl8723b.h"
++ #include "rtl8723b/hal8723breg.h"
++ #include "rtl8723b/version_rtl8723b.h"
++ #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++ #include "halrf/rtl8723b/halrf_8723b_win.h"
++ #elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
++ #include "halrf/rtl8723b/halrf_8723b_ce.h"
++ #include "rtl8723b/halhwimg8723b_mp.h"
++ #include "rtl8723b_hal.h"
++ #else
++ #include "halrf/rtl8723b/halrf_8723b_ap.h"
++ #endif
++#endif
++
++#if (RTL8821A_SUPPORT == 1)
++ #include "rtl8821a/halhwimg8821a_mac.h"
++ #include "rtl8821a/halhwimg8821a_rf.h"
++ #include "rtl8821a/halhwimg8821a_bb.h"
++ #include "rtl8821a/phydm_regconfig8821a.h"
++ #include "rtl8821a/phydm_rtl8821a.h"
++ #include "rtl8821a/version_rtl8821a.h"
++ #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++ #include "halrf/rtl8821a/halrf_8821a_win.h"
++ #elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
++ #include "halrf/rtl8821a/halrf_8821a_ce.h"
++ #include "halrf/rtl8821a/halrf_iqk_8821a_ce.h"/*@for IQK*/
++ #include "halrf/rtl8812a/halrf_8812a_ce.h"/*@for IQK,LCK,Power-tracking*/
++ #include "rtl8812a_hal.h"
++ #else
++ #endif
++#endif
++
++#if (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211)
++#include "../halmac/halmac_reg2.h"
++#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
++#include "../halmac/halmac_reg2.h"
++#endif
++
++
++#if (RTL8822B_SUPPORT == 1)
++ #include "rtl8822b/halhwimg8822b_mac.h"
++ #include "rtl8822b/halhwimg8822b_rf.h"
++ #include "rtl8822b/halhwimg8822b_bb.h"
++ #include "rtl8822b/phydm_regconfig8822b.h"
++ #include "halrf/rtl8822b/halrf_8822b.h"
++ #include "rtl8822b/phydm_rtl8822b.h"
++ #include "rtl8822b/phydm_hal_api8822b.h"
++ #include "rtl8822b/version_rtl8822b.h"
++
++ #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
++ #elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
++ #ifdef DM_ODM_CE_MAC80211
++ #include "../halmac/halmac_reg_8822b.h"
++ #elif defined(DM_ODM_CE_MAC80211_V2)
++ #include "../halmac/halmac_reg_8822b.h"
++ #else
++ #include /* @struct HAL_DATA_TYPE */
++ #include /* @RX_SMOOTH_FACTOR, reg definition and etc.*/
++ #endif
++ #elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
++ #endif
++
++#endif
++
++#if (RTL8703B_SUPPORT == 1)
++ #include "rtl8703b/phydm_rtl8703b.h"
++ #include "rtl8703b/phydm_regconfig8703b.h"
++ #include "rtl8703b/halhwimg8703b_mac.h"
++ #include "rtl8703b/halhwimg8703b_rf.h"
++ #include "rtl8703b/halhwimg8703b_bb.h"
++ #include "halrf/rtl8703b/halrf_8703b.h"
++ #include "rtl8703b/version_rtl8703b.h"
++ #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
++ #include "rtl8703b_hal.h"
++ #endif
++#endif
++
++#if (RTL8188F_SUPPORT == 1)
++ #include "rtl8188f/halhwimg8188f_mac.h"
++ #include "rtl8188f/halhwimg8188f_rf.h"
++ #include "rtl8188f/halhwimg8188f_bb.h"
++ #include "rtl8188f/hal8188freg.h"
++ #include "rtl8188f/phydm_rtl8188f.h"
++ #include "rtl8188f/phydm_regconfig8188f.h"
++ #include "halrf/rtl8188f/halrf_8188f.h" /*@for IQK,LCK,Power-tracking*/
++ #include "rtl8188f/version_rtl8188f.h"
++ #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
++ #include "rtl8188f_hal.h"
++ #endif
++#endif
++
++#if (RTL8723D_SUPPORT == 1)
++ #if (DM_ODM_SUPPORT_TYPE != ODM_AP)
++
++ #include "rtl8723d/halhwimg8723d_bb.h"
++ #include "rtl8723d/halhwimg8723d_mac.h"
++ #include "rtl8723d/halhwimg8723d_rf.h"
++ #include "rtl8723d/phydm_regconfig8723d.h"
++ #include "rtl8723d/hal8723dreg.h"
++ #include "rtl8723d/phydm_rtl8723d.h"
++ #include "halrf/rtl8723d/halrf_8723d.h"
++ #include "rtl8723d/version_rtl8723d.h"
++ #endif
++ #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
++ #ifdef DM_ODM_CE_MAC80211
++ #else
++ #include "rtl8723d_hal.h"
++ #endif
++ #endif
++#endif /* @8723D End */
++
++#if (RTL8710B_SUPPORT == 1)
++ #if (DM_ODM_SUPPORT_TYPE != ODM_AP)
++
++ #include "rtl8710b/halhwimg8710b_bb.h"
++ #include "rtl8710b/halhwimg8710b_mac.h"
++ #include "rtl8710b/halhwimg8710b_rf.h"
++ #include "rtl8710b/phydm_regconfig8710b.h"
++ #include "rtl8710b/hal8710breg.h"
++ #include "rtl8710b/phydm_rtl8710b.h"
++ #include "halrf/rtl8710b/halrf_8710b.h"
++ #include "rtl8710b/version_rtl8710b.h"
++ #endif
++ #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
++ #include "rtl8710b_hal.h"
++ #endif
++#endif /* @8710B End */
++
++#if (RTL8197F_SUPPORT == 1)
++ #include "rtl8197f/halhwimg8197f_mac.h"
++ #include "rtl8197f/halhwimg8197f_rf.h"
++ #include "rtl8197f/halhwimg8197f_bb.h"
++ #include "rtl8197f/phydm_hal_api8197f.h"
++ #include "rtl8197f/version_rtl8197f.h"
++ #include "rtl8197f/phydm_rtl8197f.h"
++ #include "rtl8197f/phydm_regconfig8197f.h"
++ #include "halrf/rtl8197f/halrf_8197f.h"
++ #include "halrf/rtl8197f/halrf_iqk_8197f.h"
++ #include "halrf/rtl8197f/halrf_dpk_8197f.h"
++#endif
++
++#if (RTL8821C_SUPPORT == 1)
++ #include "rtl8821c/phydm_hal_api8821c.h"
++ #include "rtl8821c/halhwimg8821c_mac.h"
++ #include "rtl8821c/halhwimg8821c_rf.h"
++ #include "rtl8821c/halhwimg8821c_bb.h"
++ #include "rtl8821c/phydm_regconfig8821c.h"
++ #include "halrf/rtl8821c/halrf_8821c.h"
++ #include "rtl8821c/version_rtl8821c.h"
++ #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
++ #ifdef DM_ODM_CE_MAC80211
++ #include "../halmac/halmac_reg_8821c.h"
++ #else
++ #include "rtl8821c_hal.h"
++ #endif
++ #endif
++#endif
++
++#if (RTL8192F_SUPPORT == 1)
++ #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
++ #include "rtl8192f_hal.h"/*need to before rf.h*/
++ #endif
++ #include "rtl8192f/halhwimg8192f_mac.h"
++ #include "rtl8192f/halhwimg8192f_rf.h"
++ #include "rtl8192f/halhwimg8192f_bb.h"
++ #include "rtl8192f/phydm_hal_api8192f.h"
++ #include "rtl8192f/version_rtl8192f.h"
++ #include "rtl8192f/phydm_rtl8192f.h"
++ #include "rtl8192f/phydm_regconfig8192f.h"
++ #include "halrf/rtl8192f/halrf_8192f.h"
++ #if (DM_ODM_SUPPORT_TYPE == ODM_AP)
++ #include "halrf/rtl8192f/halrf_dpk_8192f.h"
++ #endif
++#endif
++
++#if (RTL8721D_SUPPORT == 1)
++ #include "halrf/rtl8721d/halrf_8721d.h"
++ #include "rtl8721d/phydm_hal_api8721d.h"
++ #include "rtl8721d/phydm_regconfig8721d.h"
++ #include "rtl8721d/halhwimg8721d_mac.h"
++ #include "rtl8721d/halhwimg8721d_rf.h"
++ #include "rtl8721d/halhwimg8721d_bb.h"
++ #include "rtl8721d/version_rtl8721d.h"
++ #include "rtl8721d/phydm_rtl8721d.h"
++ #include "rtl8721d/hal8721dreg.h"
++ #include
++ #if 0
++ #if (DM_ODM_SUPPORT_TYPE == ODM_AP)
++ #include "halrf/rtl8721d/halrf_dpk_8721d.h"
++ #endif
++ #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
++ #include "rtl8721d_hal.h"
++ #endif
++ #endif
++#endif
++#if (RTL8195B_SUPPORT == 1)
++ #include "halrf/rtl8195b/halrf_8195b.h"
++ #include "rtl8195b/phydm_hal_api8195b.h"
++ #include "rtl8195b/phydm_regconfig8195b.h"
++ #include "rtl8195b/halhwimg8195b_mac.h"
++ #include "rtl8195b/halhwimg8195b_rf.h"
++ #include "rtl8195b/halhwimg8195b_bb.h"
++ #include "rtl8195b/version_rtl8195b.h"
++ #include /*@HAL_DATA_TYPE*/
++#endif
++
++#if (RTL8198F_SUPPORT == 1)
++ #include "rtl8198f/phydm_regconfig8198f.h"
++ #include "rtl8198f/phydm_hal_api8198f.h"
++ #include "rtl8198f/halhwimg8198f_mac.h"
++ #include "rtl8198f/halhwimg8198f_rf.h"
++ #include "rtl8198f/halhwimg8198f_bb.h"
++ #include "rtl8198f/version_rtl8198f.h"
++ #include "halrf/rtl8198f/halrf_8198f.h"
++ #include "halrf/rtl8198f/halrf_iqk_8198f.h"
++#endif
++
++#if (RTL8822C_SUPPORT)
++ #include "rtl8822c/halhwimg8822c_mac.h"
++ #include "rtl8822c/halhwimg8822c_rf.h"
++ #include "rtl8822c/halhwimg8822c_bb.h"
++ #include "rtl8822c/phydm_regconfig8822c.h"
++ #include "halrf/rtl8822c/halrf_8822c.h"
++ #include "rtl8822c/phydm_hal_api8822c.h"
++ #include "rtl8822c/version_rtl8822c.h"
++ #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
++ /* @struct HAL_DATA_TYPE */
++ #include
++ /* @RX_SMOOTH_FACTOR, reg definition and etc.*/
++ #include
++ #endif
++#endif
++#if (RTL8814B_SUPPORT == 1)
++ #include "rtl8814b/halhwimg8814b_mac.h"
++ #include "rtl8814b/halhwimg8814b_rf.h"
++ #include "rtl8814b/halhwimg8814b_bb.h"
++ #include "rtl8814b/phydm_regconfig8814b.h"
++ #include "halrf/rtl8814b/halrf_8814b.h"
++ #include "rtl8814b/phydm_hal_api8814b.h"
++ #include "rtl8814b/version_rtl8814b.h"
++#endif
++#if (RTL8812F_SUPPORT)
++ #include "rtl8812f/halhwimg8812f_mac.h"
++ #include "rtl8812f/halhwimg8812f_rf.h"
++ #include "rtl8812f/halhwimg8812f_bb.h"
++ #include "rtl8812f/phydm_regconfig8812f.h"
++ #include "halrf/rtl8812f/halrf_8812f.h"
++ #include "rtl8812f/phydm_hal_api8812f.h"
++ #include "rtl8812f/version_rtl8812f.h"
++#endif
++#if (RTL8197G_SUPPORT)
++ #include "rtl8197g/halhwimg8197g_mac.h"
++ #include "rtl8197g/halhwimg8197g_rf.h"
++ #include "rtl8197g/halhwimg8197g_bb.h"
++ #include "rtl8197g/phydm_regconfig8197g.h"
++ #include "halrf/rtl8197g/halrf_8197g.h"
++ #include "rtl8197g/phydm_hal_api8197g.h"
++ #include "rtl8197g/version_rtl8197g.h"
++#endif
++#endif /* @__ODM_PRECOMP_H__ */
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/phydm_pre_define.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/phydm_pre_define.h
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/phydm_pre_define.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/phydm_pre_define.h 2021-03-07 18:16:17.064956526 +0200
@@ -0,0 +1,849 @@
+/******************************************************************************
+ *
@@ -251331,531 +248687,9 @@ index 000000000..d8d7313b1
+};
+
+#endif
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_precomp.h linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_precomp.h
-new file mode 100644
-index 000000000..78b8945fc
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_precomp.h
-@@ -0,0 +1,514 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ * The full GNU General Public License is included in this distribution in the
-+ * file called LICENSE.
-+ *
-+ * Contact Information:
-+ * wlanfae
-+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
-+ * Hsinchu 300, Taiwan.
-+ *
-+ * Larry Finger
-+ *
-+ *****************************************************************************/
-+
-+#ifndef __ODM_PRECOMP_H__
-+#define __ODM_PRECOMP_H__
-+
-+#include "phydm_types.h"
-+#include "halrf/halrf_features.h"
-+
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+ #include "Precomp.h" /* @We need to include mp_precomp.h due to batch file setting. */
-+#else
-+ #define TEST_FALG___ 1
-+#endif
-+
-+/* @2 Config Flags and Structs - defined by each ODM type */
-+
-+#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
-+ #include "../8192cd_cfg.h"
-+ #include "../odm_inc.h"
-+
-+ #include "../8192cd.h"
-+ #include "../8192cd_util.h"
-+ #include "../8192cd_hw.h"
-+ #ifdef _BIG_ENDIAN_
-+ #define ODM_ENDIAN_TYPE ODM_ENDIAN_BIG
-+ #else
-+ #define ODM_ENDIAN_TYPE ODM_ENDIAN_LITTLE
-+ #endif
-+
-+ #include "../8192cd_headers.h"
-+ #include "../8192cd_debug.h"
-+
-+#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
-+ #ifdef DM_ODM_CE_MAC80211
-+ #include "../wifi.h"
-+ #include "rtl_phydm.h"
-+ #elif defined(DM_ODM_CE_MAC80211_V2)
-+ #include "../main.h"
-+ #include "../hw.h"
-+ #include "../fw.h"
-+ #endif
-+ #define __PACK
-+ #define __WLAN_ATTRIB_PACK__
-+#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+ #include "mp_precomp.h"
-+ #define ODM_ENDIAN_TYPE ODM_ENDIAN_LITTLE
-+ #define __PACK
-+ #define __WLAN_ATTRIB_PACK__
-+#elif (DM_ODM_SUPPORT_TYPE == ODM_IOT)
-+ #include
-+ #include
-+ #define ODM_ENDIAN_TYPE ODM_ENDIAN_LITTLE
-+ #define __PACK
-+#endif
-+
-+/* @2 OutSrc Header Files */
-+
-+#include "phydm.h"
-+#include "phydm_hwconfig.h"
-+#include "phydm_phystatus.h"
-+#include "phydm_debug.h"
-+#include "phydm_regdefine11ac.h"
-+#include "phydm_regdefine11n.h"
-+#include "phydm_interface.h"
-+#include "phydm_reg.h"
-+#include "halrf/halrf_debug.h"
-+
-+#if (DM_ODM_SUPPORT_TYPE & ODM_CE) && \
-+ (!defined(DM_ODM_CE_MAC80211) && !defined(DM_ODM_CE_MAC80211_V2))
-+
-+void phy_set_tx_power_limit(
-+ struct dm_struct *dm,
-+ u8 *regulation,
-+ u8 *band,
-+ u8 *bandwidth,
-+ u8 *rate_section,
-+ u8 *rf_path,
-+ u8 *channel,
-+ u8 *power_limit);
-+
-+enum hal_status
-+rtw_phydm_fw_iqk(
-+ struct dm_struct *dm,
-+ u8 clear,
-+ u8 segment);
-+
-+enum hal_status
-+rtw_phydm_cfg_phy_para(
-+ struct dm_struct *dm,
-+ enum phydm_halmac_param config_type,
-+ u32 offset,
-+ u32 data,
-+ u32 mask,
-+ enum rf_path e_rf_path,
-+ u32 delay_time);
-+
-+#endif
-+
-+/* @Judy ADD 20180125 */
-+#if (DM_ODM_SUPPORT_TYPE & (ODM_AP | ODM_IOT))
-+#define RTL8710B_SUPPORT 0
-+#endif
-+
-+#if RTL8188E_SUPPORT == 1
-+ #define RTL8188E_T_SUPPORT 1
-+ #ifdef CONFIG_SFW_SUPPORTED
-+ #define RTL8188E_S_SUPPORT 1
-+ #else
-+ #define RTL8188E_S_SUPPORT 0
-+ #endif
-+#endif
-+
-+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
-+#define RTL8197F_SUPPORT 0 /*@Just for PHYDM API development*/
-+#define RTL8195B_SUPPORT 0 /*@Just for PHYDM API development*/
-+#define RTL8198F_SUPPORT 0 /*@Just for PHYDM API development*/
-+#define RTL8812F_SUPPORT 0 /*@Just for PHYDM API development*/
-+#define RTL8197G_SUPPORT 0 /*@Just for PHYDM API development*/
-+#endif
-+
-+#if (RTL8188E_SUPPORT == 1)
-+ #include "rtl8188e/hal8188erateadaptive.h" /* @for RA,Power training */
-+ #include "rtl8188e/halhwimg8188e_mac.h"
-+ #include "rtl8188e/halhwimg8188e_rf.h"
-+ #include "rtl8188e/halhwimg8188e_bb.h"
-+ #include "rtl8188e/phydm_regconfig8188e.h"
-+ #include "rtl8188e/phydm_rtl8188e.h"
-+ #include "rtl8188e/hal8188ereg.h"
-+ #include "rtl8188e/version_rtl8188e.h"
-+ #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
-+ #include "rtl8188e_hal.h"
-+ #include "halrf/rtl8188e/halrf_8188e_ce.h"
-+ #endif
-+ #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+ #include "halrf/rtl8188e/halrf_8188e_win.h"
-+ #endif
-+ #if (DM_ODM_SUPPORT_TYPE == ODM_AP)
-+ #include "halrf/rtl8188e/halrf_8188e_ap.h"
-+ #endif
-+#endif /* @88E END */
-+
-+#if (RTL8192E_SUPPORT == 1)
-+
-+ #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+ #include "halrf/rtl8192e/halrf_8192e_win.h" /*@FOR_8192E_IQK*/
-+ #elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
-+ #include "halrf/rtl8192e/halrf_8192e_ap.h" /*@FOR_8192E_IQK*/
-+ #elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
-+ #include "halrf/rtl8192e/halrf_8192e_ce.h" /*@FOR_8192E_IQK*/
-+ #endif
-+
-+ #include "rtl8192e/phydm_rtl8192e.h" /* @FOR_8192E_IQK */
-+ #include "rtl8192e/version_rtl8192e.h"
-+ #if (DM_ODM_SUPPORT_TYPE != ODM_AP)
-+ #include "rtl8192e/halhwimg8192e_bb.h"
-+ #include "rtl8192e/halhwimg8192e_mac.h"
-+ #include "rtl8192e/halhwimg8192e_rf.h"
-+ #include "rtl8192e/phydm_regconfig8192e.h"
-+ #include "rtl8192e/hal8192ereg.h"
-+ #endif
-+ #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
-+ #include "rtl8192e_hal.h"
-+ #endif
-+#endif /* @92E END */
-+
-+#if (RTL8812A_SUPPORT == 1)
-+
-+ #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+ #include "halrf/rtl8812a/halrf_8812a_win.h"
-+ #elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
-+ #include "halrf/rtl8812a/halrf_8812a_ap.h"
-+ #elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
-+ #include "halrf/rtl8812a/halrf_8812a_ce.h"
-+ #endif
-+
-+ /* @#include "halrf/rtl8812a/halrf_8812a.h" */ /* @FOR_8812_IQK */
-+ #if (DM_ODM_SUPPORT_TYPE != ODM_AP)
-+ #include "rtl8812a/halhwimg8812a_bb.h"
-+ #include "rtl8812a/halhwimg8812a_mac.h"
-+ #include "rtl8812a/halhwimg8812a_rf.h"
-+ #include "rtl8812a/phydm_regconfig8812a.h"
-+ #endif
-+ #include "rtl8812a/phydm_rtl8812a.h"
-+
-+ #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
-+ #include "rtl8812a_hal.h"
-+ #endif
-+ #include "rtl8812a/version_rtl8812a.h"
-+
-+#endif /* @8812 END */
-+
-+#if (RTL8814A_SUPPORT == 1)
-+
-+ #include "rtl8814a/halhwimg8814a_mac.h"
-+ #include "rtl8814a/halhwimg8814a_rf.h"
-+ #include "rtl8814a/halhwimg8814a_bb.h"
-+ #include "rtl8814a/version_rtl8814a.h"
-+ #include "rtl8814a/phydm_rtl8814a.h"
-+ #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+ #include "halrf/rtl8814a/halrf_8814a_win.h"
-+ #elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
-+ #include "halrf/rtl8814a/halrf_8814a_ce.h"
-+ #elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
-+ #include "halrf/rtl8814a/halrf_8814a_ap.h"
-+ #endif
-+ #include "rtl8814a/phydm_regconfig8814a.h"
-+ #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
-+ #include "rtl8814a_hal.h"
-+ #include "halrf/rtl8814a/halrf_iqk_8814a.h"
-+ #endif
-+#endif /* @8814 END */
-+
-+#if (RTL8881A_SUPPORT == 1)/* @FOR_8881_IQK */
-+ #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+ #include "halrf/rtl8821a/halrf_iqk_8821a_win.h"
-+ #elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
-+ #include "halrf/rtl8821a/halrf_iqk_8821a_ce.h"
-+ #else
-+ #include "halrf/rtl8821a/halrf_iqk_8821a_ap.h"
-+ #endif
-+ /* @#include "rtl8881a/HalHWImg8881A_BB.h" */
-+ /* @#include "rtl8881a/HalHWImg8881A_MAC.h" */
-+ /* @#include "rtl8881a/HalHWImg8881A_RF.h" */
-+ /* @#include "rtl8881a/odm_RegConfig8881A.h" */
-+#endif
-+
-+#if (RTL8723B_SUPPORT == 1)
-+ #include "rtl8723b/halhwimg8723b_mac.h"
-+ #include "rtl8723b/halhwimg8723b_rf.h"
-+ #include "rtl8723b/halhwimg8723b_bb.h"
-+ #include "rtl8723b/phydm_regconfig8723b.h"
-+ #include "rtl8723b/phydm_rtl8723b.h"
-+ #include "rtl8723b/hal8723breg.h"
-+ #include "rtl8723b/version_rtl8723b.h"
-+ #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+ #include "halrf/rtl8723b/halrf_8723b_win.h"
-+ #elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
-+ #include "halrf/rtl8723b/halrf_8723b_ce.h"
-+ #include "rtl8723b/halhwimg8723b_mp.h"
-+ #include "rtl8723b_hal.h"
-+ #else
-+ #include "halrf/rtl8723b/halrf_8723b_ap.h"
-+ #endif
-+#endif
-+
-+#if (RTL8821A_SUPPORT == 1)
-+ #include "rtl8821a/halhwimg8821a_mac.h"
-+ #include "rtl8821a/halhwimg8821a_rf.h"
-+ #include "rtl8821a/halhwimg8821a_bb.h"
-+ #include "rtl8821a/phydm_regconfig8821a.h"
-+ #include "rtl8821a/phydm_rtl8821a.h"
-+ #include "rtl8821a/version_rtl8821a.h"
-+ #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+ #include "halrf/rtl8821a/halrf_8821a_win.h"
-+ #elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
-+ #include "halrf/rtl8821a/halrf_8821a_ce.h"
-+ #include "halrf/rtl8821a/halrf_iqk_8821a_ce.h"/*@for IQK*/
-+ #include "halrf/rtl8812a/halrf_8812a_ce.h"/*@for IQK,LCK,Power-tracking*/
-+ #include "rtl8812a_hal.h"
-+ #else
-+ #endif
-+#endif
-+
-+#if (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211)
-+#include "../halmac/halmac_reg2.h"
-+#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
-+#include "../halmac/halmac_reg2.h"
-+#endif
-+
-+
-+#if (RTL8822B_SUPPORT == 1)
-+ #include "rtl8822b/halhwimg8822b_mac.h"
-+ #include "rtl8822b/halhwimg8822b_rf.h"
-+ #include "rtl8822b/halhwimg8822b_bb.h"
-+ #include "rtl8822b/phydm_regconfig8822b.h"
-+ #include "halrf/rtl8822b/halrf_8822b.h"
-+ #include "rtl8822b/phydm_rtl8822b.h"
-+ #include "rtl8822b/phydm_hal_api8822b.h"
-+ #include "rtl8822b/version_rtl8822b.h"
-+
-+ #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+ #elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
-+ #ifdef DM_ODM_CE_MAC80211
-+ #include "../halmac/halmac_reg_8822b.h"
-+ #elif defined(DM_ODM_CE_MAC80211_V2)
-+ #include "../halmac/halmac_reg_8822b.h"
-+ #else
-+ #include /* @struct HAL_DATA_TYPE */
-+ #include /* @RX_SMOOTH_FACTOR, reg definition and etc.*/
-+ #endif
-+ #elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
-+ #endif
-+
-+#endif
-+
-+#if (RTL8703B_SUPPORT == 1)
-+ #include "rtl8703b/phydm_rtl8703b.h"
-+ #include "rtl8703b/phydm_regconfig8703b.h"
-+ #include "rtl8703b/halhwimg8703b_mac.h"
-+ #include "rtl8703b/halhwimg8703b_rf.h"
-+ #include "rtl8703b/halhwimg8703b_bb.h"
-+ #include "halrf/rtl8703b/halrf_8703b.h"
-+ #include "rtl8703b/version_rtl8703b.h"
-+ #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
-+ #include "rtl8703b_hal.h"
-+ #endif
-+#endif
-+
-+#if (RTL8188F_SUPPORT == 1)
-+ #include "rtl8188f/halhwimg8188f_mac.h"
-+ #include "rtl8188f/halhwimg8188f_rf.h"
-+ #include "rtl8188f/halhwimg8188f_bb.h"
-+ #include "rtl8188f/hal8188freg.h"
-+ #include "rtl8188f/phydm_rtl8188f.h"
-+ #include "rtl8188f/phydm_regconfig8188f.h"
-+ #include "halrf/rtl8188f/halrf_8188f.h" /*@for IQK,LCK,Power-tracking*/
-+ #include "rtl8188f/version_rtl8188f.h"
-+ #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
-+ #include "rtl8188f_hal.h"
-+ #endif
-+#endif
-+
-+#if (RTL8723D_SUPPORT == 1)
-+ #if (DM_ODM_SUPPORT_TYPE != ODM_AP)
-+
-+ #include "rtl8723d/halhwimg8723d_bb.h"
-+ #include "rtl8723d/halhwimg8723d_mac.h"
-+ #include "rtl8723d/halhwimg8723d_rf.h"
-+ #include "rtl8723d/phydm_regconfig8723d.h"
-+ #include "rtl8723d/hal8723dreg.h"
-+ #include "rtl8723d/phydm_rtl8723d.h"
-+ #include "halrf/rtl8723d/halrf_8723d.h"
-+ #include "rtl8723d/version_rtl8723d.h"
-+ #endif
-+ #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
-+ #ifdef DM_ODM_CE_MAC80211
-+ #else
-+ #include "rtl8723d_hal.h"
-+ #endif
-+ #endif
-+#endif /* @8723D End */
-+
-+#if (RTL8710B_SUPPORT == 1)
-+ #if (DM_ODM_SUPPORT_TYPE != ODM_AP)
-+
-+ #include "rtl8710b/halhwimg8710b_bb.h"
-+ #include "rtl8710b/halhwimg8710b_mac.h"
-+ #include "rtl8710b/halhwimg8710b_rf.h"
-+ #include "rtl8710b/phydm_regconfig8710b.h"
-+ #include "rtl8710b/hal8710breg.h"
-+ #include "rtl8710b/phydm_rtl8710b.h"
-+ #include "halrf/rtl8710b/halrf_8710b.h"
-+ #include "rtl8710b/version_rtl8710b.h"
-+ #endif
-+ #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
-+ #include "rtl8710b_hal.h"
-+ #endif
-+#endif /* @8710B End */
-+
-+#if (RTL8197F_SUPPORT == 1)
-+ #include "rtl8197f/halhwimg8197f_mac.h"
-+ #include "rtl8197f/halhwimg8197f_rf.h"
-+ #include "rtl8197f/halhwimg8197f_bb.h"
-+ #include "rtl8197f/phydm_hal_api8197f.h"
-+ #include "rtl8197f/version_rtl8197f.h"
-+ #include "rtl8197f/phydm_rtl8197f.h"
-+ #include "rtl8197f/phydm_regconfig8197f.h"
-+ #include "halrf/rtl8197f/halrf_8197f.h"
-+ #include "halrf/rtl8197f/halrf_iqk_8197f.h"
-+ #include "halrf/rtl8197f/halrf_dpk_8197f.h"
-+#endif
-+
-+#if (RTL8821C_SUPPORT == 1)
-+ #include "rtl8821c/phydm_hal_api8821c.h"
-+ #include "rtl8821c/halhwimg8821c_mac.h"
-+ #include "rtl8821c/halhwimg8821c_rf.h"
-+ #include "rtl8821c/halhwimg8821c_bb.h"
-+ #include "rtl8821c/phydm_regconfig8821c.h"
-+ #include "halrf/rtl8821c/halrf_8821c.h"
-+ #include "rtl8821c/version_rtl8821c.h"
-+ #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
-+ #ifdef DM_ODM_CE_MAC80211
-+ #include "../halmac/halmac_reg_8821c.h"
-+ #else
-+ #include "rtl8821c_hal.h"
-+ #endif
-+ #endif
-+#endif
-+
-+#if (RTL8192F_SUPPORT == 1)
-+ #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
-+ #include "rtl8192f_hal.h"/*need to before rf.h*/
-+ #endif
-+ #include "rtl8192f/halhwimg8192f_mac.h"
-+ #include "rtl8192f/halhwimg8192f_rf.h"
-+ #include "rtl8192f/halhwimg8192f_bb.h"
-+ #include "rtl8192f/phydm_hal_api8192f.h"
-+ #include "rtl8192f/version_rtl8192f.h"
-+ #include "rtl8192f/phydm_rtl8192f.h"
-+ #include "rtl8192f/phydm_regconfig8192f.h"
-+ #include "halrf/rtl8192f/halrf_8192f.h"
-+ #if (DM_ODM_SUPPORT_TYPE == ODM_AP)
-+ #include "halrf/rtl8192f/halrf_dpk_8192f.h"
-+ #endif
-+#endif
-+
-+#if (RTL8721D_SUPPORT == 1)
-+ #include "halrf/rtl8721d/halrf_8721d.h"
-+ #include "rtl8721d/phydm_hal_api8721d.h"
-+ #include "rtl8721d/phydm_regconfig8721d.h"
-+ #include "rtl8721d/halhwimg8721d_mac.h"
-+ #include "rtl8721d/halhwimg8721d_rf.h"
-+ #include "rtl8721d/halhwimg8721d_bb.h"
-+ #include "rtl8721d/version_rtl8721d.h"
-+ #include "rtl8721d/phydm_rtl8721d.h"
-+ #include "rtl8721d/hal8721dreg.h"
-+ #include
-+ #if 0
-+ #if (DM_ODM_SUPPORT_TYPE == ODM_AP)
-+ #include "halrf/rtl8721d/halrf_dpk_8721d.h"
-+ #endif
-+ #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
-+ #include "rtl8721d_hal.h"
-+ #endif
-+ #endif
-+#endif
-+#if (RTL8195B_SUPPORT == 1)
-+ #include "halrf/rtl8195b/halrf_8195b.h"
-+ #include "rtl8195b/phydm_hal_api8195b.h"
-+ #include "rtl8195b/phydm_regconfig8195b.h"
-+ #include "rtl8195b/halhwimg8195b_mac.h"
-+ #include "rtl8195b/halhwimg8195b_rf.h"
-+ #include "rtl8195b/halhwimg8195b_bb.h"
-+ #include "rtl8195b/version_rtl8195b.h"
-+ #include /*@HAL_DATA_TYPE*/
-+#endif
-+
-+#if (RTL8198F_SUPPORT == 1)
-+ #include "rtl8198f/phydm_regconfig8198f.h"
-+ #include "rtl8198f/phydm_hal_api8198f.h"
-+ #include "rtl8198f/halhwimg8198f_mac.h"
-+ #include "rtl8198f/halhwimg8198f_rf.h"
-+ #include "rtl8198f/halhwimg8198f_bb.h"
-+ #include "rtl8198f/version_rtl8198f.h"
-+ #include "halrf/rtl8198f/halrf_8198f.h"
-+ #include "halrf/rtl8198f/halrf_iqk_8198f.h"
-+#endif
-+
-+#if (RTL8822C_SUPPORT)
-+ #include "rtl8822c/halhwimg8822c_mac.h"
-+ #include "rtl8822c/halhwimg8822c_rf.h"
-+ #include "rtl8822c/halhwimg8822c_bb.h"
-+ #include "rtl8822c/phydm_regconfig8822c.h"
-+ #include "halrf/rtl8822c/halrf_8822c.h"
-+ #include "rtl8822c/phydm_hal_api8822c.h"
-+ #include "rtl8822c/version_rtl8822c.h"
-+ #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
-+ /* @struct HAL_DATA_TYPE */
-+ #include
-+ /* @RX_SMOOTH_FACTOR, reg definition and etc.*/
-+ #include
-+ #endif
-+#endif
-+#if (RTL8814B_SUPPORT == 1)
-+ #include "rtl8814b/halhwimg8814b_mac.h"
-+ #include "rtl8814b/halhwimg8814b_rf.h"
-+ #include "rtl8814b/halhwimg8814b_bb.h"
-+ #include "rtl8814b/phydm_regconfig8814b.h"
-+ #include "halrf/rtl8814b/halrf_8814b.h"
-+ #include "rtl8814b/phydm_hal_api8814b.h"
-+ #include "rtl8814b/version_rtl8814b.h"
-+#endif
-+#if (RTL8812F_SUPPORT)
-+ #include "rtl8812f/halhwimg8812f_mac.h"
-+ #include "rtl8812f/halhwimg8812f_rf.h"
-+ #include "rtl8812f/halhwimg8812f_bb.h"
-+ #include "rtl8812f/phydm_regconfig8812f.h"
-+ #include "halrf/rtl8812f/halrf_8812f.h"
-+ #include "rtl8812f/phydm_hal_api8812f.h"
-+ #include "rtl8812f/version_rtl8812f.h"
-+#endif
-+#if (RTL8197G_SUPPORT)
-+ #include "rtl8197g/halhwimg8197g_mac.h"
-+ #include "rtl8197g/halhwimg8197g_rf.h"
-+ #include "rtl8197g/halhwimg8197g_bb.h"
-+ #include "rtl8197g/phydm_regconfig8197g.h"
-+ #include "halrf/rtl8197g/halrf_8197g.h"
-+ #include "rtl8197g/phydm_hal_api8197g.h"
-+ #include "rtl8197g/version_rtl8197g.h"
-+#endif
-+#endif /* @__ODM_PRECOMP_H__ */
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_primary_cca.c linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_primary_cca.c
-new file mode 100644
-index 000000000..dec6c5365
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_primary_cca.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/phydm_primary_cca.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/phydm_primary_cca.c
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/phydm_primary_cca.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/phydm_primary_cca.c 2021-03-07 18:16:17.064956526 +0200
@@ -0,0 +1,173 @@
+/******************************************************************************
+ *
@@ -252030,11 +248864,9 @@ index 000000000..dec6c5365
+#endif
+}
+#endif
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_primary_cca.h linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_primary_cca.h
-new file mode 100644
-index 000000000..9a647502d
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_primary_cca.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/phydm_primary_cca.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/phydm_primary_cca.h
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/phydm_primary_cca.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/phydm_primary_cca.h 2021-03-07 18:16:17.064956526 +0200
@@ -0,0 +1,87 @@
+/******************************************************************************
+ *
@@ -252123,11 +248955,9 @@ index 000000000..9a647502d
+#endif /*@#ifdef PHYDM_PRIMARY_CCA*/
+#endif /*@#ifndef __PHYDM_PRIMARYCCA_H__*/
+
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_psd.c linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_psd.c
-new file mode 100644
-index 000000000..458677b59
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_psd.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/phydm_psd.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/phydm_psd.c
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/phydm_psd.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/phydm_psd.c 2021-03-07 18:16:17.064956526 +0200
@@ -0,0 +1,459 @@
+/******************************************************************************
+ *
@@ -252588,11 +249418,9 @@ index 000000000..458677b59
+}
+
+#endif
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_psd.h linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_psd.h
-new file mode 100644
-index 000000000..635a887cb
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_psd.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/phydm_psd.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/phydm_psd.h
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/phydm_psd.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/phydm_psd.h 2021-03-07 18:16:17.064956526 +0200
@@ -0,0 +1,66 @@
+/******************************************************************************
+ *
@@ -252660,11 +249488,9 @@ index 000000000..635a887cb
+
+#endif
+#endif
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_rainfo.c linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_rainfo.c
-new file mode 100644
-index 000000000..077585dfc
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_rainfo.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/phydm_rainfo.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/phydm_rainfo.c
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/phydm_rainfo.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/phydm_rainfo.c 2021-03-07 18:16:17.064956526 +0200
@@ -0,0 +1,2085 @@
+/******************************************************************************
+ *
@@ -254751,11 +251577,9 @@ index 000000000..077585dfc
+}
+
+#endif
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_rainfo.h linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_rainfo.h
-new file mode 100644
-index 000000000..a840880a4
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_rainfo.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/phydm_rainfo.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/phydm_rainfo.h
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/phydm_rainfo.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/phydm_rainfo.h 2021-03-07 18:16:17.065956573 +0200
@@ -0,0 +1,276 @@
+/******************************************************************************
+ *
@@ -255033,11 +251857,345 @@ index 000000000..a840880a4
+ void *dm_void);
+#endif
+#endif /*@#ifndef __PHYDMRAINFO_H__*/
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_reg.h linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_reg.h
-new file mode 100644
-index 000000000..310322479
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_reg.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/phydm_regdefine11ac.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/phydm_regdefine11ac.h
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/phydm_regdefine11ac.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/phydm_regdefine11ac.h 2021-03-07 18:16:17.065956573 +0200
+@@ -0,0 +1,109 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * The full GNU General Public License is included in this distribution in the
++ * file called LICENSE.
++ *
++ * Contact Information:
++ * wlanfae
++ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
++ * Hsinchu 300, Taiwan.
++ *
++ * Larry Finger
++ *
++ *****************************************************************************/
++
++#ifndef __ODM_REGDEFINE11AC_H__
++#define __ODM_REGDEFINE11AC_H__
++
++/* @2 RF REG LIST */
++
++
++
++/* @2 BB REG LIST */
++/* PAGE 8 */
++#define ODM_REG_CCK_RPT_FORMAT_11AC 0x804
++#define ODM_REG_BB_RX_PATH_11AC 0x808
++#define ODM_REG_BB_TX_PATH_11AC 0x80c
++#define ODM_REG_BB_ATC_11AC 0x860
++#define ODM_REG_EDCCA_POWER_CAL 0x8dc
++#define ODM_REG_DBG_RPT_11AC 0x8fc
++/* PAGE 9 */
++#define ODM_REG_EDCCA_DOWN_OPT 0x900
++#define ODM_REG_ACBB_EDCCA_ENHANCE 0x944
++#define odm_adc_trigger_jaguar2 0x95C /*@ADC sample mode*/
++#define ODM_REG_OFDM_FA_RST_11AC 0x9A4
++#define ODM_REG_CCX_PERIOD_11AC 0x990
++#define ODM_REG_NHM_TH9_TH10_11AC 0x994
++#define ODM_REG_CLM_11AC 0x994
++#define ODM_REG_NHM_TH3_TO_TH0_11AC 0x998
++#define ODM_REG_NHM_TH7_TO_TH4_11AC 0x99c
++#define ODM_REG_NHM_TH8_11AC 0x9a0
++#define ODM_REG_NHM_9E8_11AC 0x9e8
++#define ODM_REG_CSI_CONTENT_VALUE 0x9b4
++/* PAGE A */
++#define ODM_REG_CCK_CCA_11AC 0xA0A
++#define ODM_REG_CCK_FA_RST_11AC 0xA2C
++#define ODM_REG_CCK_FA_11AC 0xA5C
++/* PAGE B */
++#define ODM_REG_RST_RPT_11AC 0xB58
++/* PAGE C */
++#define ODM_REG_TRMUX_11AC 0xC08
++#define ODM_REG_IGI_A_11AC 0xC50
++/* PAGE E */
++#define ODM_REG_IGI_B_11AC 0xE50
++#define ODM_REG_ANT_11AC_B 0xE08
++/* PAGE F */
++#define ODM_REG_CCK_CRC32_CNT_11AC 0xF04
++#define ODM_REG_CCK_CCA_CNT_11AC 0xF08
++#define ODM_REG_VHT_CRC32_CNT_11AC 0xF0c
++#define ODM_REG_HT_CRC32_CNT_11AC 0xF10
++#define ODM_REG_OFDM_CRC32_CNT_11AC 0xF14
++#define ODM_REG_OFDM_FA_11AC 0xF48
++#define ODM_REG_OFDM_FA_TYPE1_11AC 0xFCC
++#define ODM_REG_OFDM_FA_TYPE2_11AC 0xFD0
++#define ODM_REG_OFDM_FA_TYPE3_11AC 0xFBC
++#define ODM_REG_OFDM_FA_TYPE4_11AC 0xFC0
++#define ODM_REG_OFDM_FA_TYPE5_11AC 0xFC4
++#define ODM_REG_OFDM_FA_TYPE6_11AC 0xFC8
++#define ODM_REG_RPT_11AC 0xfa0
++#define ODM_REG_CLM_RESULT_11AC 0xfa4
++#define ODM_REG_NHM_CNT_11AC 0xfa8
++#define ODM_REG_NHM_DUR_READY_11AC 0xfb4
++
++#define ODM_REG_NHM_CNT7_TO_CNT4_11AC 0xfac
++#define ODM_REG_NHM_CNT11_TO_CNT8_11AC 0xfb0
++/* PAGE 18 */
++#define ODM_REG_IGI_C_11AC 0x1850
++/* PAGE 1A */
++#define ODM_REG_IGI_D_11AC 0x1A50
++
++/* PAGE 1D */
++#define ODM_REG_IGI_11AC3 0x1D70
++
++/* @2 MAC REG LIST */
++#define ODM_REG_RESP_TX_11AC 0x6D8
++
++
++
++/* @DIG Related */
++#define ODM_BIT_IGI_11AC 0x0000007F
++#define ODM_BIT_IGI_B_11AC3 0x00007F00
++#define ODM_BIT_IGI_C_11AC3 0x007F0000
++#define ODM_BIT_IGI_D_11AC3 0x7F000000
++#define ODM_BIT_CCK_RPT_FORMAT_11AC BIT(16)
++#define ODM_BIT_BB_RX_PATH_11AC 0xF
++#define ODM_BIT_BB_TX_PATH_11AC 0xF
++#define ODM_BIT_BB_ATC_11AC BIT(14)
++
++#endif
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/phydm_regdefine11n.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/phydm_regdefine11n.h
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/phydm_regdefine11n.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/phydm_regdefine11n.h 2021-03-07 18:16:17.065956573 +0200
+@@ -0,0 +1,219 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * The full GNU General Public License is included in this distribution in the
++ * file called LICENSE.
++ *
++ * Contact Information:
++ * wlanfae
++ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
++ * Hsinchu 300, Taiwan.
++ *
++ * Larry Finger
++ *
++ *****************************************************************************/
++
++#ifndef __ODM_REGDEFINE11N_H__
++#define __ODM_REGDEFINE11N_H__
++
++/* @2 RF REG LIST */
++#define ODM_REG_RF_MODE_11N 0x00
++#define ODM_REG_RF_0B_11N 0x0B
++#define ODM_REG_CHNBW_11N 0x18
++#define ODM_REG_T_METER_11N 0x24
++#define ODM_REG_RF_25_11N 0x25
++#define ODM_REG_RF_26_11N 0x26
++#define ODM_REG_RF_27_11N 0x27
++#define ODM_REG_RF_2B_11N 0x2B
++#define ODM_REG_RF_2C_11N 0x2C
++#define ODM_REG_RXRF_A3_11N 0x3C
++#define ODM_REG_T_METER_92D_11N 0x42
++#define ODM_REG_T_METER_88E_11N 0x42
++
++
++
++/* @2 BB REG LIST
++ * PAGE 8
++ */
++#define ODM_REG_BB_CTRL_11N 0x800
++#define ODM_REG_RF_PIN_11N 0x804
++#define ODM_REG_PSD_CTRL_11N 0x808
++#define ODM_REG_TX_ANT_CTRL_11N 0x80C
++#define ODM_REG_BB_PWR_SAV5_11N 0x818
++#define ODM_REG_CCK_RPT_FORMAT_11N 0x824
++#define ODM_REG_CCK_RPT_FORMAT_11N_B 0x82C
++#define ODM_REG_RX_DEFAULT_A_11N 0x858
++#define ODM_REG_RX_DEFAULT_B_11N 0x85A
++#define ODM_REG_BB_PWR_SAV3_11N 0x85C
++#define ODM_REG_ANTSEL_CTRL_11N 0x860
++#define ODM_REG_RX_ANT_CTRL_11N 0x864
++#define ODM_REG_PIN_CTRL_11N 0x870
++#define ODM_REG_BB_PWR_SAV1_11N 0x874
++#define ODM_REG_ANTSEL_PATH_11N 0x878
++#define ODM_REG_BB_3WIRE_11N 0x88C
++#define ODM_REG_SC_CNT_11N 0x8C4
++#define ODM_REG_PSD_DATA_11N 0x8B4
++#define ODM_REG_CCX_PERIOD_11N 0x894
++#define ODM_REG_NHM_TH9_TH10_11N 0x890
++#define ODM_REG_CLM_11N 0x890
++#define ODM_REG_NHM_TH3_TO_TH0_11N 0x898
++#define ODM_REG_NHM_TH7_TO_TH4_11N 0x89c
++#define ODM_REG_NHM_TH8_11N 0xe28
++#define ODM_REG_CLM_READY_11N 0x8b4
++#define ODM_REG_CLM_RESULT_11N 0x8d0
++#define ODM_REG_NHM_CNT_11N 0x8d8
++
++/* @For struct acs_info, Jeffery, 2014-12-26 */
++#define ODM_REG_NHM_CNT7_TO_CNT4_11N 0x8dc
++#define ODM_REG_NHM_CNT9_TO_CNT8_11N 0x8d0
++#define ODM_REG_NHM_CNT10_TO_CNT11_11N 0x8d4
++
++/* PAGE 9 */
++#define ODM_REG_BB_CTRL_PAGE9_11N 0x900
++#define ODM_REG_DBG_RPT_11N 0x908
++#define ODM_REG_BB_TX_PATH_11N 0x90c
++#define ODM_REG_ANT_MAPPING1_11N 0x914
++#define ODM_REG_ANT_MAPPING2_11N 0x918
++#define ODM_REG_EDCCA_DOWN_OPT_11N 0x948
++#define ODM_REG_RX_DFIR_MOD_97F 0x948
++#define ODM_REG_SOML_97F 0x998
++
++/* PAGE A */
++#define ODM_REG_CCK_ANTDIV_PARA1_11N 0xA00
++#define ODM_REG_CCK_ANT_SEL_11N 0xA04
++#define ODM_REG_CCK_CCA_11N 0xA0A
++#define ODM_REG_CCK_ANTDIV_PARA2_11N 0xA0C
++#define ODM_REG_CCK_ANTDIV_PARA3_11N 0xA10
++#define ODM_REG_CCK_ANTDIV_PARA4_11N 0xA14
++#define ODM_REG_CCK_FILTER_PARA1_11N 0xA22
++#define ODM_REG_CCK_FILTER_PARA2_11N 0xA23
++#define ODM_REG_CCK_FILTER_PARA3_11N 0xA24
++#define ODM_REG_CCK_FILTER_PARA4_11N 0xA25
++#define ODM_REG_CCK_FILTER_PARA5_11N 0xA26
++#define ODM_REG_CCK_FILTER_PARA6_11N 0xA27
++#define ODM_REG_CCK_FILTER_PARA7_11N 0xA28
++#define ODM_REG_CCK_FILTER_PARA8_11N 0xA29
++#define ODM_REG_CCK_FA_RST_11N 0xA2C
++#define ODM_REG_CCK_FA_MSB_11N 0xA58
++#define ODM_REG_CCK_FA_LSB_11N 0xA5C
++#define ODM_REG_CCK_CCA_CNT_11N 0xA60
++#define ODM_REG_BB_PWR_SAV4_11N 0xA74
++/* PAGE B */
++#define ODM_REG_LNA_SWITCH_11N 0xB2C
++#define ODM_REG_PATH_SWITCH_11N 0xB30
++#define ODM_REG_RSSI_CTRL_11N 0xB38
++#define ODM_REG_CONFIG_ANTA_11N 0xB68
++#define ODM_REG_RSSI_BT_11N 0xB9C
++#define ODM_REG_RXCK_RFMOD 0xBB0
++#define ODM_REG_EDCCA_DCNF_97F 0xBC0
++
++/* PAGE C */
++#define ODM_REG_OFDM_FA_HOLDC_11N 0xC00
++#define ODM_REG_BB_RX_PATH_11N 0xC04
++#define ODM_REG_TRMUX_11N 0xC08
++#define ODM_REG_OFDM_FA_RSTC_11N 0xC0C
++#define ODM_REG_DOWNSAM_FACTOR_11N 0xC10
++#define ODM_REG_RXIQI_MATRIX_11N 0xC14
++#define ODM_REG_TXIQK_MATRIX_LSB1_11N 0xC4C
++#define ODM_REG_IGI_A_11N 0xC50
++#define ODM_REG_ANTDIV_PARA2_11N 0xC54
++#define ODM_REG_IGI_B_11N 0xC58
++#define ODM_REG_ANTDIV_PARA3_11N 0xC5C
++#define ODM_REG_L1SBD_PD_CH_11N 0XC6C
++#define ODM_REG_BB_PWR_SAV2_11N 0xC70
++#define ODM_REG_BB_AGC_SET_2_11N 0xc74
++#define ODM_REG_RX_OFF_11N 0xC7C
++#define ODM_REG_TXIQK_MATRIXA_11N 0xC80
++#define ODM_REG_TXIQK_MATRIXB_11N 0xC88
++#define ODM_REG_TXIQK_MATRIXA_LSB2_11N 0xC94
++#define ODM_REG_TXIQK_MATRIXB_LSB2_11N 0xC9C
++#define ODM_REG_RXIQK_MATRIX_LSB_11N 0xCA0
++#define ODM_REG_ANTDIV_PARA1_11N 0xCA4
++#define ODM_REG_SMALL_BANDWIDTH_11N 0xCE4
++#define ODM_REG_OFDM_FA_TYPE1_11N 0xCF0
++/* PAGE D */
++#define ODM_REG_OFDM_FA_RSTD_11N 0xD00
++#define ODM_REG_BB_RX_ANT_11N 0xD04
++#define ODM_REG_BB_ATC_11N 0xD2C
++#define ODM_REG_OFDM_FA_TYPE2_11N 0xDA0
++#define ODM_REG_OFDM_FA_TYPE3_11N 0xDA4
++#define ODM_REG_OFDM_FA_TYPE4_11N 0xDA8
++#define ODM_REG_RPT_11N 0xDF4
++/* PAGE E */
++#define ODM_REG_TXAGC_A_6_18_11N 0xE00
++#define ODM_REG_TXAGC_A_24_54_11N 0xE04
++#define ODM_REG_TXAGC_A_1_MCS32_11N 0xE08
++#define ODM_REG_TXAGC_A_MCS0_3_11N 0xE10
++#define ODM_REG_TXAGC_A_MCS4_7_11N 0xE14
++#define ODM_REG_TXAGC_A_MCS8_11_11N 0xE18
++#define ODM_REG_TXAGC_A_MCS12_15_11N 0xE1C
++#define ODM_REG_EDCCA_DCNF_11N 0xE24
++#define ODM_REG_TAP_UPD_97F 0xE24
++#define ODM_REG_FPGA0_IQK_11N 0xE28
++#define ODM_REG_PAGE_B1_97F 0xE28
++#define ODM_REG_TXIQK_TONE_A_11N 0xE30
++#define ODM_REG_RXIQK_TONE_A_11N 0xE34
++#define ODM_REG_TXIQK_PI_A_11N 0xE38
++#define ODM_REG_RXIQK_PI_A_11N 0xE3C
++#define ODM_REG_TXIQK_11N 0xE40
++#define ODM_REG_RXIQK_11N 0xE44
++#define ODM_REG_IQK_AGC_PTS_11N 0xE48
++#define ODM_REG_IQK_AGC_RSP_11N 0xE4C
++#define ODM_REG_BLUETOOTH_11N 0xE6C
++#define ODM_REG_RX_WAIT_CCA_11N 0xE70
++#define ODM_REG_TX_CCK_RFON_11N 0xE74
++#define ODM_REG_TX_CCK_BBON_11N 0xE78
++#define ODM_REG_OFDM_RFON_11N 0xE7C
++#define ODM_REG_OFDM_BBON_11N 0xE80
++#define ODM_REG_TX2RX_11N 0xE84
++#define ODM_REG_TX2TX_11N 0xE88
++#define ODM_REG_RX_CCK_11N 0xE8C
++#define ODM_REG_RX_OFDM_11N 0xED0
++#define ODM_REG_RX_WAIT_RIFS_11N 0xED4
++#define ODM_REG_RX2RX_11N 0xED8
++#define ODM_REG_STANDBY_11N 0xEDC
++#define ODM_REG_SLEEP_11N 0xEE0
++#define ODM_REG_PMPD_ANAEN_11N 0xEEC
++/* PAGE F */
++#define ODM_REG_PAGE_F_RST_11N 0xF14
++#define ODM_REG_IGI_C_11N 0xF84
++#define ODM_REG_IGI_D_11N 0xF88
++#define ODM_REG_CCK_CRC32_ERROR_CNT_11N 0xF84
++#define ODM_REG_CCK_CRC32_OK_CNT_11N 0xF88
++#define ODM_REG_HT_CRC32_CNT_11N 0xF90
++#define ODM_REG_OFDM_CRC32_CNT_11N 0xF94
++#define ODM_REG_HT_CRC32_CNT_11N_AGG 0xFB8
++
++/* @2 MAC REG LIST */
++#define ODM_REG_BB_RST_11N 0x02
++#define ODM_REG_ANTSEL_PIN_11N 0x4C
++#define ODM_REG_EARLY_MODE_11N 0x4D0
++#define ODM_REG_RSSI_MONITOR_11N 0x4FE
++#define ODM_REG_EDCA_VO_11N 0x500
++#define ODM_REG_EDCA_VI_11N 0x504
++#define ODM_REG_EDCA_BE_11N 0x508
++#define ODM_REG_EDCA_BK_11N 0x50C
++#define ODM_REG_TXPAUSE_11N 0x522
++#define ODM_REG_RESP_TX_11N 0x6D8
++#define ODM_REG_ANT_TRAIN_PARA1_11N 0x7b0
++#define ODM_REG_ANT_TRAIN_PARA2_11N 0x7b4
++
++
++/* @DIG Related */
++#define ODM_BIT_IGI_11N 0x0000007F
++#define ODM_BIT_CCK_RPT_FORMAT_11N BIT(9)
++#define ODM_BIT_BB_RX_PATH_11N 0xF
++#define ODM_BIT_BB_TX_PATH_11N 0xF
++#define ODM_BIT_BB_ATC_11N BIT(11)
++#endif
++
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/phydm_reg.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/phydm_reg.h
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/phydm_reg.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/phydm_reg.h 2021-03-07 18:16:17.065956573 +0200
@@ -0,0 +1,241 @@
+/******************************************************************************
+ *
@@ -255280,351 +252438,9 @@ index 000000000..310322479
+#define BIT_FA_RESET BIT(0)
+
+#endif
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_regdefine11ac.h linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_regdefine11ac.h
-new file mode 100644
-index 000000000..7824ac22c
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_regdefine11ac.h
-@@ -0,0 +1,109 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ * The full GNU General Public License is included in this distribution in the
-+ * file called LICENSE.
-+ *
-+ * Contact Information:
-+ * wlanfae
-+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
-+ * Hsinchu 300, Taiwan.
-+ *
-+ * Larry Finger
-+ *
-+ *****************************************************************************/
-+
-+#ifndef __ODM_REGDEFINE11AC_H__
-+#define __ODM_REGDEFINE11AC_H__
-+
-+/* @2 RF REG LIST */
-+
-+
-+
-+/* @2 BB REG LIST */
-+/* PAGE 8 */
-+#define ODM_REG_CCK_RPT_FORMAT_11AC 0x804
-+#define ODM_REG_BB_RX_PATH_11AC 0x808
-+#define ODM_REG_BB_TX_PATH_11AC 0x80c
-+#define ODM_REG_BB_ATC_11AC 0x860
-+#define ODM_REG_EDCCA_POWER_CAL 0x8dc
-+#define ODM_REG_DBG_RPT_11AC 0x8fc
-+/* PAGE 9 */
-+#define ODM_REG_EDCCA_DOWN_OPT 0x900
-+#define ODM_REG_ACBB_EDCCA_ENHANCE 0x944
-+#define odm_adc_trigger_jaguar2 0x95C /*@ADC sample mode*/
-+#define ODM_REG_OFDM_FA_RST_11AC 0x9A4
-+#define ODM_REG_CCX_PERIOD_11AC 0x990
-+#define ODM_REG_NHM_TH9_TH10_11AC 0x994
-+#define ODM_REG_CLM_11AC 0x994
-+#define ODM_REG_NHM_TH3_TO_TH0_11AC 0x998
-+#define ODM_REG_NHM_TH7_TO_TH4_11AC 0x99c
-+#define ODM_REG_NHM_TH8_11AC 0x9a0
-+#define ODM_REG_NHM_9E8_11AC 0x9e8
-+#define ODM_REG_CSI_CONTENT_VALUE 0x9b4
-+/* PAGE A */
-+#define ODM_REG_CCK_CCA_11AC 0xA0A
-+#define ODM_REG_CCK_FA_RST_11AC 0xA2C
-+#define ODM_REG_CCK_FA_11AC 0xA5C
-+/* PAGE B */
-+#define ODM_REG_RST_RPT_11AC 0xB58
-+/* PAGE C */
-+#define ODM_REG_TRMUX_11AC 0xC08
-+#define ODM_REG_IGI_A_11AC 0xC50
-+/* PAGE E */
-+#define ODM_REG_IGI_B_11AC 0xE50
-+#define ODM_REG_ANT_11AC_B 0xE08
-+/* PAGE F */
-+#define ODM_REG_CCK_CRC32_CNT_11AC 0xF04
-+#define ODM_REG_CCK_CCA_CNT_11AC 0xF08
-+#define ODM_REG_VHT_CRC32_CNT_11AC 0xF0c
-+#define ODM_REG_HT_CRC32_CNT_11AC 0xF10
-+#define ODM_REG_OFDM_CRC32_CNT_11AC 0xF14
-+#define ODM_REG_OFDM_FA_11AC 0xF48
-+#define ODM_REG_OFDM_FA_TYPE1_11AC 0xFCC
-+#define ODM_REG_OFDM_FA_TYPE2_11AC 0xFD0
-+#define ODM_REG_OFDM_FA_TYPE3_11AC 0xFBC
-+#define ODM_REG_OFDM_FA_TYPE4_11AC 0xFC0
-+#define ODM_REG_OFDM_FA_TYPE5_11AC 0xFC4
-+#define ODM_REG_OFDM_FA_TYPE6_11AC 0xFC8
-+#define ODM_REG_RPT_11AC 0xfa0
-+#define ODM_REG_CLM_RESULT_11AC 0xfa4
-+#define ODM_REG_NHM_CNT_11AC 0xfa8
-+#define ODM_REG_NHM_DUR_READY_11AC 0xfb4
-+
-+#define ODM_REG_NHM_CNT7_TO_CNT4_11AC 0xfac
-+#define ODM_REG_NHM_CNT11_TO_CNT8_11AC 0xfb0
-+/* PAGE 18 */
-+#define ODM_REG_IGI_C_11AC 0x1850
-+/* PAGE 1A */
-+#define ODM_REG_IGI_D_11AC 0x1A50
-+
-+/* PAGE 1D */
-+#define ODM_REG_IGI_11AC3 0x1D70
-+
-+/* @2 MAC REG LIST */
-+#define ODM_REG_RESP_TX_11AC 0x6D8
-+
-+
-+
-+/* @DIG Related */
-+#define ODM_BIT_IGI_11AC 0x0000007F
-+#define ODM_BIT_IGI_B_11AC3 0x00007F00
-+#define ODM_BIT_IGI_C_11AC3 0x007F0000
-+#define ODM_BIT_IGI_D_11AC3 0x7F000000
-+#define ODM_BIT_CCK_RPT_FORMAT_11AC BIT(16)
-+#define ODM_BIT_BB_RX_PATH_11AC 0xF
-+#define ODM_BIT_BB_TX_PATH_11AC 0xF
-+#define ODM_BIT_BB_ATC_11AC BIT(14)
-+
-+#endif
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_regdefine11n.h linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_regdefine11n.h
-new file mode 100644
-index 000000000..e36f37df6
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_regdefine11n.h
-@@ -0,0 +1,219 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ * The full GNU General Public License is included in this distribution in the
-+ * file called LICENSE.
-+ *
-+ * Contact Information:
-+ * wlanfae
-+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
-+ * Hsinchu 300, Taiwan.
-+ *
-+ * Larry Finger
-+ *
-+ *****************************************************************************/
-+
-+#ifndef __ODM_REGDEFINE11N_H__
-+#define __ODM_REGDEFINE11N_H__
-+
-+/* @2 RF REG LIST */
-+#define ODM_REG_RF_MODE_11N 0x00
-+#define ODM_REG_RF_0B_11N 0x0B
-+#define ODM_REG_CHNBW_11N 0x18
-+#define ODM_REG_T_METER_11N 0x24
-+#define ODM_REG_RF_25_11N 0x25
-+#define ODM_REG_RF_26_11N 0x26
-+#define ODM_REG_RF_27_11N 0x27
-+#define ODM_REG_RF_2B_11N 0x2B
-+#define ODM_REG_RF_2C_11N 0x2C
-+#define ODM_REG_RXRF_A3_11N 0x3C
-+#define ODM_REG_T_METER_92D_11N 0x42
-+#define ODM_REG_T_METER_88E_11N 0x42
-+
-+
-+
-+/* @2 BB REG LIST
-+ * PAGE 8
-+ */
-+#define ODM_REG_BB_CTRL_11N 0x800
-+#define ODM_REG_RF_PIN_11N 0x804
-+#define ODM_REG_PSD_CTRL_11N 0x808
-+#define ODM_REG_TX_ANT_CTRL_11N 0x80C
-+#define ODM_REG_BB_PWR_SAV5_11N 0x818
-+#define ODM_REG_CCK_RPT_FORMAT_11N 0x824
-+#define ODM_REG_CCK_RPT_FORMAT_11N_B 0x82C
-+#define ODM_REG_RX_DEFAULT_A_11N 0x858
-+#define ODM_REG_RX_DEFAULT_B_11N 0x85A
-+#define ODM_REG_BB_PWR_SAV3_11N 0x85C
-+#define ODM_REG_ANTSEL_CTRL_11N 0x860
-+#define ODM_REG_RX_ANT_CTRL_11N 0x864
-+#define ODM_REG_PIN_CTRL_11N 0x870
-+#define ODM_REG_BB_PWR_SAV1_11N 0x874
-+#define ODM_REG_ANTSEL_PATH_11N 0x878
-+#define ODM_REG_BB_3WIRE_11N 0x88C
-+#define ODM_REG_SC_CNT_11N 0x8C4
-+#define ODM_REG_PSD_DATA_11N 0x8B4
-+#define ODM_REG_CCX_PERIOD_11N 0x894
-+#define ODM_REG_NHM_TH9_TH10_11N 0x890
-+#define ODM_REG_CLM_11N 0x890
-+#define ODM_REG_NHM_TH3_TO_TH0_11N 0x898
-+#define ODM_REG_NHM_TH7_TO_TH4_11N 0x89c
-+#define ODM_REG_NHM_TH8_11N 0xe28
-+#define ODM_REG_CLM_READY_11N 0x8b4
-+#define ODM_REG_CLM_RESULT_11N 0x8d0
-+#define ODM_REG_NHM_CNT_11N 0x8d8
-+
-+/* @For struct acs_info, Jeffery, 2014-12-26 */
-+#define ODM_REG_NHM_CNT7_TO_CNT4_11N 0x8dc
-+#define ODM_REG_NHM_CNT9_TO_CNT8_11N 0x8d0
-+#define ODM_REG_NHM_CNT10_TO_CNT11_11N 0x8d4
-+
-+/* PAGE 9 */
-+#define ODM_REG_BB_CTRL_PAGE9_11N 0x900
-+#define ODM_REG_DBG_RPT_11N 0x908
-+#define ODM_REG_BB_TX_PATH_11N 0x90c
-+#define ODM_REG_ANT_MAPPING1_11N 0x914
-+#define ODM_REG_ANT_MAPPING2_11N 0x918
-+#define ODM_REG_EDCCA_DOWN_OPT_11N 0x948
-+#define ODM_REG_RX_DFIR_MOD_97F 0x948
-+#define ODM_REG_SOML_97F 0x998
-+
-+/* PAGE A */
-+#define ODM_REG_CCK_ANTDIV_PARA1_11N 0xA00
-+#define ODM_REG_CCK_ANT_SEL_11N 0xA04
-+#define ODM_REG_CCK_CCA_11N 0xA0A
-+#define ODM_REG_CCK_ANTDIV_PARA2_11N 0xA0C
-+#define ODM_REG_CCK_ANTDIV_PARA3_11N 0xA10
-+#define ODM_REG_CCK_ANTDIV_PARA4_11N 0xA14
-+#define ODM_REG_CCK_FILTER_PARA1_11N 0xA22
-+#define ODM_REG_CCK_FILTER_PARA2_11N 0xA23
-+#define ODM_REG_CCK_FILTER_PARA3_11N 0xA24
-+#define ODM_REG_CCK_FILTER_PARA4_11N 0xA25
-+#define ODM_REG_CCK_FILTER_PARA5_11N 0xA26
-+#define ODM_REG_CCK_FILTER_PARA6_11N 0xA27
-+#define ODM_REG_CCK_FILTER_PARA7_11N 0xA28
-+#define ODM_REG_CCK_FILTER_PARA8_11N 0xA29
-+#define ODM_REG_CCK_FA_RST_11N 0xA2C
-+#define ODM_REG_CCK_FA_MSB_11N 0xA58
-+#define ODM_REG_CCK_FA_LSB_11N 0xA5C
-+#define ODM_REG_CCK_CCA_CNT_11N 0xA60
-+#define ODM_REG_BB_PWR_SAV4_11N 0xA74
-+/* PAGE B */
-+#define ODM_REG_LNA_SWITCH_11N 0xB2C
-+#define ODM_REG_PATH_SWITCH_11N 0xB30
-+#define ODM_REG_RSSI_CTRL_11N 0xB38
-+#define ODM_REG_CONFIG_ANTA_11N 0xB68
-+#define ODM_REG_RSSI_BT_11N 0xB9C
-+#define ODM_REG_RXCK_RFMOD 0xBB0
-+#define ODM_REG_EDCCA_DCNF_97F 0xBC0
-+
-+/* PAGE C */
-+#define ODM_REG_OFDM_FA_HOLDC_11N 0xC00
-+#define ODM_REG_BB_RX_PATH_11N 0xC04
-+#define ODM_REG_TRMUX_11N 0xC08
-+#define ODM_REG_OFDM_FA_RSTC_11N 0xC0C
-+#define ODM_REG_DOWNSAM_FACTOR_11N 0xC10
-+#define ODM_REG_RXIQI_MATRIX_11N 0xC14
-+#define ODM_REG_TXIQK_MATRIX_LSB1_11N 0xC4C
-+#define ODM_REG_IGI_A_11N 0xC50
-+#define ODM_REG_ANTDIV_PARA2_11N 0xC54
-+#define ODM_REG_IGI_B_11N 0xC58
-+#define ODM_REG_ANTDIV_PARA3_11N 0xC5C
-+#define ODM_REG_L1SBD_PD_CH_11N 0XC6C
-+#define ODM_REG_BB_PWR_SAV2_11N 0xC70
-+#define ODM_REG_BB_AGC_SET_2_11N 0xc74
-+#define ODM_REG_RX_OFF_11N 0xC7C
-+#define ODM_REG_TXIQK_MATRIXA_11N 0xC80
-+#define ODM_REG_TXIQK_MATRIXB_11N 0xC88
-+#define ODM_REG_TXIQK_MATRIXA_LSB2_11N 0xC94
-+#define ODM_REG_TXIQK_MATRIXB_LSB2_11N 0xC9C
-+#define ODM_REG_RXIQK_MATRIX_LSB_11N 0xCA0
-+#define ODM_REG_ANTDIV_PARA1_11N 0xCA4
-+#define ODM_REG_SMALL_BANDWIDTH_11N 0xCE4
-+#define ODM_REG_OFDM_FA_TYPE1_11N 0xCF0
-+/* PAGE D */
-+#define ODM_REG_OFDM_FA_RSTD_11N 0xD00
-+#define ODM_REG_BB_RX_ANT_11N 0xD04
-+#define ODM_REG_BB_ATC_11N 0xD2C
-+#define ODM_REG_OFDM_FA_TYPE2_11N 0xDA0
-+#define ODM_REG_OFDM_FA_TYPE3_11N 0xDA4
-+#define ODM_REG_OFDM_FA_TYPE4_11N 0xDA8
-+#define ODM_REG_RPT_11N 0xDF4
-+/* PAGE E */
-+#define ODM_REG_TXAGC_A_6_18_11N 0xE00
-+#define ODM_REG_TXAGC_A_24_54_11N 0xE04
-+#define ODM_REG_TXAGC_A_1_MCS32_11N 0xE08
-+#define ODM_REG_TXAGC_A_MCS0_3_11N 0xE10
-+#define ODM_REG_TXAGC_A_MCS4_7_11N 0xE14
-+#define ODM_REG_TXAGC_A_MCS8_11_11N 0xE18
-+#define ODM_REG_TXAGC_A_MCS12_15_11N 0xE1C
-+#define ODM_REG_EDCCA_DCNF_11N 0xE24
-+#define ODM_REG_TAP_UPD_97F 0xE24
-+#define ODM_REG_FPGA0_IQK_11N 0xE28
-+#define ODM_REG_PAGE_B1_97F 0xE28
-+#define ODM_REG_TXIQK_TONE_A_11N 0xE30
-+#define ODM_REG_RXIQK_TONE_A_11N 0xE34
-+#define ODM_REG_TXIQK_PI_A_11N 0xE38
-+#define ODM_REG_RXIQK_PI_A_11N 0xE3C
-+#define ODM_REG_TXIQK_11N 0xE40
-+#define ODM_REG_RXIQK_11N 0xE44
-+#define ODM_REG_IQK_AGC_PTS_11N 0xE48
-+#define ODM_REG_IQK_AGC_RSP_11N 0xE4C
-+#define ODM_REG_BLUETOOTH_11N 0xE6C
-+#define ODM_REG_RX_WAIT_CCA_11N 0xE70
-+#define ODM_REG_TX_CCK_RFON_11N 0xE74
-+#define ODM_REG_TX_CCK_BBON_11N 0xE78
-+#define ODM_REG_OFDM_RFON_11N 0xE7C
-+#define ODM_REG_OFDM_BBON_11N 0xE80
-+#define ODM_REG_TX2RX_11N 0xE84
-+#define ODM_REG_TX2TX_11N 0xE88
-+#define ODM_REG_RX_CCK_11N 0xE8C
-+#define ODM_REG_RX_OFDM_11N 0xED0
-+#define ODM_REG_RX_WAIT_RIFS_11N 0xED4
-+#define ODM_REG_RX2RX_11N 0xED8
-+#define ODM_REG_STANDBY_11N 0xEDC
-+#define ODM_REG_SLEEP_11N 0xEE0
-+#define ODM_REG_PMPD_ANAEN_11N 0xEEC
-+/* PAGE F */
-+#define ODM_REG_PAGE_F_RST_11N 0xF14
-+#define ODM_REG_IGI_C_11N 0xF84
-+#define ODM_REG_IGI_D_11N 0xF88
-+#define ODM_REG_CCK_CRC32_ERROR_CNT_11N 0xF84
-+#define ODM_REG_CCK_CRC32_OK_CNT_11N 0xF88
-+#define ODM_REG_HT_CRC32_CNT_11N 0xF90
-+#define ODM_REG_OFDM_CRC32_CNT_11N 0xF94
-+#define ODM_REG_HT_CRC32_CNT_11N_AGG 0xFB8
-+
-+/* @2 MAC REG LIST */
-+#define ODM_REG_BB_RST_11N 0x02
-+#define ODM_REG_ANTSEL_PIN_11N 0x4C
-+#define ODM_REG_EARLY_MODE_11N 0x4D0
-+#define ODM_REG_RSSI_MONITOR_11N 0x4FE
-+#define ODM_REG_EDCA_VO_11N 0x500
-+#define ODM_REG_EDCA_VI_11N 0x504
-+#define ODM_REG_EDCA_BE_11N 0x508
-+#define ODM_REG_EDCA_BK_11N 0x50C
-+#define ODM_REG_TXPAUSE_11N 0x522
-+#define ODM_REG_RESP_TX_11N 0x6D8
-+#define ODM_REG_ANT_TRAIN_PARA1_11N 0x7b0
-+#define ODM_REG_ANT_TRAIN_PARA2_11N 0x7b4
-+
-+
-+/* @DIG Related */
-+#define ODM_BIT_IGI_11N 0x0000007F
-+#define ODM_BIT_CCK_RPT_FORMAT_11N BIT(9)
-+#define ODM_BIT_BB_RX_PATH_11N 0xF
-+#define ODM_BIT_BB_TX_PATH_11N 0xF
-+#define ODM_BIT_BB_ATC_11N BIT(11)
-+#endif
-+
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_regtable.h linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_regtable.h
-new file mode 100644
-index 000000000..cf2226c3b
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_regtable.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/phydm_regtable.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/phydm_regtable.h
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/phydm_regtable.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/phydm_regtable.h 2021-03-07 18:16:17.065956573 +0200
@@ -0,0 +1,849 @@
+#define R_0x0 0x0
+#define R_0x00 0x00
@@ -256475,11 +253291,9 @@ index 000000000..cf2226c3b
+#define RF_0xee 0xee
+#define RF_0xef 0xef
+#define RF_0xf5 0xf5
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_rssi_monitor.c linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_rssi_monitor.c
-new file mode 100644
-index 000000000..0d5e41766
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_rssi_monitor.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/phydm_rssi_monitor.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/phydm_rssi_monitor.c
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/phydm_rssi_monitor.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/phydm_rssi_monitor.c 2021-03-07 18:16:17.065956573 +0200
@@ -0,0 +1,170 @@
+/******************************************************************************
+ *
@@ -256651,11 +253465,9 @@ index 000000000..0d5e41766
+}
+
+#endif
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_rssi_monitor.h linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_rssi_monitor.h
-new file mode 100644
-index 000000000..ac997e326
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_rssi_monitor.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/phydm_rssi_monitor.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/phydm_rssi_monitor.h
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/phydm_rssi_monitor.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/phydm_rssi_monitor.h 2021-03-07 18:16:17.065956573 +0200
@@ -0,0 +1,55 @@
+/******************************************************************************
+ *
@@ -256712,11 +253524,9 @@ index 000000000..ac997e326
+void phydm_rssi_monitor_init(void *dm_void);
+
+#endif
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_smt_ant.c linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_smt_ant.c
-new file mode 100644
-index 000000000..8e805b3ce
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_smt_ant.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/phydm_smt_ant.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/phydm_smt_ant.c
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/phydm_smt_ant.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/phydm_smt_ant.c 2021-03-07 18:16:17.065956573 +0200
@@ -0,0 +1,2277 @@
+/******************************************************************************
+ *
@@ -258995,11 +255805,9 @@ index 000000000..8e805b3ce
+ }
+}
+#endif
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_smt_ant.h linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_smt_ant.h
-new file mode 100644
-index 000000000..3a408c4c6
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_smt_ant.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/phydm_smt_ant.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/phydm_smt_ant.h
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/phydm_smt_ant.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/phydm_smt_ant.h 2021-03-07 18:16:17.065956573 +0200
@@ -0,0 +1,210 @@
+/******************************************************************************
+ *
@@ -259211,12 +256019,10 @@ index 000000000..3a408c4c6
+void phydm_smt_ant_init(void *dm_void);
+#endif /*@#if (defined(CONFIG_SMART_ANTENNA))*/
+#endif
-\ No newline at end of file
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_soml.c linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_soml.c
-new file mode 100644
-index 000000000..35507e3f4
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_soml.c
+\ Ingen nyrad vid filslut
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/phydm_soml.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/phydm_soml.c
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/phydm_soml.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/phydm_soml.c 2021-03-07 18:16:17.065956573 +0200
@@ -0,0 +1,1111 @@
+/******************************************************************************
+ *
@@ -260329,11 +257135,9 @@ index 000000000..35507e3f4
+ }
+#endif
+}
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_soml.h linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_soml.h
-new file mode 100644
-index 000000000..2d5fbc31a
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_soml.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/phydm_soml.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/phydm_soml.h
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/phydm_soml.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/phydm_soml.h 2021-03-07 18:16:17.065956573 +0200
@@ -0,0 +1,185 @@
+/******************************************************************************
+ *
@@ -260520,11 +257324,9 @@ index 000000000..2d5fbc31a
+#endif
+void phydm_init_soft_ml_setting(void *dm_void);
+#endif /*@#ifndef __PHYDMSOML_H__*/
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_types.h linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_types.h
-new file mode 100644
-index 000000000..a13f506b0
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/phydm_types.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/phydm_types.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/phydm_types.h
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/phydm_types.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/phydm_types.h 2021-03-07 18:16:17.065956573 +0200
@@ -0,0 +1,330 @@
+/******************************************************************************
+ *
@@ -260856,11 +257658,9 @@ index 000000000..a13f506b0
+#define MASKL3BYTES 0x00ffffff
+
+#endif /* __ODM_TYPES_H__ */
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/rtl8812a/halhwimg8812a_bb.c linux-5.8/3rdparty/rtl8812au/hal/phydm/rtl8812a/halhwimg8812a_bb.c
-new file mode 100644
-index 000000000..0d2cb51c0
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/rtl8812a/halhwimg8812a_bb.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/rtl8812a/halhwimg8812a_bb.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/rtl8812a/halhwimg8812a_bb.c
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/rtl8812a/halhwimg8812a_bb.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/rtl8812a/halhwimg8812a_bb.c 2021-03-07 18:16:17.066956620 +0200
@@ -0,0 +1,1469 @@
+/******************************************************************************
+ *
@@ -262331,11 +259131,9 @@ index 000000000..0d2cb51c0
+
+#endif /* end of HWIMG_SUPPORT*/
+
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/rtl8812a/halhwimg8812a_bb.h linux-5.8/3rdparty/rtl8812au/hal/phydm/rtl8812a/halhwimg8812a_bb.h
-new file mode 100644
-index 000000000..aca9f019f
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/rtl8812a/halhwimg8812a_bb.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/rtl8812a/halhwimg8812a_bb.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/rtl8812a/halhwimg8812a_bb.h
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/rtl8812a/halhwimg8812a_bb.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/rtl8812a/halhwimg8812a_bb.h 2021-03-07 18:16:17.066956620 +0200
@@ -0,0 +1,107 @@
+/******************************************************************************
+ *
@@ -262444,11 +259242,9 @@ index 000000000..aca9f019f
+#endif
+#endif /* end of HWIMG_SUPPORT*/
+
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/rtl8812a/halhwimg8812a_mac.c linux-5.8/3rdparty/rtl8812au/hal/phydm/rtl8812a/halhwimg8812a_mac.c
-new file mode 100644
-index 000000000..febfa8010
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/rtl8812a/halhwimg8812a_mac.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/rtl8812a/halhwimg8812a_mac.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/rtl8812a/halhwimg8812a_mac.c
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/rtl8812a/halhwimg8812a_mac.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/rtl8812a/halhwimg8812a_mac.c 2021-03-07 18:16:17.066956620 +0200
@@ -0,0 +1,301 @@
+/******************************************************************************
+ *
@@ -262751,11 +259547,9 @@ index 000000000..febfa8010
+
+#endif /* end of HWIMG_SUPPORT*/
+
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/rtl8812a/halhwimg8812a_mac.h linux-5.8/3rdparty/rtl8812au/hal/phydm/rtl8812a/halhwimg8812a_mac.h
-new file mode 100644
-index 000000000..2fe4f20e9
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/rtl8812a/halhwimg8812a_mac.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/rtl8812a/halhwimg8812a_mac.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/rtl8812a/halhwimg8812a_mac.h
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/rtl8812a/halhwimg8812a_mac.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/rtl8812a/halhwimg8812a_mac.h 2021-03-07 18:16:17.066956620 +0200
@@ -0,0 +1,33 @@
+/******************************************************************************
+ *
@@ -262790,11 +259584,9 @@ index 000000000..2fe4f20e9
+#endif
+#endif /* end of HWIMG_SUPPORT*/
+
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/rtl8812a/halhwimg8812a_rf.c linux-5.8/3rdparty/rtl8812au/hal/phydm/rtl8812a/halhwimg8812a_rf.c
-new file mode 100644
-index 000000000..02f64522d
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/rtl8812a/halhwimg8812a_rf.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/rtl8812a/halhwimg8812a_rf.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/rtl8812a/halhwimg8812a_rf.c
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/rtl8812a/halhwimg8812a_rf.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/rtl8812a/halhwimg8812a_rf.c 2021-03-07 18:16:17.066956620 +0200
@@ -0,0 +1,3848 @@
+/******************************************************************************
+ *
@@ -266644,11 +263436,9 @@ index 000000000..02f64522d
+
+#endif /* end of HWIMG_SUPPORT*/
+
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/rtl8812a/halhwimg8812a_rf.h linux-5.8/3rdparty/rtl8812au/hal/phydm/rtl8812a/halhwimg8812a_rf.h
-new file mode 100644
-index 000000000..20ba73357
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/rtl8812a/halhwimg8812a_rf.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/rtl8812a/halhwimg8812a_rf.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/rtl8812a/halhwimg8812a_rf.h
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/rtl8812a/halhwimg8812a_rf.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/rtl8812a/halhwimg8812a_rf.h 2021-03-07 18:16:17.066956620 +0200
@@ -0,0 +1,124 @@
+/******************************************************************************
+ *
@@ -266774,11 +263564,9 @@ index 000000000..20ba73357
+#endif
+#endif /* end of HWIMG_SUPPORT*/
+
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/rtl8812a/phydm_regconfig8812a.c linux-5.8/3rdparty/rtl8812au/hal/phydm/rtl8812a/phydm_regconfig8812a.c
-new file mode 100644
-index 000000000..83362e539
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/rtl8812a/phydm_regconfig8812a.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/rtl8812a/phydm_regconfig8812a.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/rtl8812a/phydm_regconfig8812a.c
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/rtl8812a/phydm_regconfig8812a.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/rtl8812a/phydm_regconfig8812a.c 2021-03-07 18:16:17.066956620 +0200
@@ -0,0 +1,149 @@
+/******************************************************************************
+ *
@@ -266929,11 +263717,9 @@ index 000000000..83362e539
+ enum rf_path RF_PATH, u32 reg_addr) {}
+
+#endif /* #if (RTL8812A_SUPPORT == 1) */
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/rtl8812a/phydm_regconfig8812a.h linux-5.8/3rdparty/rtl8812au/hal/phydm/rtl8812a/phydm_regconfig8812a.h
-new file mode 100644
-index 000000000..60a24ca29
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/rtl8812a/phydm_regconfig8812a.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/rtl8812a/phydm_regconfig8812a.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/rtl8812a/phydm_regconfig8812a.h
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/rtl8812a/phydm_regconfig8812a.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/rtl8812a/phydm_regconfig8812a.h 2021-03-07 18:16:17.066956620 +0200
@@ -0,0 +1,44 @@
+/******************************************************************************
+ *
@@ -266979,11 +263765,9 @@ index 000000000..60a24ca29
+
+#endif
+#endif /* end of SUPPORT */
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/rtl8812a/phydm_rtl8812a.c linux-5.8/3rdparty/rtl8812au/hal/phydm/rtl8812a/phydm_rtl8812a.c
-new file mode 100644
-index 000000000..192d776bb
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/rtl8812a/phydm_rtl8812a.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/rtl8812a/phydm_rtl8812a.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/rtl8812a/phydm_rtl8812a.c
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/rtl8812a/phydm_rtl8812a.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/rtl8812a/phydm_rtl8812a.c 2021-03-07 18:16:17.066956620 +0200
@@ -0,0 +1,113 @@
+/******************************************************************************
+ *
@@ -267098,11 +263882,9 @@ index 000000000..192d776bb
+}
+
+#endif /* #if (RTL8812A_SUPPORT == 1) */
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/rtl8812a/phydm_rtl8812a.h linux-5.8/3rdparty/rtl8812au/hal/phydm/rtl8812a/phydm_rtl8812a.h
-new file mode 100644
-index 000000000..1738351ef
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/rtl8812a/phydm_rtl8812a.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/rtl8812a/phydm_rtl8812a.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/rtl8812a/phydm_rtl8812a.h
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/rtl8812a/phydm_rtl8812a.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/rtl8812a/phydm_rtl8812a.h 2021-03-07 18:16:17.066956620 +0200
@@ -0,0 +1,27 @@
+/******************************************************************************
+ *
@@ -267131,11 +263913,9 @@ index 000000000..1738351ef
+void phydm_hwsetting_8812a(struct dm_struct *dm);
+
+#endif
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/rtl8812a/version_rtl8812a.h linux-5.8/3rdparty/rtl8812au/hal/phydm/rtl8812a/version_rtl8812a.h
-new file mode 100644
-index 000000000..c9a50ab32
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/rtl8812a/version_rtl8812a.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/rtl8812a/version_rtl8812a.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/rtl8812a/version_rtl8812a.h
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/rtl8812a/version_rtl8812a.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/rtl8812a/version_rtl8812a.h 2021-03-07 18:16:17.066956620 +0200
@@ -0,0 +1,24 @@
+/******************************************************************************
+ *
@@ -267161,11 +263941,9 @@ index 000000000..c9a50ab32
+#define RELEASE_DATE_8812A 20150920
+#define COMMIT_BY_8812A "BB_LUKE"
+#define RELEASE_VERSION_8812A 57
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/rtl8814a/hal8814areg_odm.h linux-5.8/3rdparty/rtl8812au/hal/phydm/rtl8814a/hal8814areg_odm.h
-new file mode 100644
-index 000000000..1cd40304a
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/rtl8814a/hal8814areg_odm.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/rtl8814a/hal8814areg_odm.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/rtl8814a/hal8814areg_odm.h
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/rtl8814a/hal8814areg_odm.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/rtl8814a/hal8814areg_odm.h 2021-03-07 18:16:17.066956620 +0200
@@ -0,0 +1,47 @@
+/******************************************************************************
+ *
@@ -267214,11 +263992,9 @@ index 000000000..1cd40304a
+
+#endif
+
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/rtl8814a/halhwimg8814a_bb.c linux-5.8/3rdparty/rtl8812au/hal/phydm/rtl8814a/halhwimg8814a_bb.c
-new file mode 100644
-index 000000000..181b88a85
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/rtl8814a/halhwimg8814a_bb.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/rtl8814a/halhwimg8814a_bb.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/rtl8814a/halhwimg8814a_bb.c
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/rtl8814a/halhwimg8814a_bb.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/rtl8814a/halhwimg8814a_bb.c 2021-03-07 18:16:17.067956667 +0200
@@ -0,0 +1,4308 @@
+/******************************************************************************
+ *
@@ -271528,11 +268304,9 @@ index 000000000..181b88a85
+
+#endif /* end of HWIMG_SUPPORT*/
+
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/rtl8814a/halhwimg8814a_bb.h linux-5.8/3rdparty/rtl8812au/hal/phydm/rtl8814a/halhwimg8814a_bb.h
-new file mode 100644
-index 000000000..949b6f978
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/rtl8814a/halhwimg8814a_bb.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/rtl8814a/halhwimg8814a_bb.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/rtl8814a/halhwimg8814a_bb.h
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/rtl8814a/halhwimg8814a_bb.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/rtl8814a/halhwimg8814a_bb.h 2021-03-07 18:16:17.067956667 +0200
@@ -0,0 +1,99 @@
+/******************************************************************************
+*
@@ -271633,11 +268407,9 @@ index 000000000..949b6f978
+#endif
+#endif /* end of HWIMG_SUPPORT*/
+
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/rtl8814a/halhwimg8814a_fw.h linux-5.8/3rdparty/rtl8812au/hal/phydm/rtl8814a/halhwimg8814a_fw.h
-new file mode 100644
-index 000000000..3f8de123d
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/rtl8814a/halhwimg8814a_fw.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/rtl8814a/halhwimg8814a_fw.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/rtl8814a/halhwimg8814a_fw.h
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/rtl8814a/halhwimg8814a_fw.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/rtl8814a/halhwimg8814a_fw.h 2021-03-07 18:16:17.067956667 +0200
@@ -0,0 +1,56 @@
+/******************************************************************************
+*
@@ -271695,11 +268467,9 @@ index 000000000..3f8de123d
+#endif
+#endif // end of HWIMG_SUPPORT
+
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/rtl8814a/halhwimg8814a_mac.c linux-5.8/3rdparty/rtl8812au/hal/phydm/rtl8814a/halhwimg8814a_mac.c
-new file mode 100644
-index 000000000..0d5867028
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/rtl8814a/halhwimg8814a_mac.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/rtl8814a/halhwimg8814a_mac.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/rtl8814a/halhwimg8814a_mac.c
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/rtl8814a/halhwimg8814a_mac.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/rtl8814a/halhwimg8814a_mac.c 2021-03-07 18:16:17.067956667 +0200
@@ -0,0 +1,325 @@
+/******************************************************************************
+ *
@@ -272026,11 +268796,9 @@ index 000000000..0d5867028
+
+#endif /* end of HWIMG_SUPPORT*/
+
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/rtl8814a/halhwimg8814a_mac.h linux-5.8/3rdparty/rtl8812au/hal/phydm/rtl8814a/halhwimg8814a_mac.h
-new file mode 100644
-index 000000000..94f6a2daf
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/rtl8814a/halhwimg8814a_mac.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/rtl8814a/halhwimg8814a_mac.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/rtl8814a/halhwimg8814a_mac.h
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/rtl8814a/halhwimg8814a_mac.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/rtl8814a/halhwimg8814a_mac.h 2021-03-07 18:16:17.067956667 +0200
@@ -0,0 +1,39 @@
+/******************************************************************************
+*
@@ -272071,11 +268839,9 @@ index 000000000..94f6a2daf
+#endif
+#endif /* end of HWIMG_SUPPORT*/
+
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/rtl8814a/halhwimg8814a_rf.c linux-5.8/3rdparty/rtl8812au/hal/phydm/rtl8814a/halhwimg8814a_rf.c
-new file mode 100644
-index 000000000..c7225cd93
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/rtl8814a/halhwimg8814a_rf.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/rtl8814a/halhwimg8814a_rf.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/rtl8814a/halhwimg8814a_rf.c
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/rtl8814a/halhwimg8814a_rf.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/rtl8814a/halhwimg8814a_rf.c 2021-03-07 18:16:17.067956667 +0200
@@ -0,0 +1,8838 @@
+/******************************************************************************
+ *
@@ -280915,11 +277681,9 @@ index 000000000..c7225cd93
+
+#endif /* end of HWIMG_SUPPORT*/
+
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/rtl8814a/halhwimg8814a_rf.h linux-5.8/3rdparty/rtl8812au/hal/phydm/rtl8814a/halhwimg8814a_rf.h
-new file mode 100644
-index 000000000..27707510e
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/rtl8814a/halhwimg8814a_rf.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/rtl8814a/halhwimg8814a_rf.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/rtl8814a/halhwimg8814a_rf.h
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/rtl8814a/halhwimg8814a_rf.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/rtl8814a/halhwimg8814a_rf.h 2021-03-07 18:16:17.067956667 +0200
@@ -0,0 +1,149 @@
+/******************************************************************************
+*
@@ -281070,11 +277834,9 @@ index 000000000..27707510e
+#endif
+#endif /* end of HWIMG_SUPPORT*/
+
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/rtl8814a/halphyrf_8814a_ap.c linux-5.8/3rdparty/rtl8812au/hal/phydm/rtl8814a/halphyrf_8814a_ap.c
-new file mode 100644
-index 000000000..948f91963
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/rtl8814a/halphyrf_8814a_ap.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/rtl8814a/halphyrf_8814a_ap.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/rtl8814a/halphyrf_8814a_ap.c
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/rtl8814a/halphyrf_8814a_ap.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/rtl8814a/halphyrf_8814a_ap.c 2021-03-07 18:16:17.068956715 +0200
@@ -0,0 +1,1754 @@
+/******************************************************************************
+ *
@@ -282830,11 +279592,9 @@ index 000000000..948f91963
+#endif
+
+
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/rtl8814a/halphyrf_8814a_ap.h linux-5.8/3rdparty/rtl8812au/hal/phydm/rtl8814a/halphyrf_8814a_ap.h
-new file mode 100644
-index 000000000..cbb1ced95
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/rtl8814a/halphyrf_8814a_ap.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/rtl8814a/halphyrf_8814a_ap.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/rtl8814a/halphyrf_8814a_ap.h
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/rtl8814a/halphyrf_8814a_ap.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/rtl8814a/halphyrf_8814a_ap.h 2021-03-07 18:16:17.068956715 +0200
@@ -0,0 +1,164 @@
+/******************************************************************************
+ *
@@ -283000,11 +279760,9 @@ index 000000000..cbb1ced95
+
+#endif // #ifndef __HAL_PHY_RF_8814A_H__
+
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/rtl8814a/halphyrf_8814a_win.c linux-5.8/3rdparty/rtl8812au/hal/phydm/rtl8814a/halphyrf_8814a_win.c
-new file mode 100644
-index 000000000..eb91c4d8a
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/rtl8814a/halphyrf_8814a_win.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/rtl8814a/halphyrf_8814a_win.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/rtl8814a/halphyrf_8814a_win.c
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/rtl8814a/halphyrf_8814a_win.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/rtl8814a/halphyrf_8814a_win.c 2021-03-07 18:16:17.068956715 +0200
@@ -0,0 +1,528 @@
+/******************************************************************************
+ *
@@ -283534,11 +280292,9 @@ index 000000000..eb91c4d8a
+ IN BOOLEAN bReCovery
+ ){}
+#endif /* (RTL8814A_SUPPORT == 0)*/
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/rtl8814a/halphyrf_8814a_win.h linux-5.8/3rdparty/rtl8812au/hal/phydm/rtl8814a/halphyrf_8814a_win.h
-new file mode 100644
-index 000000000..658d6f063
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/rtl8814a/halphyrf_8814a_win.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/rtl8814a/halphyrf_8814a_win.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/rtl8814a/halphyrf_8814a_win.h
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/rtl8814a/halphyrf_8814a_win.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/rtl8814a/halphyrf_8814a_win.h 2021-03-07 18:16:17.068956715 +0200
@@ -0,0 +1,106 @@
+/******************************************************************************
+ *
@@ -283646,11 +280402,9 @@ index 000000000..658d6f063
+
+#endif // #ifndef __HAL_PHY_RF_8188E_H__
+
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/rtl8814a/phydm_regconfig8814a.c linux-5.8/3rdparty/rtl8812au/hal/phydm/rtl8814a/phydm_regconfig8814a.c
-new file mode 100644
-index 000000000..2e3f20622
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/rtl8814a/phydm_regconfig8814a.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/rtl8814a/phydm_regconfig8814a.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/rtl8814a/phydm_regconfig8814a.c
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/rtl8814a/phydm_regconfig8814a.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/rtl8814a/phydm_regconfig8814a.c 2021-03-07 18:16:17.068956715 +0200
@@ -0,0 +1,219 @@
+/******************************************************************************
+ *
@@ -283871,11 +280625,9 @@ index 000000000..2e3f20622
+}
+#endif
+
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/rtl8814a/phydm_regconfig8814a.h linux-5.8/3rdparty/rtl8812au/hal/phydm/rtl8814a/phydm_regconfig8814a.h
-new file mode 100644
-index 000000000..bc3f9434e
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/rtl8814a/phydm_regconfig8814a.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/rtl8814a/phydm_regconfig8814a.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/rtl8814a/phydm_regconfig8814a.h
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/rtl8814a/phydm_regconfig8814a.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/rtl8814a/phydm_regconfig8814a.h 2021-03-07 18:16:17.068956715 +0200
@@ -0,0 +1,109 @@
+/******************************************************************************
+ *
@@ -283986,11 +280738,9 @@ index 000000000..bc3f9434e
+#endif
+#endif // end of SUPPORT
+
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/rtl8814a/phydm_rtl8814a.c linux-5.8/3rdparty/rtl8812au/hal/phydm/rtl8814a/phydm_rtl8814a.c
-new file mode 100644
-index 000000000..885e06336
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/rtl8814a/phydm_rtl8814a.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/rtl8814a/phydm_rtl8814a.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/rtl8814a/phydm_rtl8814a.c
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/rtl8814a/phydm_rtl8814a.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/rtl8814a/phydm_rtl8814a.c 2021-03-07 18:16:17.068956715 +0200
@@ -0,0 +1,503 @@
+/******************************************************************************
+ *
@@ -284495,11 +281245,9 @@ index 000000000..885e06336
+
+
+
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/rtl8814a/phydm_rtl8814a.h linux-5.8/3rdparty/rtl8812au/hal/phydm/rtl8814a/phydm_rtl8814a.h
-new file mode 100644
-index 000000000..a7ff6757d
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/rtl8814a/phydm_rtl8814a.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/rtl8814a/phydm_rtl8814a.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/rtl8814a/phydm_rtl8814a.h
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/rtl8814a/phydm_rtl8814a.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/rtl8814a/phydm_rtl8814a.h 2021-03-07 18:16:17.068956715 +0200
@@ -0,0 +1,78 @@
+/******************************************************************************
+ *
@@ -284579,11 +281327,9 @@ index 000000000..a7ff6757d
+ );
+
+#endif
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/rtl8814a/version_rtl8814a.h linux-5.8/3rdparty/rtl8812au/hal/phydm/rtl8814a/version_rtl8814a.h
-new file mode 100644
-index 000000000..e9c28bfb7
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/rtl8814a/version_rtl8814a.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/rtl8814a/version_rtl8814a.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/rtl8814a/version_rtl8814a.h
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/rtl8814a/version_rtl8814a.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/rtl8814a/version_rtl8814a.h 2021-03-07 18:16:17.068956715 +0200
@@ -0,0 +1,10 @@
+/*RTL8814A PHY Parameters*/
+/*
@@ -284595,11 +281341,9 @@ index 000000000..e9c28bfb7
+#define RELEASE_DATE_8814A 20150908
+#define COMMIT_BY_8814A "BB_LUKE"
+#define RELEASE_VERSION_8814A 81
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/rtl8821a/halhwimg8821a_bb.c linux-5.8/3rdparty/rtl8812au/hal/phydm/rtl8821a/halhwimg8821a_bb.c
-new file mode 100644
-index 000000000..0dc7ab6e1
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/rtl8821a/halhwimg8821a_bb.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/rtl8821a/halhwimg8821a_bb.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/rtl8821a/halhwimg8821a_bb.c
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/rtl8821a/halhwimg8821a_bb.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/rtl8821a/halhwimg8821a_bb.c 2021-03-07 18:16:17.068956715 +0200
@@ -0,0 +1,923 @@
+/******************************************************************************
+ *
@@ -285524,11 +282268,9 @@ index 000000000..0dc7ab6e1
+
+
+#endif /* end of HWIMG_SUPPORT*/
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/rtl8821a/halhwimg8821a_bb.h linux-5.8/3rdparty/rtl8812au/hal/phydm/rtl8821a/halhwimg8821a_bb.h
-new file mode 100644
-index 000000000..791b7d19d
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/rtl8821a/halhwimg8821a_bb.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/rtl8821a/halhwimg8821a_bb.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/rtl8821a/halhwimg8821a_bb.h
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/rtl8821a/halhwimg8821a_bb.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/rtl8821a/halhwimg8821a_bb.h 2021-03-07 18:16:17.068956715 +0200
@@ -0,0 +1,83 @@
+/******************************************************************************
+ *
@@ -285613,11 +282355,9 @@ index 000000000..791b7d19d
+
+#endif
+#endif /* end of HWIMG_SUPPORT*/
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/rtl8821a/halhwimg8821a_mac.c linux-5.8/3rdparty/rtl8812au/hal/phydm/rtl8821a/halhwimg8821a_mac.c
-new file mode 100644
-index 000000000..b93be49b6
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/rtl8821a/halhwimg8821a_mac.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/rtl8821a/halhwimg8821a_mac.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/rtl8821a/halhwimg8821a_mac.c
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/rtl8821a/halhwimg8821a_mac.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/rtl8821a/halhwimg8821a_mac.c 2021-03-07 18:16:17.068956715 +0200
@@ -0,0 +1,279 @@
+/******************************************************************************
+ *
@@ -285898,11 +282638,9 @@ index 000000000..b93be49b6
+}
+
+#endif /* end of HWIMG_SUPPORT*/
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/rtl8821a/halhwimg8821a_mac.h linux-5.8/3rdparty/rtl8812au/hal/phydm/rtl8821a/halhwimg8821a_mac.h
-new file mode 100644
-index 000000000..35665a4d1
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/rtl8821a/halhwimg8821a_mac.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/rtl8821a/halhwimg8821a_mac.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/rtl8821a/halhwimg8821a_mac.h
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/rtl8821a/halhwimg8821a_mac.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/rtl8821a/halhwimg8821a_mac.h 2021-03-07 18:16:17.068956715 +0200
@@ -0,0 +1,33 @@
+/******************************************************************************
+ *
@@ -285937,11 +282675,9 @@ index 000000000..35665a4d1
+
+#endif
+#endif /* end of HWIMG_SUPPORT*/
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/rtl8821a/halhwimg8821a_rf.c linux-5.8/3rdparty/rtl8812au/hal/phydm/rtl8821a/halhwimg8821a_rf.c
-new file mode 100644
-index 000000000..05b004bd4
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/rtl8821a/halhwimg8821a_rf.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/rtl8821a/halhwimg8821a_rf.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/rtl8821a/halhwimg8821a_rf.c
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/rtl8821a/halhwimg8821a_rf.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/rtl8821a/halhwimg8821a_rf.c 2021-03-07 18:16:17.069956761 +0200
@@ -0,0 +1,5457 @@
+/******************************************************************************
+ *
@@ -291400,11 +288136,9 @@ index 000000000..05b004bd4
+}
+
+#endif /* end of HWIMG_SUPPORT*/
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/rtl8821a/halhwimg8821a_rf.h linux-5.8/3rdparty/rtl8812au/hal/phydm/rtl8821a/halhwimg8821a_rf.h
-new file mode 100644
-index 000000000..e630f7cb5
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/rtl8821a/halhwimg8821a_rf.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/rtl8821a/halhwimg8821a_rf.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/rtl8821a/halhwimg8821a_rf.h
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/rtl8821a/halhwimg8821a_rf.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/rtl8821a/halhwimg8821a_rf.h 2021-03-07 18:16:17.069956761 +0200
@@ -0,0 +1,143 @@
+/******************************************************************************
+ *
@@ -291549,11 +288283,9 @@ index 000000000..e630f7cb5
+
+#endif
+#endif /* end of HWIMG_SUPPORT*/
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/rtl8821a/phydm_regconfig8821a.c linux-5.8/3rdparty/rtl8812au/hal/phydm/rtl8821a/phydm_regconfig8821a.c
-new file mode 100644
-index 000000000..aa96ac7fc
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/rtl8821a/phydm_regconfig8821a.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/rtl8821a/phydm_regconfig8821a.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/rtl8821a/phydm_regconfig8821a.c
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/rtl8821a/phydm_regconfig8821a.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/rtl8821a/phydm_regconfig8821a.c 2021-03-07 18:16:17.069956761 +0200
@@ -0,0 +1,206 @@
+/******************************************************************************
+ *
@@ -291761,11 +288493,9 @@ index 000000000..aa96ac7fc
+}
+
+#endif /* #if (RTL8821A_SUPPORT == 1)*/
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/rtl8821a/phydm_regconfig8821a.h linux-5.8/3rdparty/rtl8812au/hal/phydm/rtl8821a/phydm_regconfig8821a.h
-new file mode 100644
-index 000000000..cf5eeeb19
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/rtl8821a/phydm_regconfig8821a.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/rtl8821a/phydm_regconfig8821a.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/rtl8821a/phydm_regconfig8821a.h
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/rtl8821a/phydm_regconfig8821a.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/rtl8821a/phydm_regconfig8821a.h 2021-03-07 18:16:17.069956761 +0200
@@ -0,0 +1,90 @@
+/******************************************************************************
+ *
@@ -291857,11 +288587,9 @@ index 000000000..cf5eeeb19
+
+#endif
+#endif /* end of SUPPORT */
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/rtl8821a/phydm_rtl8821a.c linux-5.8/3rdparty/rtl8812au/hal/phydm/rtl8821a/phydm_rtl8821a.c
-new file mode 100644
-index 000000000..5de0754da
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/rtl8821a/phydm_rtl8821a.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/rtl8821a/phydm_rtl8821a.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/rtl8821a/phydm_rtl8821a.c
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/rtl8821a/phydm_rtl8821a.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/rtl8821a/phydm_rtl8821a.c 2021-03-07 18:16:17.069956761 +0200
@@ -0,0 +1,129 @@
+/******************************************************************************
+ *
@@ -291992,11 +288720,9 @@ index 000000000..5de0754da
+}
+
+#endif /* #if (RTL8821A_SUPPORT == 1) */
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/rtl8821a/phydm_rtl8821a.h linux-5.8/3rdparty/rtl8812au/hal/phydm/rtl8821a/phydm_rtl8821a.h
-new file mode 100644
-index 000000000..2886fdc56
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/rtl8821a/phydm_rtl8821a.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/rtl8821a/phydm_rtl8821a.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/rtl8821a/phydm_rtl8821a.h
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/rtl8821a/phydm_rtl8821a.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/rtl8821a/phydm_rtl8821a.h 2021-03-07 18:16:17.069956761 +0200
@@ -0,0 +1,31 @@
+/******************************************************************************
+ *
@@ -292029,11 +288755,9 @@ index 000000000..2886fdc56
+);
+
+#endif
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/rtl8821a/version_rtl8821a.h linux-5.8/3rdparty/rtl8812au/hal/phydm/rtl8821a/version_rtl8821a.h
-new file mode 100644
-index 000000000..63b4ec971
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/rtl8821a/version_rtl8821a.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/rtl8821a/version_rtl8821a.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/rtl8821a/version_rtl8821a.h
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/rtl8821a/version_rtl8821a.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/rtl8821a/version_rtl8821a.h 2021-03-07 18:16:17.069956761 +0200
@@ -0,0 +1,24 @@
+/******************************************************************************
+ *
@@ -292059,11 +288783,9 @@ index 000000000..63b4ec971
+#define RELEASE_DATE_8821A 20150920
+#define COMMIT_BY_8821A "BB_LUKE"
+#define RELEASE_VERSION_8821A 59
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/sd4_phydm_2_kernel.mk linux-5.8/3rdparty/rtl8812au/hal/phydm/sd4_phydm_2_kernel.mk
-new file mode 100644
-index 000000000..f11c6ac90
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/sd4_phydm_2_kernel.mk
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/sd4_phydm_2_kernel.mk linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/sd4_phydm_2_kernel.mk
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/sd4_phydm_2_kernel.mk 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/sd4_phydm_2_kernel.mk 2021-03-07 18:16:17.069956761 +0200
@@ -0,0 +1,188 @@
+EXTRA_CFLAGS += -I$(src)/hal/phydm
+
@@ -292253,11 +288975,9 @@ index 000000000..f11c6ac90
+ hal/phydm/$(RTL871X)/phydm_hal_api8198f.o\
+ hal/phydm/$(RTL871X)/phydm_regconfig8198f.o
+endif
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/txbf/halcomtxbf.c linux-5.8/3rdparty/rtl8812au/hal/phydm/txbf/halcomtxbf.c
-new file mode 100644
-index 000000000..ae45a5b1a
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/txbf/halcomtxbf.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/txbf/halcomtxbf.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/txbf/halcomtxbf.c
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/txbf/halcomtxbf.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/txbf/halcomtxbf.c 2021-03-07 18:16:17.069956761 +0200
@@ -0,0 +1,520 @@
+/******************************************************************************
+ *
@@ -292779,11 +289499,9 @@ index 000000000..ae45a5b1a
+#endif
+
+#endif
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/txbf/halcomtxbf.h linux-5.8/3rdparty/rtl8812au/hal/phydm/txbf/halcomtxbf.h
-new file mode 100644
-index 000000000..5ad303394
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/txbf/halcomtxbf.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/txbf/halcomtxbf.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/txbf/halcomtxbf.h
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/txbf/halcomtxbf.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/txbf/halcomtxbf.h 2021-03-07 18:16:17.069956761 +0200
@@ -0,0 +1,183 @@
+/******************************************************************************
+ *
@@ -292968,11 +289686,9 @@ index 000000000..5ad303394
+#endif
+
+#endif /* @#ifndef __HAL_COM_TXBF_H__ */
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/txbf/haltxbf8192e.c linux-5.8/3rdparty/rtl8812au/hal/phydm/txbf/haltxbf8192e.c
-new file mode 100644
-index 000000000..daac3e58a
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/txbf/haltxbf8192e.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/txbf/haltxbf8192e.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/txbf/haltxbf8192e.c
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/txbf/haltxbf8192e.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/txbf/haltxbf8192e.c 2021-03-07 18:16:17.069956761 +0200
@@ -0,0 +1,384 @@
+/******************************************************************************
+ *
@@ -293358,11 +290074,9 @@ index 000000000..daac3e58a
+#endif /* @#if (RTL8192E_SUPPORT == 1)*/
+
+#endif
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/txbf/haltxbf8192e.h linux-5.8/3rdparty/rtl8812au/hal/phydm/txbf/haltxbf8192e.h
-new file mode 100644
-index 000000000..9b0c8321f
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/txbf/haltxbf8192e.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/txbf/haltxbf8192e.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/txbf/haltxbf8192e.h
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/txbf/haltxbf8192e.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/txbf/haltxbf8192e.h 2021-03-07 18:16:17.069956761 +0200
@@ -0,0 +1,71 @@
+/******************************************************************************
+ *
@@ -293435,11 +290149,9 @@ index 000000000..9b0c8321f
+#endif
+
+#endif
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/txbf/haltxbf8814a.c linux-5.8/3rdparty/rtl8812au/hal/phydm/txbf/haltxbf8814a.c
-new file mode 100644
-index 000000000..7ad6ca909
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/txbf/haltxbf8814a.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/txbf/haltxbf8814a.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/txbf/haltxbf8814a.c
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/txbf/haltxbf8814a.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/txbf/haltxbf8814a.c 2021-03-07 18:16:17.069956761 +0200
@@ -0,0 +1,675 @@
+/******************************************************************************
+ *
@@ -294116,11 +290828,9 @@ index 000000000..7ad6ca909
+#endif /* @(RTL8814A_SUPPORT == 1)*/
+
+#endif
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/txbf/haltxbf8814a.h linux-5.8/3rdparty/rtl8812au/hal/phydm/txbf/haltxbf8814a.h
-new file mode 100644
-index 000000000..61b33bbfb
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/txbf/haltxbf8814a.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/txbf/haltxbf8814a.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/txbf/haltxbf8814a.h
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/txbf/haltxbf8814a.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/txbf/haltxbf8814a.h 2021-03-07 18:16:17.069956761 +0200
@@ -0,0 +1,77 @@
+/******************************************************************************
+ *
@@ -294199,11 +290909,9 @@ index 000000000..61b33bbfb
+#endif
+
+#endif
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/txbf/haltxbf8822b.c linux-5.8/3rdparty/rtl8812au/hal/phydm/txbf/haltxbf8822b.c
-new file mode 100644
-index 000000000..f25912a5e
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/txbf/haltxbf8822b.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/txbf/haltxbf8822b.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/txbf/haltxbf8822b.c
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/txbf/haltxbf8822b.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/txbf/haltxbf8822b.c 2021-03-07 18:16:17.069956761 +0200
@@ -0,0 +1,1087 @@
+/******************************************************************************
+ *
@@ -295292,11 +292000,9 @@ index 000000000..f25912a5e
+}
+#endif
+#endif /* @(RTL8822B_SUPPORT == 1)*/
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/txbf/haltxbf8822b.h linux-5.8/3rdparty/rtl8812au/hal/phydm/txbf/haltxbf8822b.h
-new file mode 100644
-index 000000000..552fba2a7
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/txbf/haltxbf8822b.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/txbf/haltxbf8822b.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/txbf/haltxbf8822b.h
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/txbf/haltxbf8822b.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/txbf/haltxbf8822b.h 2021-03-07 18:16:17.069956761 +0200
@@ -0,0 +1,78 @@
+/******************************************************************************
+ *
@@ -295376,11 +292082,9 @@ index 000000000..552fba2a7
+
+#endif
+#endif
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/txbf/haltxbfinterface.c linux-5.8/3rdparty/rtl8812au/hal/phydm/txbf/haltxbfinterface.c
-new file mode 100644
-index 000000000..c125fecad
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/txbf/haltxbfinterface.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/txbf/haltxbfinterface.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/txbf/haltxbfinterface.c
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/txbf/haltxbfinterface.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/txbf/haltxbfinterface.c 2021-03-07 18:16:17.069956761 +0200
@@ -0,0 +1,1484 @@
+/******************************************************************************
+ *
@@ -296866,11 +293570,9 @@ index 000000000..c125fecad
+}
+
+#endif
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/txbf/haltxbfinterface.h linux-5.8/3rdparty/rtl8812au/hal/phydm/txbf/haltxbfinterface.h
-new file mode 100644
-index 000000000..b97aa349e
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/txbf/haltxbfinterface.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/txbf/haltxbfinterface.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/txbf/haltxbfinterface.h
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/txbf/haltxbfinterface.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/txbf/haltxbfinterface.h 2021-03-07 18:16:17.069956761 +0200
@@ -0,0 +1,167 @@
+/******************************************************************************
+ *
@@ -297039,11 +293741,9 @@ index 000000000..b97aa349e
+#endif
+
+#endif
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/txbf/haltxbfjaguar.c linux-5.8/3rdparty/rtl8812au/hal/phydm/txbf/haltxbfjaguar.c
-new file mode 100644
-index 000000000..18a47d4a9
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/txbf/haltxbfjaguar.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/txbf/haltxbfjaguar.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/txbf/haltxbfjaguar.c
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/txbf/haltxbfjaguar.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/txbf/haltxbfjaguar.c 2021-03-07 18:16:17.070956809 +0200
@@ -0,0 +1,510 @@
+/******************************************************************************
+ *
@@ -297555,11 +294255,9 @@ index 000000000..18a47d4a9
+#endif
+
+#endif
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/txbf/haltxbfjaguar.h linux-5.8/3rdparty/rtl8812au/hal/phydm/txbf/haltxbfjaguar.h
-new file mode 100644
-index 000000000..2c9a623ba
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/txbf/haltxbfjaguar.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/txbf/haltxbfjaguar.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/txbf/haltxbfjaguar.h
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/txbf/haltxbfjaguar.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/txbf/haltxbfjaguar.h 2021-03-07 18:16:17.070956809 +0200
@@ -0,0 +1,78 @@
+/******************************************************************************
+ *
@@ -297639,11 +294337,9 @@ index 000000000..2c9a623ba
+#endif
+
+#endif /* @#ifndef __HAL_TXBF_JAGUAR_H__ */
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/txbf/phydm_hal_txbf_api.c linux-5.8/3rdparty/rtl8812au/hal/phydm/txbf/phydm_hal_txbf_api.c
-new file mode 100644
-index 000000000..a7f7e14fb
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/txbf/phydm_hal_txbf_api.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/txbf/phydm_hal_txbf_api.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/txbf/phydm_hal_txbf_api.c
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/txbf/phydm_hal_txbf_api.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/txbf/phydm_hal_txbf_api.c 2021-03-07 18:16:17.070956809 +0200
@@ -0,0 +1,425 @@
+/******************************************************************************
+ *
@@ -298070,11 +294766,9 @@ index 000000000..a7f7e14fb
+#endif
+#endif /*PHYSTS_3RD_TYPE_IC*/
+#endif /*CONFIG_BB_TXBF_API*/
-diff --git linux-5.8/3rdparty/rtl8812au/hal/phydm/txbf/phydm_hal_txbf_api.h linux-5.8/3rdparty/rtl8812au/hal/phydm/txbf/phydm_hal_txbf_api.h
-new file mode 100644
-index 000000000..7755bcaf9
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/phydm/txbf/phydm_hal_txbf_api.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/phydm/txbf/phydm_hal_txbf_api.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/txbf/phydm_hal_txbf_api.h
+--- linux-5.11.4/3rdparty/rtl8812au/hal/phydm/txbf/phydm_hal_txbf_api.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/phydm/txbf/phydm_hal_txbf_api.h 2021-03-07 18:16:17.070956809 +0200
@@ -0,0 +1,74 @@
+/******************************************************************************
+ *
@@ -298150,192 +294844,9 @@ index 000000000..7755bcaf9
+
+#endif
+#endif
-diff --git linux-5.8/3rdparty/rtl8812au/hal/rtl8812a/Hal8812PwrSeq.c linux-5.8/3rdparty/rtl8812au/hal/rtl8812a/Hal8812PwrSeq.c
-new file mode 100644
-index 000000000..f450325fd
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/rtl8812a/Hal8812PwrSeq.c
-@@ -0,0 +1,83 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+
-+#include "Hal8812PwrSeq.h"
-+#include
-+
-+/*
-+ drivers should parse below arrays and do the corresponding actions
-+*/
-+/* 3 Power on Array */
-+WLAN_PWR_CFG rtl8812_power_on_flow[RTL8812_TRANS_CARDEMU_TO_ACT_STEPS + RTL8812_TRANS_END_STEPS] = {
-+ RTL8812_TRANS_CARDEMU_TO_ACT
-+ RTL8812_TRANS_END
-+};
-+
-+/* 3Radio off GPIO Array */
-+WLAN_PWR_CFG rtl8812_radio_off_flow[RTL8812_TRANS_ACT_TO_CARDEMU_STEPS + RTL8812_TRANS_END_STEPS] = {
-+ RTL8812_TRANS_ACT_TO_CARDEMU
-+ RTL8812_TRANS_END
-+};
-+
-+/* 3Card Disable Array */
-+WLAN_PWR_CFG rtl8812_card_disable_flow[RTL8812_TRANS_ACT_TO_CARDEMU_STEPS + RTL8812_TRANS_CARDEMU_TO_PDN_STEPS + RTL8812_TRANS_END_STEPS] = {
-+ RTL8812_TRANS_ACT_TO_CARDEMU
-+ RTL8812_TRANS_CARDEMU_TO_CARDDIS
-+ RTL8812_TRANS_END
-+};
-+
-+/* 3 Card Enable Array */
-+WLAN_PWR_CFG rtl8812_card_enable_flow[RTL8812_TRANS_ACT_TO_CARDEMU_STEPS + RTL8812_TRANS_CARDEMU_TO_PDN_STEPS + RTL8812_TRANS_END_STEPS] = {
-+ RTL8812_TRANS_CARDDIS_TO_CARDEMU
-+ RTL8812_TRANS_CARDEMU_TO_ACT
-+ RTL8812_TRANS_END
-+};
-+
-+/* 3Suspend Array */
-+WLAN_PWR_CFG rtl8812_suspend_flow[RTL8812_TRANS_ACT_TO_CARDEMU_STEPS + RTL8812_TRANS_CARDEMU_TO_SUS_STEPS + RTL8812_TRANS_END_STEPS] = {
-+ RTL8812_TRANS_ACT_TO_CARDEMU
-+ RTL8812_TRANS_CARDEMU_TO_SUS
-+ RTL8812_TRANS_END
-+};
-+
-+/* 3 Resume Array */
-+WLAN_PWR_CFG rtl8812_resume_flow[RTL8812_TRANS_ACT_TO_CARDEMU_STEPS + RTL8812_TRANS_CARDEMU_TO_SUS_STEPS + RTL8812_TRANS_END_STEPS] = {
-+ RTL8812_TRANS_SUS_TO_CARDEMU
-+ RTL8812_TRANS_CARDEMU_TO_ACT
-+ RTL8812_TRANS_END
-+};
-+
-+
-+
-+/* 3HWPDN Array */
-+WLAN_PWR_CFG rtl8812_hwpdn_flow[RTL8812_TRANS_ACT_TO_CARDEMU_STEPS + RTL8812_TRANS_CARDEMU_TO_PDN_STEPS + RTL8812_TRANS_END_STEPS] = {
-+ RTL8812_TRANS_ACT_TO_CARDEMU
-+ RTL8812_TRANS_CARDEMU_TO_PDN
-+ RTL8812_TRANS_END
-+};
-+
-+/* 3 Enter LPS */
-+WLAN_PWR_CFG rtl8812_enter_lps_flow[RTL8812_TRANS_ACT_TO_LPS_STEPS + RTL8812_TRANS_END_STEPS] = {
-+ /* FW behavior */
-+ RTL8812_TRANS_ACT_TO_LPS
-+ RTL8812_TRANS_END
-+};
-+
-+/* 3 Leave LPS */
-+WLAN_PWR_CFG rtl8812_leave_lps_flow[RTL8812_TRANS_LPS_TO_ACT_STEPS + RTL8812_TRANS_END_STEPS] = {
-+ /* FW behavior */
-+ RTL8812_TRANS_LPS_TO_ACT
-+ RTL8812_TRANS_END
-+};
-diff --git linux-5.8/3rdparty/rtl8812au/hal/rtl8812a/Hal8821APwrSeq.c linux-5.8/3rdparty/rtl8812au/hal/rtl8812a/Hal8821APwrSeq.c
-new file mode 100644
-index 000000000..2e13733de
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/rtl8812a/Hal8821APwrSeq.c
-@@ -0,0 +1,86 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) Semiconductor - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+
-+
-+
-+#include "Hal8821APwrSeq.h"
-+#include
-+
-+
-+/*
-+ drivers should parse below arrays and do the corresponding actions
-+*/
-+/* 3 Power on Array */
-+WLAN_PWR_CFG rtl8821A_power_on_flow[RTL8821A_TRANS_CARDEMU_TO_ACT_STEPS + RTL8821A_TRANS_END_STEPS] = {
-+ RTL8821A_TRANS_CARDEMU_TO_ACT
-+ RTL8821A_TRANS_END
-+};
-+
-+/* 3Radio off GPIO Array */
-+WLAN_PWR_CFG rtl8821A_radio_off_flow[RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8821A_TRANS_END_STEPS] = {
-+ RTL8821A_TRANS_ACT_TO_CARDEMU
-+ RTL8821A_TRANS_END
-+};
-+
-+/* 3Card Disable Array */
-+WLAN_PWR_CFG rtl8821A_card_disable_flow[RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8821A_TRANS_CARDEMU_TO_PDN_STEPS + RTL8821A_TRANS_END_STEPS] = {
-+ RTL8821A_TRANS_ACT_TO_CARDEMU
-+ RTL8821A_TRANS_CARDEMU_TO_CARDDIS
-+ RTL8821A_TRANS_END
-+};
-+
-+/* 3 Card Enable Array */
-+WLAN_PWR_CFG rtl8821A_card_enable_flow[RTL8821A_TRANS_CARDDIS_TO_CARDEMU_STEPS + RTL8821A_TRANS_CARDEMU_TO_ACT_STEPS + RTL8821A_TRANS_END_STEPS] = {
-+ RTL8821A_TRANS_CARDDIS_TO_CARDEMU
-+ RTL8821A_TRANS_CARDEMU_TO_ACT
-+ RTL8821A_TRANS_END
-+};
-+
-+/* 3Suspend Array */
-+WLAN_PWR_CFG rtl8821A_suspend_flow[RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8821A_TRANS_CARDEMU_TO_SUS_STEPS + RTL8821A_TRANS_END_STEPS] = {
-+ RTL8821A_TRANS_ACT_TO_CARDEMU
-+ RTL8821A_TRANS_CARDEMU_TO_SUS
-+ RTL8821A_TRANS_END
-+};
-+
-+/* 3 Resume Array */
-+WLAN_PWR_CFG rtl8821A_resume_flow[RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8821A_TRANS_CARDEMU_TO_SUS_STEPS + RTL8821A_TRANS_END_STEPS] = {
-+ RTL8821A_TRANS_SUS_TO_CARDEMU
-+ RTL8821A_TRANS_CARDEMU_TO_ACT
-+ RTL8821A_TRANS_END
-+};
-+
-+
-+
-+/* 3HWPDN Array */
-+WLAN_PWR_CFG rtl8821A_hwpdn_flow[RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8821A_TRANS_CARDEMU_TO_PDN_STEPS + RTL8821A_TRANS_END_STEPS] = {
-+ RTL8821A_TRANS_ACT_TO_CARDEMU
-+ RTL8821A_TRANS_CARDEMU_TO_PDN
-+ RTL8821A_TRANS_END
-+};
-+
-+/* 3 Enter LPS */
-+WLAN_PWR_CFG rtl8821A_enter_lps_flow[RTL8821A_TRANS_ACT_TO_LPS_STEPS + RTL8821A_TRANS_END_STEPS] = {
-+ /* FW behavior */
-+ RTL8821A_TRANS_ACT_TO_LPS
-+ RTL8821A_TRANS_END
-+};
-+
-+/* 3 Leave LPS */
-+WLAN_PWR_CFG rtl8821A_leave_lps_flow[RTL8821A_TRANS_LPS_TO_ACT_STEPS + RTL8821A_TRANS_END_STEPS] = {
-+ /* FW behavior */
-+ RTL8821A_TRANS_LPS_TO_ACT
-+ RTL8821A_TRANS_END
-+};
-diff --git linux-5.8/3rdparty/rtl8812au/hal/rtl8812a/hal8812a_fw.c linux-5.8/3rdparty/rtl8812au/hal/rtl8812a/hal8812a_fw.c
-new file mode 100644
-index 000000000..388d84452
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/rtl8812a/hal8812a_fw.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/rtl8812a/hal8812a_fw.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/rtl8812a/hal8812a_fw.c
+--- linux-5.11.4/3rdparty/rtl8812au/hal/rtl8812a/hal8812a_fw.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/rtl8812a/hal8812a_fw.c 2021-03-07 18:16:17.074956998 +0200
@@ -0,0 +1,17941 @@
+/******************************************************************************
+*
@@ -316278,11 +312789,9 @@ index 000000000..388d84452
+#endif /* end of LOAD_FW_HEADER_FROM_DRIVER */
+
+#endif
-diff --git linux-5.8/3rdparty/rtl8812au/hal/rtl8812a/hal8812a_fw.h linux-5.8/3rdparty/rtl8812au/hal/rtl8812a/hal8812a_fw.h
-new file mode 100644
-index 000000000..0a370d534
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/rtl8812a/hal8812a_fw.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/rtl8812a/hal8812a_fw.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/rtl8812a/hal8812a_fw.h
+--- linux-5.11.4/3rdparty/rtl8812au/hal/rtl8812a/hal8812a_fw.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/rtl8812a/hal8812a_fw.h 2021-03-07 18:16:17.074956998 +0200
@@ -0,0 +1,47 @@
+/******************************************************************************
+*
@@ -316331,11 +312840,96 @@ index 000000000..0a370d534
+
+#endif
+
-diff --git linux-5.8/3rdparty/rtl8812au/hal/rtl8812a/hal8821a_fw.c linux-5.8/3rdparty/rtl8812au/hal/rtl8812a/hal8821a_fw.c
-new file mode 100644
-index 000000000..40728f7cc
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/rtl8812a/hal8821a_fw.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/rtl8812a/Hal8812PwrSeq.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/rtl8812a/Hal8812PwrSeq.c
+--- linux-5.11.4/3rdparty/rtl8812au/hal/rtl8812a/Hal8812PwrSeq.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/rtl8812a/Hal8812PwrSeq.c 2021-03-07 18:16:17.070956809 +0200
+@@ -0,0 +1,83 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++
++#include "Hal8812PwrSeq.h"
++#include
++
++/*
++ drivers should parse below arrays and do the corresponding actions
++*/
++/* 3 Power on Array */
++WLAN_PWR_CFG rtl8812_power_on_flow[RTL8812_TRANS_CARDEMU_TO_ACT_STEPS + RTL8812_TRANS_END_STEPS] = {
++ RTL8812_TRANS_CARDEMU_TO_ACT
++ RTL8812_TRANS_END
++};
++
++/* 3Radio off GPIO Array */
++WLAN_PWR_CFG rtl8812_radio_off_flow[RTL8812_TRANS_ACT_TO_CARDEMU_STEPS + RTL8812_TRANS_END_STEPS] = {
++ RTL8812_TRANS_ACT_TO_CARDEMU
++ RTL8812_TRANS_END
++};
++
++/* 3Card Disable Array */
++WLAN_PWR_CFG rtl8812_card_disable_flow[RTL8812_TRANS_ACT_TO_CARDEMU_STEPS + RTL8812_TRANS_CARDEMU_TO_PDN_STEPS + RTL8812_TRANS_END_STEPS] = {
++ RTL8812_TRANS_ACT_TO_CARDEMU
++ RTL8812_TRANS_CARDEMU_TO_CARDDIS
++ RTL8812_TRANS_END
++};
++
++/* 3 Card Enable Array */
++WLAN_PWR_CFG rtl8812_card_enable_flow[RTL8812_TRANS_ACT_TO_CARDEMU_STEPS + RTL8812_TRANS_CARDEMU_TO_PDN_STEPS + RTL8812_TRANS_END_STEPS] = {
++ RTL8812_TRANS_CARDDIS_TO_CARDEMU
++ RTL8812_TRANS_CARDEMU_TO_ACT
++ RTL8812_TRANS_END
++};
++
++/* 3Suspend Array */
++WLAN_PWR_CFG rtl8812_suspend_flow[RTL8812_TRANS_ACT_TO_CARDEMU_STEPS + RTL8812_TRANS_CARDEMU_TO_SUS_STEPS + RTL8812_TRANS_END_STEPS] = {
++ RTL8812_TRANS_ACT_TO_CARDEMU
++ RTL8812_TRANS_CARDEMU_TO_SUS
++ RTL8812_TRANS_END
++};
++
++/* 3 Resume Array */
++WLAN_PWR_CFG rtl8812_resume_flow[RTL8812_TRANS_ACT_TO_CARDEMU_STEPS + RTL8812_TRANS_CARDEMU_TO_SUS_STEPS + RTL8812_TRANS_END_STEPS] = {
++ RTL8812_TRANS_SUS_TO_CARDEMU
++ RTL8812_TRANS_CARDEMU_TO_ACT
++ RTL8812_TRANS_END
++};
++
++
++
++/* 3HWPDN Array */
++WLAN_PWR_CFG rtl8812_hwpdn_flow[RTL8812_TRANS_ACT_TO_CARDEMU_STEPS + RTL8812_TRANS_CARDEMU_TO_PDN_STEPS + RTL8812_TRANS_END_STEPS] = {
++ RTL8812_TRANS_ACT_TO_CARDEMU
++ RTL8812_TRANS_CARDEMU_TO_PDN
++ RTL8812_TRANS_END
++};
++
++/* 3 Enter LPS */
++WLAN_PWR_CFG rtl8812_enter_lps_flow[RTL8812_TRANS_ACT_TO_LPS_STEPS + RTL8812_TRANS_END_STEPS] = {
++ /* FW behavior */
++ RTL8812_TRANS_ACT_TO_LPS
++ RTL8812_TRANS_END
++};
++
++/* 3 Leave LPS */
++WLAN_PWR_CFG rtl8812_leave_lps_flow[RTL8812_TRANS_LPS_TO_ACT_STEPS + RTL8812_TRANS_END_STEPS] = {
++ /* FW behavior */
++ RTL8812_TRANS_LPS_TO_ACT
++ RTL8812_TRANS_END
++};
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/rtl8812a/hal8821a_fw.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/rtl8812a/hal8821a_fw.c
+--- linux-5.11.4/3rdparty/rtl8812au/hal/rtl8812a/hal8821a_fw.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/rtl8812a/hal8821a_fw.c 2021-03-07 18:16:17.078957187 +0200
@@ -0,0 +1,14005 @@
+/******************************************************************************
+*
@@ -330342,11 +326936,9 @@ index 000000000..40728f7cc
+#endif /* end of LOAD_FW_HEADER_FROM_DRIVER */
+
+#endif
-diff --git linux-5.8/3rdparty/rtl8812au/hal/rtl8812a/hal8821a_fw.h linux-5.8/3rdparty/rtl8812au/hal/rtl8812a/hal8821a_fw.h
-new file mode 100644
-index 000000000..16b394f16
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/rtl8812a/hal8821a_fw.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/rtl8812a/hal8821a_fw.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/rtl8812a/hal8821a_fw.h
+--- linux-5.11.4/3rdparty/rtl8812au/hal/rtl8812a/hal8821a_fw.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/rtl8812a/hal8821a_fw.h 2021-03-07 18:16:17.078957187 +0200
@@ -0,0 +1,47 @@
+/******************************************************************************
+*
@@ -330395,11 +326987,99 @@ index 000000000..16b394f16
+
+#endif
+
-diff --git linux-5.8/3rdparty/rtl8812au/hal/rtl8812a/rtl8812a_cmd.c linux-5.8/3rdparty/rtl8812au/hal/rtl8812a/rtl8812a_cmd.c
-new file mode 100644
-index 000000000..ecbb397d5
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/rtl8812a/rtl8812a_cmd.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/rtl8812a/Hal8821APwrSeq.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/rtl8812a/Hal8821APwrSeq.c
+--- linux-5.11.4/3rdparty/rtl8812au/hal/rtl8812a/Hal8821APwrSeq.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/rtl8812a/Hal8821APwrSeq.c 2021-03-07 18:16:17.070956809 +0200
+@@ -0,0 +1,86 @@
++/******************************************************************************
++ *
++ * Copyright(c) Semiconductor - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++
++
++
++#include "Hal8821APwrSeq.h"
++#include
++
++
++/*
++ drivers should parse below arrays and do the corresponding actions
++*/
++/* 3 Power on Array */
++WLAN_PWR_CFG rtl8821A_power_on_flow[RTL8821A_TRANS_CARDEMU_TO_ACT_STEPS + RTL8821A_TRANS_END_STEPS] = {
++ RTL8821A_TRANS_CARDEMU_TO_ACT
++ RTL8821A_TRANS_END
++};
++
++/* 3Radio off GPIO Array */
++WLAN_PWR_CFG rtl8821A_radio_off_flow[RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8821A_TRANS_END_STEPS] = {
++ RTL8821A_TRANS_ACT_TO_CARDEMU
++ RTL8821A_TRANS_END
++};
++
++/* 3Card Disable Array */
++WLAN_PWR_CFG rtl8821A_card_disable_flow[RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8821A_TRANS_CARDEMU_TO_PDN_STEPS + RTL8821A_TRANS_END_STEPS] = {
++ RTL8821A_TRANS_ACT_TO_CARDEMU
++ RTL8821A_TRANS_CARDEMU_TO_CARDDIS
++ RTL8821A_TRANS_END
++};
++
++/* 3 Card Enable Array */
++WLAN_PWR_CFG rtl8821A_card_enable_flow[RTL8821A_TRANS_CARDDIS_TO_CARDEMU_STEPS + RTL8821A_TRANS_CARDEMU_TO_ACT_STEPS + RTL8821A_TRANS_END_STEPS] = {
++ RTL8821A_TRANS_CARDDIS_TO_CARDEMU
++ RTL8821A_TRANS_CARDEMU_TO_ACT
++ RTL8821A_TRANS_END
++};
++
++/* 3Suspend Array */
++WLAN_PWR_CFG rtl8821A_suspend_flow[RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8821A_TRANS_CARDEMU_TO_SUS_STEPS + RTL8821A_TRANS_END_STEPS] = {
++ RTL8821A_TRANS_ACT_TO_CARDEMU
++ RTL8821A_TRANS_CARDEMU_TO_SUS
++ RTL8821A_TRANS_END
++};
++
++/* 3 Resume Array */
++WLAN_PWR_CFG rtl8821A_resume_flow[RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8821A_TRANS_CARDEMU_TO_SUS_STEPS + RTL8821A_TRANS_END_STEPS] = {
++ RTL8821A_TRANS_SUS_TO_CARDEMU
++ RTL8821A_TRANS_CARDEMU_TO_ACT
++ RTL8821A_TRANS_END
++};
++
++
++
++/* 3HWPDN Array */
++WLAN_PWR_CFG rtl8821A_hwpdn_flow[RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8821A_TRANS_CARDEMU_TO_PDN_STEPS + RTL8821A_TRANS_END_STEPS] = {
++ RTL8821A_TRANS_ACT_TO_CARDEMU
++ RTL8821A_TRANS_CARDEMU_TO_PDN
++ RTL8821A_TRANS_END
++};
++
++/* 3 Enter LPS */
++WLAN_PWR_CFG rtl8821A_enter_lps_flow[RTL8821A_TRANS_ACT_TO_LPS_STEPS + RTL8821A_TRANS_END_STEPS] = {
++ /* FW behavior */
++ RTL8821A_TRANS_ACT_TO_LPS
++ RTL8821A_TRANS_END
++};
++
++/* 3 Leave LPS */
++WLAN_PWR_CFG rtl8821A_leave_lps_flow[RTL8821A_TRANS_LPS_TO_ACT_STEPS + RTL8821A_TRANS_END_STEPS] = {
++ /* FW behavior */
++ RTL8821A_TRANS_LPS_TO_ACT
++ RTL8821A_TRANS_END
++};
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/rtl8812a/rtl8812a_cmd.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/rtl8812a/rtl8812a_cmd.c
+--- linux-5.11.4/3rdparty/rtl8812au/hal/rtl8812a/rtl8812a_cmd.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/rtl8812a/rtl8812a_cmd.c 2021-03-07 18:16:17.079957235 +0200
@@ -0,0 +1,860 @@
+/******************************************************************************
+ *
@@ -331261,11 +327941,9 @@ index 000000000..ecbb397d5
+}
+
+#endif /* CONFIG_BT_COEXIST */
-diff --git linux-5.8/3rdparty/rtl8812au/hal/rtl8812a/rtl8812a_dm.c linux-5.8/3rdparty/rtl8812au/hal/rtl8812a/rtl8812a_dm.c
-new file mode 100644
-index 000000000..56c7cc750
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/rtl8812a/rtl8812a_dm.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/rtl8812a/rtl8812a_dm.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/rtl8812a/rtl8812a_dm.c
+--- linux-5.11.4/3rdparty/rtl8812au/hal/rtl8812a/rtl8812a_dm.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/rtl8812a/rtl8812a_dm.c 2021-03-07 18:16:17.079957235 +0200
@@ -0,0 +1,360 @@
+/******************************************************************************
+ *
@@ -331627,11 +328305,9 @@ index 000000000..56c7cc750
+ /* _rtw_spinlock_free(&pHalData->odm_stainfo_lock); */
+ odm_cancel_all_timers(podmpriv);
+}
-diff --git linux-5.8/3rdparty/rtl8812au/hal/rtl8812a/rtl8812a_hal_init.c linux-5.8/3rdparty/rtl8812au/hal/rtl8812a/rtl8812a_hal_init.c
-new file mode 100644
-index 000000000..4a21818b7
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/rtl8812a/rtl8812a_hal_init.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/rtl8812a/rtl8812a_hal_init.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/rtl8812a/rtl8812a_hal_init.c
+--- linux-5.11.4/3rdparty/rtl8812au/hal/rtl8812a/rtl8812a_hal_init.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/rtl8812a/rtl8812a_hal_init.c 2021-03-07 18:16:17.079957235 +0200
@@ -0,0 +1,5777 @@
+/******************************************************************************
+ *
@@ -337410,12 +334086,10 @@ index 000000000..4a21818b7
+ pHalFunc->fw_dl = &FirmwareDownload8812;
+ pHalFunc->hal_get_tx_buff_rsvd_page_num = &GetTxBufferRsvdPageNum8812;
+}
-diff --git linux-5.8/3rdparty/rtl8812au/hal/rtl8812a/rtl8812a_phycfg.c linux-5.8/3rdparty/rtl8812au/hal/rtl8812a/rtl8812a_phycfg.c
-new file mode 100644
-index 000000000..4fb1b8cef
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/rtl8812a/rtl8812a_phycfg.c
-@@ -0,0 +1,2041 @@
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/rtl8812a/rtl8812a_phycfg.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/rtl8812a/rtl8812a_phycfg.c
+--- linux-5.11.4/3rdparty/rtl8812au/hal/rtl8812a/rtl8812a_phycfg.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/rtl8812a/rtl8812a_phycfg.c 2021-03-07 18:16:17.080957282 +0200
+@@ -0,0 +1,2045 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
@@ -339216,9 +335890,11 @@ index 000000000..4fb1b8cef
+ /* fc_area */
+ if (36 <= channelToSW && channelToSW <= 48)
+ phy_set_bb_reg(pAdapter, rFc_area_Jaguar, 0x1ffe0000, 0x494);
-+ else if (50 <= channelToSW && channelToSW <= 64)
++ else if (15 <= channelToSW && channelToSW <= 35)
++ phy_set_bb_reg(pAdapter, rFc_area_Jaguar, 0x1ffe0000, 0x494);
++ else if (50 <= channelToSW && channelToSW <= 80)
+ phy_set_bb_reg(pAdapter, rFc_area_Jaguar, 0x1ffe0000, 0x453);
-+ else if (100 <= channelToSW && channelToSW <= 116)
++ else if (82 <= channelToSW && channelToSW <= 116)
+ phy_set_bb_reg(pAdapter, rFc_area_Jaguar, 0x1ffe0000, 0x452);
+ else if (118 <= channelToSW)
+ phy_set_bb_reg(pAdapter, rFc_area_Jaguar, 0x1ffe0000, 0x412);
@@ -339227,9 +335903,11 @@ index 000000000..4fb1b8cef
+
+ for (eRFPath = 0; eRFPath < pHalData->NumTotalRFPath; eRFPath++) {
+ /* RF_MOD_AG */
-+ if (36 <= channelToSW && channelToSW <= 64)
++ if (36 <= channelToSW && channelToSW <= 80)
+ phy_set_rf_reg(pAdapter, eRFPath, RF_CHNLBW_Jaguar, BIT18 | BIT17 | BIT16 | BIT9 | BIT8, 0x101); /* 5'b00101); */
-+ else if (100 <= channelToSW && channelToSW <= 140)
++ else if (15 <= channelToSW && channelToSW <= 35)
++ phy_set_rf_reg(pAdapter, eRFPath, RF_CHNLBW_Jaguar, BIT18 | BIT17 | BIT16 | BIT9 | BIT8, 0x101); /* 5'b00101); */
++ else if (82 <= channelToSW && channelToSW <= 140)
+ phy_set_rf_reg(pAdapter, eRFPath, RF_CHNLBW_Jaguar, BIT18 | BIT17 | BIT16 | BIT9 | BIT8, 0x301); /* 5'b01101); */
+ else if (140 < channelToSW)
+ phy_set_rf_reg(pAdapter, eRFPath, RF_CHNLBW_Jaguar, BIT18 | BIT17 | BIT16 | BIT9 | BIT8, 0x501); /* 5'b10101); */
@@ -339244,25 +335922,25 @@ index 000000000..4fb1b8cef
+ /* <20130104, Kordan> APK for MP chip is done on initialization from folder. */
+ if (IS_HARDWARE_TYPE_8821U(pAdapter) && (!IS_NORMAL_CHIP(pHalData->version_id)) && channelToSW > 14) {
+ /* <20121116, Kordan> For better result of APK. Asked by AlexWang. */
-+ if (36 <= channelToSW && channelToSW <= 64)
++ if (15 <= channelToSW && channelToSW <= 80)
+ phy_set_rf_reg(pAdapter, eRFPath, RF_APK_Jaguar, bRFRegOffsetMask, 0x710E7);
-+ else if (100 <= channelToSW && channelToSW <= 140)
++ else if (82 <= channelToSW && channelToSW <= 140)
+ phy_set_rf_reg(pAdapter, eRFPath, RF_APK_Jaguar, bRFRegOffsetMask, 0x716E9);
+ else
+ phy_set_rf_reg(pAdapter, eRFPath, RF_APK_Jaguar, bRFRegOffsetMask, 0x714E9);
+ } else if (IS_HARDWARE_TYPE_8821S(pAdapter) && channelToSW > 14) {
+ /* <20130111, Kordan> For better result of APK. Asked by Willson. */
-+ if (36 <= channelToSW && channelToSW <= 64)
++ if (15 <= channelToSW && channelToSW <= 80)
+ phy_set_rf_reg(pAdapter, eRFPath, RF_APK_Jaguar, bRFRegOffsetMask, 0x714E9);
-+ else if (100 <= channelToSW && channelToSW <= 140)
++ else if (82 <= channelToSW && channelToSW <= 140)
+ phy_set_rf_reg(pAdapter, eRFPath, RF_APK_Jaguar, bRFRegOffsetMask, 0x110E9);
+ else
+ phy_set_rf_reg(pAdapter, eRFPath, RF_APK_Jaguar, bRFRegOffsetMask, 0x714E9);
+ } else if (IS_HARDWARE_TYPE_8821E(pAdapter) && channelToSW > 14) {
+ /* <20130613, Kordan> For better result of APK. Asked by Willson. */
-+ if (36 <= channelToSW && channelToSW <= 64)
++ if (15 <= channelToSW && channelToSW <= 80)
+ phy_set_rf_reg(pAdapter, eRFPath, RF_APK_Jaguar, bRFRegOffsetMask, 0x114E9);
-+ else if (100 <= channelToSW && channelToSW <= 140)
++ else if (82 <= channelToSW && channelToSW <= 140)
+ phy_set_rf_reg(pAdapter, eRFPath, RF_APK_Jaguar, bRFRegOffsetMask, 0x110E9);
+ else
+ phy_set_rf_reg(pAdapter, eRFPath, RF_APK_Jaguar, bRFRegOffsetMask, 0x110E9);
@@ -339457,11 +336135,9 @@ index 000000000..4fb1b8cef
+
+ /* RTW_INFO("<==%s()\n",__FUNCTION__); */
+}
-diff --git linux-5.8/3rdparty/rtl8812au/hal/rtl8812a/rtl8812a_rf6052.c linux-5.8/3rdparty/rtl8812au/hal/rtl8812a/rtl8812a_rf6052.c
-new file mode 100644
-index 000000000..c2060b7b1
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/rtl8812a/rtl8812a_rf6052.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/rtl8812a/rtl8812a_rf6052.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/rtl8812a/rtl8812a_rf6052.c
+--- linux-5.11.4/3rdparty/rtl8812au/hal/rtl8812a/rtl8812a_rf6052.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/rtl8812a/rtl8812a_rf6052.c 2021-03-07 18:16:17.080957282 +0200
@@ -0,0 +1,158 @@
+/******************************************************************************
+ *
@@ -339621,11 +336297,9 @@ index 000000000..c2060b7b1
+
+
+/* End of HalRf6052.c */
-diff --git linux-5.8/3rdparty/rtl8812au/hal/rtl8812a/rtl8812a_rxdesc.c linux-5.8/3rdparty/rtl8812au/hal/rtl8812a/rtl8812a_rxdesc.c
-new file mode 100644
-index 000000000..1ae5f21fb
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/rtl8812a/rtl8812a_rxdesc.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/rtl8812a/rtl8812a_rxdesc.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/rtl8812a/rtl8812a_rxdesc.c
+--- linux-5.11.4/3rdparty/rtl8812au/hal/rtl8812a/rtl8812a_rxdesc.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/rtl8812a/rtl8812a_rxdesc.c 2021-03-07 18:16:17.080957282 +0200
@@ -0,0 +1,62 @@
+/******************************************************************************
+ *
@@ -339689,11 +336363,9 @@ index 000000000..1ae5f21fb
+ /* Offset 20 */
+ /* pattrib->tsfl=(u8)GET_RX_STATUS_DESC_TSFL_8812(pdesc); */
+}
-diff --git linux-5.8/3rdparty/rtl8812au/hal/rtl8812a/rtl8812a_sreset.c linux-5.8/3rdparty/rtl8812au/hal/rtl8812a/rtl8812a_sreset.c
-new file mode 100644
-index 000000000..43edc9728
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/rtl8812a/rtl8812a_sreset.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/rtl8812a/rtl8812a_sreset.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/rtl8812a/rtl8812a_sreset.c
+--- linux-5.11.4/3rdparty/rtl8812au/hal/rtl8812a/rtl8812a_sreset.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/rtl8812a/rtl8812a_sreset.c 2021-03-07 18:16:17.080957282 +0200
@@ -0,0 +1,106 @@
+/******************************************************************************
+ *
@@ -339801,11 +336473,9 @@ index 000000000..43edc9728
+ }
+}
+#endif
-diff --git linux-5.8/3rdparty/rtl8812au/hal/rtl8812a/rtl8812a_xmit.c linux-5.8/3rdparty/rtl8812au/hal/rtl8812a/rtl8812a_xmit.c
-new file mode 100644
-index 000000000..dd2887594
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/rtl8812a/rtl8812a_xmit.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/rtl8812a/rtl8812a_xmit.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/rtl8812a/rtl8812a_xmit.c
+--- linux-5.11.4/3rdparty/rtl8812au/hal/rtl8812a/rtl8812a_xmit.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/rtl8812a/rtl8812a_xmit.c 2021-03-07 18:16:17.080957282 +0200
@@ -0,0 +1,515 @@
+/******************************************************************************
+ *
@@ -340322,11 +336992,9 @@ index 000000000..dd2887594
+
+ return SCSettingOfDesc;
+}
-diff --git linux-5.8/3rdparty/rtl8812au/hal/rtl8812a/usb/rtl8812au_led.c linux-5.8/3rdparty/rtl8812au/hal/rtl8812a/usb/rtl8812au_led.c
-new file mode 100644
-index 000000000..e9ed78a23
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/rtl8812a/usb/rtl8812au_led.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/rtl8812a/usb/rtl8812au_led.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/rtl8812a/usb/rtl8812au_led.c
+--- linux-5.11.4/3rdparty/rtl8812au/hal/rtl8812a/usb/rtl8812au_led.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/rtl8812a/usb/rtl8812au_led.c 2021-03-07 18:16:17.080957282 +0200
@@ -0,0 +1,389 @@
+/******************************************************************************
+ *
@@ -340717,11 +337385,9 @@ index 000000000..e9ed78a23
+ DeInitLed(&(ledpriv->SwLed2));
+}
+#endif
-diff --git linux-5.8/3rdparty/rtl8812au/hal/rtl8812a/usb/rtl8812au_recv.c linux-5.8/3rdparty/rtl8812au/hal/rtl8812a/usb/rtl8812au_recv.c
-new file mode 100644
-index 000000000..5f0f621fe
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/rtl8812a/usb/rtl8812au_recv.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/rtl8812a/usb/rtl8812au_recv.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/rtl8812a/usb/rtl8812au_recv.c
+--- linux-5.11.4/3rdparty/rtl8812au/hal/rtl8812a/usb/rtl8812au_recv.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/rtl8812a/usb/rtl8812au_recv.c 2021-03-07 18:16:17.080957282 +0200
@@ -0,0 +1,28 @@
+/******************************************************************************
+ *
@@ -340751,11 +337417,9 @@ index 000000000..5f0f621fe
+{
+ usb_free_recv_priv(padapter, INTERRUPT_MSG_FORMAT_LEN);
+}
-diff --git linux-5.8/3rdparty/rtl8812au/hal/rtl8812a/usb/rtl8812au_xmit.c linux-5.8/3rdparty/rtl8812au/hal/rtl8812a/usb/rtl8812au_xmit.c
-new file mode 100644
-index 000000000..8da4f79ce
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/rtl8812a/usb/rtl8812au_xmit.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/rtl8812a/usb/rtl8812au_xmit.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/rtl8812a/usb/rtl8812au_xmit.c
+--- linux-5.11.4/3rdparty/rtl8812au/hal/rtl8812a/usb/rtl8812au_xmit.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/rtl8812a/usb/rtl8812au_xmit.c 2021-03-07 18:16:17.080957282 +0200
@@ -0,0 +1,1169 @@
+/******************************************************************************
+ *
@@ -341926,11 +338590,9 @@ index 000000000..8da4f79ce
+
+}
+#endif
-diff --git linux-5.8/3rdparty/rtl8812au/hal/rtl8812a/usb/usb_halinit.c linux-5.8/3rdparty/rtl8812au/hal/rtl8812a/usb/usb_halinit.c
-new file mode 100644
-index 000000000..37d6cec0a
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/rtl8812a/usb/usb_halinit.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/rtl8812a/usb/usb_halinit.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/rtl8812a/usb/usb_halinit.c
+--- linux-5.11.4/3rdparty/rtl8812au/hal/rtl8812a/usb/usb_halinit.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/rtl8812a/usb/usb_halinit.c 2021-03-07 18:16:17.080957282 +0200
@@ -0,0 +1,2716 @@
+/******************************************************************************
+ *
@@ -344648,11 +341310,9 @@ index 000000000..37d6cec0a
+ rtl8812_set_hal_ops(pHalFunc);
+
+}
-diff --git linux-5.8/3rdparty/rtl8812au/hal/rtl8812a/usb/usb_ops_linux.c linux-5.8/3rdparty/rtl8812au/hal/rtl8812a/usb/usb_ops_linux.c
-new file mode 100644
-index 000000000..22f8c42cf
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/rtl8812a/usb/usb_ops_linux.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/rtl8812a/usb/usb_ops_linux.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/rtl8812a/usb/usb_ops_linux.c
+--- linux-5.11.4/3rdparty/rtl8812au/hal/rtl8812a/usb/usb_ops_linux.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/rtl8812a/usb/usb_ops_linux.c 2021-03-07 18:16:17.081957329 +0200
@@ -0,0 +1,244 @@
+/******************************************************************************
+ *
@@ -344898,115 +341558,9 @@ index 000000000..22f8c42cf
+ RTW_INFO("CHIP TYPE: RTL8811AU or RTL8821U\n");
+ }
+}
-diff --git linux-5.8/3rdparty/rtl8812au/hal/rtl8814a/Hal8814PwrSeq.c linux-5.8/3rdparty/rtl8812au/hal/rtl8814a/Hal8814PwrSeq.c
-new file mode 100644
-index 000000000..c11a36e96
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/rtl8814a/Hal8814PwrSeq.c
-@@ -0,0 +1,98 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ * You should have received a copy of the GNU General Public License along with
-+ * this program; if not, write to the Free Software Foundation, Inc.,
-+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
-+ *
-+ *
-+ ******************************************************************************/
-+
-+#include "Hal8814PwrSeq.h"
-+#include
-+
-+/*
-+ drivers should parse below arrays and do the corresponding actions
-+*/
-+//3 Power on Array
-+WLAN_PWR_CFG rtl8814A_power_on_flow[RTL8814A_TRANS_CARDEMU_TO_ACT_STEPS+RTL8814A_TRANS_END_STEPS]=
-+{
-+ RTL8814A_TRANS_CARDEMU_TO_ACT
-+ RTL8814A_TRANS_END
-+};
-+
-+//3Radio off GPIO Array
-+WLAN_PWR_CFG rtl8814A_radio_off_flow[RTL8814A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8814A_TRANS_END_STEPS]=
-+{
-+ RTL8814A_TRANS_ACT_TO_CARDEMU
-+ RTL8814A_TRANS_END
-+};
-+
-+//3Card Disable Array
-+WLAN_PWR_CFG rtl8814A_card_disable_flow[RTL8814A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8814A_TRANS_CARDEMU_TO_PDN_STEPS+RTL8814A_TRANS_END_STEPS]=
-+{
-+ RTL8814A_TRANS_ACT_TO_CARDEMU
-+ RTL8814A_TRANS_CARDEMU_TO_CARDDIS
-+ RTL8814A_TRANS_END
-+};
-+
-+//3 Card Enable Array
-+WLAN_PWR_CFG rtl8814A_card_enable_flow[RTL8814A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8814A_TRANS_CARDEMU_TO_PDN_STEPS+RTL8814A_TRANS_END_STEPS]=
-+{
-+ RTL8814A_TRANS_CARDDIS_TO_CARDEMU
-+ RTL8814A_TRANS_CARDEMU_TO_ACT
-+ RTL8814A_TRANS_END
-+};
-+
-+//3Suspend Array
-+WLAN_PWR_CFG rtl8814A_suspend_flow[RTL8814A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8814A_TRANS_CARDEMU_TO_SUS_STEPS+RTL8814A_TRANS_END_STEPS]=
-+{
-+ RTL8814A_TRANS_ACT_TO_CARDEMU
-+ RTL8814A_TRANS_CARDEMU_TO_SUS
-+ RTL8814A_TRANS_END
-+};
-+
-+//3 Resume Array
-+WLAN_PWR_CFG rtl8814A_resume_flow[RTL8814A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8814A_TRANS_CARDEMU_TO_SUS_STEPS+RTL8814A_TRANS_END_STEPS]=
-+{
-+ RTL8814A_TRANS_SUS_TO_CARDEMU
-+ RTL8814A_TRANS_CARDEMU_TO_ACT
-+ RTL8814A_TRANS_END
-+};
-+
-+
-+
-+//3HWPDN Array
-+WLAN_PWR_CFG rtl8814A_hwpdn_flow[RTL8814A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8814A_TRANS_CARDEMU_TO_PDN_STEPS+RTL8814A_TRANS_END_STEPS]=
-+{
-+ RTL8814A_TRANS_ACT_TO_CARDEMU
-+ RTL8814A_TRANS_CARDEMU_TO_PDN
-+ RTL8814A_TRANS_END
-+};
-+
-+//3 Enter LPS
-+WLAN_PWR_CFG rtl8814A_enter_lps_flow[RTL8814A_TRANS_ACT_TO_LPS_STEPS+RTL8814A_TRANS_END_STEPS]=
-+{
-+ //FW behavior
-+ RTL8814A_TRANS_ACT_TO_LPS
-+ RTL8814A_TRANS_END
-+};
-+
-+//3 Leave LPS
-+WLAN_PWR_CFG rtl8814A_leave_lps_flow[RTL8814A_TRANS_LPS_TO_ACT_STEPS+RTL8814A_TRANS_END_STEPS]=
-+{
-+ //FW behavior
-+ RTL8814A_TRANS_LPS_TO_ACT
-+ RTL8814A_TRANS_END
-+};
-+
-diff --git linux-5.8/3rdparty/rtl8812au/hal/rtl8814a/hal8814a_fw.c linux-5.8/3rdparty/rtl8812au/hal/rtl8814a/hal8814a_fw.c
-new file mode 100644
-index 000000000..fb01dd8c5
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/rtl8814a/hal8814a_fw.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/rtl8814a/hal8814a_fw.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/rtl8814a/hal8814a_fw.c
+--- linux-5.11.4/3rdparty/rtl8812au/hal/rtl8814a/hal8814a_fw.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/rtl8814a/hal8814a_fw.c 2021-03-07 18:16:17.082957376 +0200
@@ -0,0 +1,7741 @@
+/******************************************************************************
+*
@@ -352749,11 +349303,111 @@ index 000000000..fb01dd8c5
+
+#endif // end of HWIMG_SUPPORT
+
-diff --git linux-5.8/3rdparty/rtl8812au/hal/rtl8814a/rtl8814a_cmd.c linux-5.8/3rdparty/rtl8812au/hal/rtl8814a/rtl8814a_cmd.c
-new file mode 100644
-index 000000000..6aa1fda17
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/rtl8814a/rtl8814a_cmd.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/rtl8814a/Hal8814PwrSeq.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/rtl8814a/Hal8814PwrSeq.c
+--- linux-5.11.4/3rdparty/rtl8812au/hal/rtl8814a/Hal8814PwrSeq.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/rtl8814a/Hal8814PwrSeq.c 2021-03-07 18:16:17.081957329 +0200
+@@ -0,0 +1,98 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
++ *
++ *
++ ******************************************************************************/
++
++#include "Hal8814PwrSeq.h"
++#include
++
++/*
++ drivers should parse below arrays and do the corresponding actions
++*/
++//3 Power on Array
++WLAN_PWR_CFG rtl8814A_power_on_flow[RTL8814A_TRANS_CARDEMU_TO_ACT_STEPS+RTL8814A_TRANS_END_STEPS]=
++{
++ RTL8814A_TRANS_CARDEMU_TO_ACT
++ RTL8814A_TRANS_END
++};
++
++//3Radio off GPIO Array
++WLAN_PWR_CFG rtl8814A_radio_off_flow[RTL8814A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8814A_TRANS_END_STEPS]=
++{
++ RTL8814A_TRANS_ACT_TO_CARDEMU
++ RTL8814A_TRANS_END
++};
++
++//3Card Disable Array
++WLAN_PWR_CFG rtl8814A_card_disable_flow[RTL8814A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8814A_TRANS_CARDEMU_TO_PDN_STEPS+RTL8814A_TRANS_END_STEPS]=
++{
++ RTL8814A_TRANS_ACT_TO_CARDEMU
++ RTL8814A_TRANS_CARDEMU_TO_CARDDIS
++ RTL8814A_TRANS_END
++};
++
++//3 Card Enable Array
++WLAN_PWR_CFG rtl8814A_card_enable_flow[RTL8814A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8814A_TRANS_CARDEMU_TO_PDN_STEPS+RTL8814A_TRANS_END_STEPS]=
++{
++ RTL8814A_TRANS_CARDDIS_TO_CARDEMU
++ RTL8814A_TRANS_CARDEMU_TO_ACT
++ RTL8814A_TRANS_END
++};
++
++//3Suspend Array
++WLAN_PWR_CFG rtl8814A_suspend_flow[RTL8814A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8814A_TRANS_CARDEMU_TO_SUS_STEPS+RTL8814A_TRANS_END_STEPS]=
++{
++ RTL8814A_TRANS_ACT_TO_CARDEMU
++ RTL8814A_TRANS_CARDEMU_TO_SUS
++ RTL8814A_TRANS_END
++};
++
++//3 Resume Array
++WLAN_PWR_CFG rtl8814A_resume_flow[RTL8814A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8814A_TRANS_CARDEMU_TO_SUS_STEPS+RTL8814A_TRANS_END_STEPS]=
++{
++ RTL8814A_TRANS_SUS_TO_CARDEMU
++ RTL8814A_TRANS_CARDEMU_TO_ACT
++ RTL8814A_TRANS_END
++};
++
++
++
++//3HWPDN Array
++WLAN_PWR_CFG rtl8814A_hwpdn_flow[RTL8814A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8814A_TRANS_CARDEMU_TO_PDN_STEPS+RTL8814A_TRANS_END_STEPS]=
++{
++ RTL8814A_TRANS_ACT_TO_CARDEMU
++ RTL8814A_TRANS_CARDEMU_TO_PDN
++ RTL8814A_TRANS_END
++};
++
++//3 Enter LPS
++WLAN_PWR_CFG rtl8814A_enter_lps_flow[RTL8814A_TRANS_ACT_TO_LPS_STEPS+RTL8814A_TRANS_END_STEPS]=
++{
++ //FW behavior
++ RTL8814A_TRANS_ACT_TO_LPS
++ RTL8814A_TRANS_END
++};
++
++//3 Leave LPS
++WLAN_PWR_CFG rtl8814A_leave_lps_flow[RTL8814A_TRANS_LPS_TO_ACT_STEPS+RTL8814A_TRANS_END_STEPS]=
++{
++ //FW behavior
++ RTL8814A_TRANS_LPS_TO_ACT
++ RTL8814A_TRANS_END
++};
++
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/rtl8814a/rtl8814a_cmd.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/rtl8814a/rtl8814a_cmd.c
+--- linux-5.11.4/3rdparty/rtl8812au/hal/rtl8814a/rtl8814a_cmd.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/rtl8814a/rtl8814a_cmd.c 2021-03-07 18:16:17.082957376 +0200
@@ -0,0 +1,1515 @@
+/******************************************************************************
+ *
@@ -354270,11 +350924,9 @@ index 000000000..6aa1fda17
+
+#endif // CONFIG_BT_COEXIST
+
-diff --git linux-5.8/3rdparty/rtl8812au/hal/rtl8814a/rtl8814a_dm.c linux-5.8/3rdparty/rtl8812au/hal/rtl8814a/rtl8814a_dm.c
-new file mode 100644
-index 000000000..10d7c7825
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/rtl8814a/rtl8814a_dm.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/rtl8814a/rtl8814a_dm.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/rtl8814a/rtl8814a_dm.c
+--- linux-5.11.4/3rdparty/rtl8812au/hal/rtl8814a/rtl8814a_dm.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/rtl8814a/rtl8814a_dm.c 2021-03-07 18:16:17.082957376 +0200
@@ -0,0 +1,407 @@
+/******************************************************************************
+ *
@@ -354683,11 +351335,9 @@ index 000000000..10d7c7825
+}
+#endif //CONFIG_ANTENNA_DIVERSITY
+
-diff --git linux-5.8/3rdparty/rtl8812au/hal/rtl8814a/rtl8814a_hal_init.c linux-5.8/3rdparty/rtl8812au/hal/rtl8814a/rtl8814a_hal_init.c
-new file mode 100644
-index 000000000..b93ed3174
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/rtl8814a/rtl8814a_hal_init.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/rtl8814a/rtl8814a_hal_init.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/rtl8814a/rtl8814a_hal_init.c
+--- linux-5.11.4/3rdparty/rtl8812au/hal/rtl8814a/rtl8814a_hal_init.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/rtl8814a/rtl8814a_hal_init.c 2021-03-07 18:16:17.083957423 +0200
@@ -0,0 +1,6769 @@
+/******************************************************************************
+ *
@@ -361458,11 +358108,9 @@ index 000000000..b93ed3174
+}
+
+
-diff --git linux-5.8/3rdparty/rtl8812au/hal/rtl8814a/rtl8814a_phycfg.c linux-5.8/3rdparty/rtl8812au/hal/rtl8814a/rtl8814a_phycfg.c
-new file mode 100644
-index 000000000..1c212540c
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/rtl8814a/rtl8814a_phycfg.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/rtl8814a/rtl8814a_phycfg.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/rtl8814a/rtl8814a_phycfg.c
+--- linux-5.11.4/3rdparty/rtl8812au/hal/rtl8814a/rtl8814a_phycfg.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/rtl8814a/rtl8814a_phycfg.c 2021-03-07 18:16:17.083957423 +0200
@@ -0,0 +1,3027 @@
+/******************************************************************************
+ *
@@ -364491,11 +361139,9 @@ index 000000000..1c212540c
+ //RTW_INFO("<==%s()\n",__FUNCTION__);
+}
+
-diff --git linux-5.8/3rdparty/rtl8812au/hal/rtl8814a/rtl8814a_rf6052.c linux-5.8/3rdparty/rtl8812au/hal/rtl8814a/rtl8814a_rf6052.c
-new file mode 100644
-index 000000000..f298471ad
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/rtl8814a/rtl8814a_rf6052.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/rtl8814a/rtl8814a_rf6052.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/rtl8814a/rtl8814a_rf6052.c
+--- linux-5.11.4/3rdparty/rtl8812au/hal/rtl8814a/rtl8814a_rf6052.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/rtl8814a/rtl8814a_rf6052.c 2021-03-07 18:16:17.083957423 +0200
@@ -0,0 +1,210 @@
+/******************************************************************************
+ *
@@ -364707,11 +361353,9 @@ index 000000000..f298471ad
+
+/* End of HalRf6052.c */
+
-diff --git linux-5.8/3rdparty/rtl8812au/hal/rtl8814a/rtl8814a_rxdesc.c linux-5.8/3rdparty/rtl8812au/hal/rtl8814a/rtl8814a_rxdesc.c
-new file mode 100644
-index 000000000..7de802c6c
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/rtl8814a/rtl8814a_rxdesc.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/rtl8814a/rtl8814a_rxdesc.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/rtl8814a/rtl8814a_rxdesc.c
+--- linux-5.11.4/3rdparty/rtl8812au/hal/rtl8814a/rtl8814a_rxdesc.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/rtl8814a/rtl8814a_rxdesc.c 2021-03-07 18:16:17.083957423 +0200
@@ -0,0 +1,68 @@
+/******************************************************************************
+ *
@@ -364781,11 +361425,9 @@ index 000000000..7de802c6c
+
+}
+
-diff --git linux-5.8/3rdparty/rtl8812au/hal/rtl8814a/rtl8814a_sreset.c linux-5.8/3rdparty/rtl8812au/hal/rtl8814a/rtl8814a_sreset.c
-new file mode 100644
-index 000000000..5d7e423ce
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/rtl8814a/rtl8814a_sreset.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/rtl8814a/rtl8814a_sreset.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/rtl8814a/rtl8814a_sreset.c
+--- linux-5.11.4/3rdparty/rtl8812au/hal/rtl8814a/rtl8814a_sreset.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/rtl8814a/rtl8814a_sreset.c 2021-03-07 18:16:17.083957423 +0200
@@ -0,0 +1,114 @@
+/******************************************************************************
+ *
@@ -364901,11 +361543,9 @@ index 000000000..5d7e423ce
+}
+#endif
+
-diff --git linux-5.8/3rdparty/rtl8812au/hal/rtl8814a/rtl8814a_xmit.c linux-5.8/3rdparty/rtl8812au/hal/rtl8814a/rtl8814a_xmit.c
-new file mode 100644
-index 000000000..8e9047b82
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/rtl8814a/rtl8814a_xmit.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/rtl8814a/rtl8814a_xmit.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/rtl8814a/rtl8814a_xmit.c
+--- linux-5.11.4/3rdparty/rtl8812au/hal/rtl8814a/rtl8814a_xmit.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/rtl8814a/rtl8814a_xmit.c 2021-03-07 18:16:17.083957423 +0200
@@ -0,0 +1,515 @@
+/******************************************************************************
+ *
@@ -365422,11 +362062,9 @@ index 000000000..8e9047b82
+}
+
+
-diff --git linux-5.8/3rdparty/rtl8812au/hal/rtl8814a/usb/rtl8814au_led.c linux-5.8/3rdparty/rtl8812au/hal/rtl8814a/usb/rtl8814au_led.c
-new file mode 100644
-index 000000000..070f886e6
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/rtl8814a/usb/rtl8814au_led.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/rtl8814a/usb/rtl8814au_led.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/rtl8814a/usb/rtl8814au_led.c
+--- linux-5.11.4/3rdparty/rtl8812au/hal/rtl8814a/usb/rtl8814au_led.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/rtl8814a/usb/rtl8814au_led.c 2021-03-07 18:16:17.083957423 +0200
@@ -0,0 +1,147 @@
+/******************************************************************************
+ *
@@ -365575,11 +362213,9 @@ index 000000000..070f886e6
+ DeInitLed( &(ledpriv->SwLed2) );
+}
+#endif
-diff --git linux-5.8/3rdparty/rtl8812au/hal/rtl8814a/usb/rtl8814au_recv.c linux-5.8/3rdparty/rtl8812au/hal/rtl8814a/usb/rtl8814au_recv.c
-new file mode 100644
-index 000000000..4d381791b
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/rtl8814a/usb/rtl8814au_recv.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/rtl8814a/usb/rtl8814au_recv.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/rtl8814a/usb/rtl8814au_recv.c
+--- linux-5.11.4/3rdparty/rtl8812au/hal/rtl8814a/usb/rtl8814au_recv.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/rtl8814a/usb/rtl8814au_recv.c 2021-03-07 18:16:17.083957423 +0200
@@ -0,0 +1,34 @@
+/******************************************************************************
+ *
@@ -365615,11 +362251,9 @@ index 000000000..4d381791b
+ usb_free_recv_priv(padapter, INTERRUPT_MSG_FORMAT_LEN);
+}
+
-diff --git linux-5.8/3rdparty/rtl8812au/hal/rtl8814a/usb/rtl8814au_xmit.c linux-5.8/3rdparty/rtl8812au/hal/rtl8814a/usb/rtl8814au_xmit.c
-new file mode 100644
-index 000000000..482040b57
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/rtl8814a/usb/rtl8814au_xmit.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/rtl8814a/usb/rtl8814au_xmit.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/rtl8814a/usb/rtl8814au_xmit.c
+--- linux-5.11.4/3rdparty/rtl8812au/hal/rtl8814a/usb/rtl8814au_xmit.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/rtl8814a/usb/rtl8814au_xmit.c 2021-03-07 18:16:17.083957423 +0200
@@ -0,0 +1,1129 @@
+/******************************************************************************
+ *
@@ -366750,11 +363384,9 @@ index 000000000..482040b57
+}
+#endif
+
-diff --git linux-5.8/3rdparty/rtl8812au/hal/rtl8814a/usb/usb_halinit.c linux-5.8/3rdparty/rtl8812au/hal/rtl8814a/usb/usb_halinit.c
-new file mode 100644
-index 000000000..5c0bf0d03
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/rtl8814a/usb/usb_halinit.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/rtl8814a/usb/usb_halinit.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/rtl8814a/usb/usb_halinit.c
+--- linux-5.11.4/3rdparty/rtl8812au/hal/rtl8814a/usb/usb_halinit.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/rtl8814a/usb/usb_halinit.c 2021-03-07 18:16:17.083957423 +0200
@@ -0,0 +1,2416 @@
+/******************************************************************************
+ *
@@ -369172,11 +365804,9 @@ index 000000000..5c0bf0d03
+
+}
+
-diff --git linux-5.8/3rdparty/rtl8812au/hal/rtl8814a/usb/usb_ops_linux.c linux-5.8/3rdparty/rtl8812au/hal/rtl8814a/usb/usb_ops_linux.c
-new file mode 100644
-index 000000000..320024cae
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/hal/rtl8814a/usb/usb_ops_linux.c
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/hal/rtl8814a/usb/usb_ops_linux.c linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/rtl8814a/usb/usb_ops_linux.c
+--- linux-5.11.4/3rdparty/rtl8812au/hal/rtl8814a/usb/usb_ops_linux.c 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/hal/rtl8814a/usb/usb_ops_linux.c 2021-03-07 18:16:17.083957423 +0200
@@ -0,0 +1,312 @@
+/******************************************************************************
+ *
@@ -369490,3040 +366120,9 @@ index 000000000..320024cae
+ pdvobj->HardwareType = HARDWARE_TYPE_RTL8814AU;
+ RTW_INFO("CHIP TYPE: RTL8814\n");
+}
-diff --git linux-5.8/3rdparty/rtl8812au/include/Hal8812PhyCfg.h linux-5.8/3rdparty/rtl8812au/include/Hal8812PhyCfg.h
-new file mode 100644
-index 000000000..0d5282a42
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/include/Hal8812PhyCfg.h
-@@ -0,0 +1,143 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __INC_HAL8812PHYCFG_H__
-+#define __INC_HAL8812PHYCFG_H__
-+
-+
-+/*--------------------------Define Parameters-------------------------------*/
-+#define LOOP_LIMIT 5
-+#define MAX_STALL_TIME 50 /* us */
-+#define AntennaDiversityValue 0x80 /* (Adapter->bSoftwareAntennaDiversity ? 0x00 : 0x80) */
-+#define MAX_TXPWR_IDX_NMODE_92S 63
-+#define Reset_Cnt_Limit 3
-+
-+
-+#ifdef CONFIG_PCI_HCI
-+ #define MAX_AGGR_NUM 0x0B
-+#else
-+ #define MAX_AGGR_NUM 0x07
-+#endif /* CONFIG_PCI_HCI */
-+
-+
-+/*--------------------------Define Parameters-------------------------------*/
-+
-+/*------------------------------Define structure----------------------------*/
-+
-+
-+/* BB/RF related */
-+
-+/*------------------------------Define structure----------------------------*/
-+
-+
-+/*------------------------Export global variable----------------------------*/
-+/*------------------------Export global variable----------------------------*/
-+
-+
-+/*------------------------Export Marco Definition---------------------------*/
-+/*------------------------Export Marco Definition---------------------------*/
-+
-+
-+/*--------------------------Exported Function prototype---------------------*/
-+/*
-+ * BB and RF register read/write
-+ * */
-+u32 PHY_QueryBBReg8812(IN PADAPTER Adapter,
-+ IN u32 RegAddr,
-+ IN u32 BitMask);
-+void PHY_SetBBReg8812(IN PADAPTER Adapter,
-+ IN u32 RegAddr,
-+ IN u32 BitMask,
-+ IN u32 Data);
-+u32 PHY_QueryRFReg8812(IN PADAPTER Adapter,
-+ IN enum rf_path eRFPath,
-+ IN u32 RegAddr,
-+ IN u32 BitMask);
-+void PHY_SetRFReg8812(IN PADAPTER Adapter,
-+ IN enum rf_path eRFPath,
-+ IN u32 RegAddr,
-+ IN u32 BitMask,
-+ IN u32 Data);
-+
-+/*
-+ * Initialization related function
-+ *
-+ * MAC/BB/RF HAL config */
-+int PHY_MACConfig8812(IN PADAPTER Adapter);
-+int PHY_BBConfig8812(IN PADAPTER Adapter);
-+void PHY_BB8812_Config_1T(IN PADAPTER Adapter);
-+int PHY_RFConfig8812(IN PADAPTER Adapter);
-+
-+/* RF config */
-+
-+s32
-+PHY_SwitchWirelessBand8812(
-+ IN PADAPTER Adapter,
-+ IN u8 Band
-+);
-+
-+/*
-+ * BB TX Power R/W
-+ * */
-+void PHY_GetTxPowerLevel8812(IN PADAPTER Adapter, OUT s32 *powerlevel);
-+void PHY_SetTxPowerLevel8812(IN PADAPTER Adapter, IN u8 Channel);
-+
-+BOOLEAN PHY_UpdateTxPowerDbm8812(IN PADAPTER Adapter, IN int powerInDbm);
-+u8 PHY_GetTxPowerIndex_8812A(
-+ IN PADAPTER pAdapter,
-+ IN enum rf_path RFPath,
-+ IN u8 Rate,
-+ IN u8 BandWidth,
-+ IN u8 Channel,
-+ struct txpwr_idx_comp *tic
-+);
-+
-+u32 phy_get_tx_bb_swing_8812a(
-+ IN PADAPTER Adapter,
-+ IN BAND_TYPE Band,
-+ IN enum rf_path RFPath
-+);
-+
-+VOID
-+PHY_SetTxPowerIndex_8812A(
-+ IN PADAPTER Adapter,
-+ IN u32 PowerIndex,
-+ IN enum rf_path RFPath,
-+ IN u8 Rate
-+);
-+
-+/*
-+ * channel switch related funciton
-+ * */
-+VOID
-+PHY_SetSwChnlBWMode8812(
-+ IN PADAPTER Adapter,
-+ IN u8 channel,
-+ IN enum channel_width Bandwidth,
-+ IN u8 Offset40,
-+ IN u8 Offset80
-+);
-+
-+/*
-+ * BB/MAC/RF other monitor API
-+ * */
-+
-+VOID
-+phy_set_rf_path_switch_8812a(
-+ IN struct dm_struct *phydm,
-+ IN bool bMain
-+);
-+
-+/*--------------------------Exported Function prototype---------------------*/
-+#endif /* __INC_HAL8192CPHYCFG_H */
-diff --git linux-5.8/3rdparty/rtl8812au/include/Hal8812PhyReg.h linux-5.8/3rdparty/rtl8812au/include/Hal8812PhyReg.h
-new file mode 100644
-index 000000000..521ebb202
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/include/Hal8812PhyReg.h
-@@ -0,0 +1,735 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __INC_HAL8812PHYREG_H__
-+#define __INC_HAL8812PHYREG_H__
-+/*--------------------------Define Parameters-------------------------------*/
-+/*
-+ * BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF
-+ * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF
-+ * 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00
-+ * 3. RF register 0x00-2E
-+ * 4. Bit Mask for BB/RF register
-+ * 5. Other defintion for BB/RF R/W
-+ * */
-+
-+
-+/* BB Register Definition */
-+
-+#define rCCAonSec_Jaguar 0x838
-+#define rPwed_TH_Jaguar 0x830
-+
-+/* BW and sideband setting */
-+#define rBWIndication_Jaguar 0x834
-+#define rL1PeakTH_Jaguar 0x848
-+#define rFPGA0_XA_LSSIReadBack 0x8a0 /*Tranceiver LSSI Readback*/
-+#define rRFMOD_Jaguar 0x8ac /* RF mode */
-+#define rADC_Buf_Clk_Jaguar 0x8c4
-+#define rRFECTRL_Jaguar 0x900
-+#define bRFMOD_Jaguar 0xc3
-+#define rCCK_System_Jaguar 0xa00 /* for cck sideband */
-+#define bCCK_System_Jaguar 0x10
-+
-+/* Block & Path enable */
-+#define rOFDMCCKEN_Jaguar 0x808 /* OFDM/CCK block enable */
-+#define bOFDMEN_Jaguar 0x20000000
-+#define bCCKEN_Jaguar 0x10000000
-+#define rRxPath_Jaguar 0x808 /* Rx antenna */
-+#define bRxPath_Jaguar 0xff
-+#define rTxPath_Jaguar 0x80c /* Tx antenna */
-+#define bTxPath_Jaguar 0x0fffffff
-+#define rCCK_RX_Jaguar 0xa04 /* for cck rx path selection */
-+#define bCCK_RX_Jaguar 0x0c000000
-+#define rVhtlen_Use_Lsig_Jaguar 0x8c3 /* Use LSIG for VHT length */
-+
-+/* RF read/write-related */
-+#define rHSSIRead_Jaguar 0x8b0 /* RF read addr */
-+#define bHSSIRead_addr_Jaguar 0xff
-+#define bHSSIRead_trigger_Jaguar 0x100
-+#define rA_PIRead_Jaguar 0xd04 /* RF readback with PI */
-+#define rB_PIRead_Jaguar 0xd44 /* RF readback with PI */
-+#define rA_SIRead_Jaguar 0xd08 /* RF readback with SI */
-+#define rB_SIRead_Jaguar 0xd48 /* RF readback with SI */
-+#define rRead_data_Jaguar 0xfffff
-+#define rA_LSSIWrite_Jaguar 0xc90 /* RF write addr */
-+#define rB_LSSIWrite_Jaguar 0xe90 /* RF write addr */
-+#define bLSSIWrite_data_Jaguar 0x000fffff
-+#define bLSSIWrite_addr_Jaguar 0x0ff00000
-+
-+
-+
-+/* YN: mask the following register definition temporarily */
-+#define rFPGA0_XA_RFInterfaceOE 0x860 /* RF Channel switch */
-+#define rFPGA0_XB_RFInterfaceOE 0x864
-+
-+#define rFPGA0_XAB_RFInterfaceSW 0x870 /* RF Interface Software Control */
-+#define rFPGA0_XCD_RFInterfaceSW 0x874
-+
-+/* #define rFPGA0_XAB_RFParameter 0x878 */ /* RF Parameter
-+ * #define rFPGA0_XCD_RFParameter 0x87c */
-+
-+/* #define rFPGA0_AnalogParameter1 0x880 */ /* Crystal cap setting RF-R/W protection for parameter4??
-+ * #define rFPGA0_AnalogParameter2 0x884
-+ * #define rFPGA0_AnalogParameter3 0x888
-+ * #define rFPGA0_AdDaClockEn 0x888 */ /* enable ad/da clock1 for dual-phy
-+ * #define rFPGA0_AnalogParameter4 0x88c */
-+
-+
-+/* CCK TX scaling */
-+#define rCCK_TxFilter1_Jaguar 0xa20
-+#define bCCK_TxFilter1_C0_Jaguar 0x00ff0000
-+#define bCCK_TxFilter1_C1_Jaguar 0xff000000
-+#define rCCK_TxFilter2_Jaguar 0xa24
-+#define bCCK_TxFilter2_C2_Jaguar 0x000000ff
-+#define bCCK_TxFilter2_C3_Jaguar 0x0000ff00
-+#define bCCK_TxFilter2_C4_Jaguar 0x00ff0000
-+#define bCCK_TxFilter2_C5_Jaguar 0xff000000
-+#define rCCK_TxFilter3_Jaguar 0xa28
-+#define bCCK_TxFilter3_C6_Jaguar 0x000000ff
-+#define bCCK_TxFilter3_C7_Jaguar 0x0000ff00
-+
-+
-+/* YN: mask the following register definition temporarily
-+ * #define rPdp_AntA 0xb00
-+ * #define rPdp_AntA_4 0xb04
-+ * #define rConfig_Pmpd_AntA 0xb28
-+ * #define rConfig_AntA 0xb68
-+ * #define rConfig_AntB 0xb6c
-+ * #define rPdp_AntB 0xb70
-+ * #define rPdp_AntB_4 0xb74
-+ * #define rConfig_Pmpd_AntB 0xb98
-+ * #define rAPK 0xbd8 */
-+
-+/* RXIQC */
-+#define rA_RxIQC_AB_Jaguar 0xc10 /* RxIQ imblance matrix coeff. A & B */
-+#define rA_RxIQC_CD_Jaguar 0xc14 /* RxIQ imblance matrix coeff. C & D */
-+#define rA_TxScale_Jaguar 0xc1c /* Pah_A TX scaling factor */
-+#define rB_TxScale_Jaguar 0xe1c /* Path_B TX scaling factor */
-+#define rB_RxIQC_AB_Jaguar 0xe10 /* RxIQ imblance matrix coeff. A & B */
-+#define rB_RxIQC_CD_Jaguar 0xe14 /* RxIQ imblance matrix coeff. C & D */
-+#define b_RxIQC_AC_Jaguar 0x02ff /* bit mask for IQC matrix element A & C */
-+#define b_RxIQC_BD_Jaguar 0x02ff0000 /* bit mask for IQC matrix element A & C */
-+
-+
-+/* DIG-related */
-+#define rA_IGI_Jaguar 0xc50 /* Initial Gain for path-A */
-+#define rB_IGI_Jaguar 0xe50 /* Initial Gain for path-B */
-+#define rOFDM_FalseAlarm1_Jaguar 0xf48 /* counter for break */
-+#define rOFDM_FalseAlarm2_Jaguar 0xf4c /* counter for spoofing */
-+#define rCCK_FalseAlarm_Jaguar 0xa5c /* counter for cck false alarm */
-+#define b_FalseAlarm_Jaguar 0xffff
-+#define rCCK_CCA_Jaguar 0xa08 /* cca threshold */
-+#define bCCK_CCA_Jaguar 0x00ff0000
-+
-+/* Tx Power Ttraining-related */
-+#define rA_TxPwrTraing_Jaguar 0xc54
-+#define rB_TxPwrTraing_Jaguar 0xe54
-+
-+/* Report-related */
-+#define rOFDM_ShortCFOAB_Jaguar 0xf60
-+#define rOFDM_LongCFOAB_Jaguar 0xf64
-+#define rOFDM_EndCFOAB_Jaguar 0xf70
-+#define rOFDM_AGCReport_Jaguar 0xf84
-+#define rOFDM_RxSNR_Jaguar 0xf88
-+#define rOFDM_RxEVMCSI_Jaguar 0xf8c
-+#define rOFDM_SIGReport_Jaguar 0xf90
-+
-+/* Misc functions */
-+#define rEDCCA_Jaguar 0x8a4 /* EDCCA */
-+#define bEDCCA_Jaguar 0xffff
-+#define rAGC_table_Jaguar 0x82c /* AGC tabel select */
-+#define bAGC_table_Jaguar 0x3
-+#define b_sel5g_Jaguar 0x1000 /* sel5g */
-+#define b_LNA_sw_Jaguar 0x8000 /* HW/WS control for LNA */
-+#define rFc_area_Jaguar 0x860 /* fc_area */
-+#define bFc_area_Jaguar 0x1ffe000
-+#define rSingleTone_ContTx_Jaguar 0x914
-+
-+/* RFE */
-+#define rA_RFE_Pinmux_Jaguar 0xcb0 /* Path_A RFE cotrol pinmux */
-+#define rB_RFE_Pinmux_Jaguar 0xeb0 /* Path_B RFE control pinmux */
-+#define rA_RFE_Inv_Jaguar 0xcb4 /* Path_A RFE cotrol */
-+#define rB_RFE_Inv_Jaguar 0xeb4 /* Path_B RFE control */
-+#define rA_RFE_Jaguar 0xcb8 /* Path_A RFE cotrol */
-+#define rB_RFE_Jaguar 0xeb8 /* Path_B RFE control */
-+#define rA_RFE_Inverse_Jaguar 0xCBC /* Path_A RFE control inverse */
-+#define rB_RFE_Inverse_Jaguar 0xEBC /* Path_B RFE control inverse */
-+#define r_ANTSEL_SW_Jaguar 0x900 /* ANTSEL SW Control */
-+#define bMask_RFEInv_Jaguar 0x3ff00000
-+#define bMask_AntselPathFollow_Jaguar 0x00030000
-+
-+/* TX AGC */
-+#define rTxAGC_A_CCK11_CCK1_JAguar 0xc20
-+#define rTxAGC_A_Ofdm18_Ofdm6_JAguar 0xc24
-+#define rTxAGC_A_Ofdm54_Ofdm24_JAguar 0xc28
-+#define rTxAGC_A_MCS3_MCS0_JAguar 0xc2c
-+#define rTxAGC_A_MCS7_MCS4_JAguar 0xc30
-+#define rTxAGC_A_MCS11_MCS8_JAguar 0xc34
-+#define rTxAGC_A_MCS15_MCS12_JAguar 0xc38
-+#define rTxAGC_A_Nss1Index3_Nss1Index0_JAguar 0xc3c
-+#define rTxAGC_A_Nss1Index7_Nss1Index4_JAguar 0xc40
-+#define rTxAGC_A_Nss2Index1_Nss1Index8_JAguar 0xc44
-+#define rTxAGC_A_Nss2Index5_Nss2Index2_JAguar 0xc48
-+#define rTxAGC_A_Nss2Index9_Nss2Index6_JAguar 0xc4c
-+#define rTxAGC_B_CCK11_CCK1_JAguar 0xe20
-+#define rTxAGC_B_Ofdm18_Ofdm6_JAguar 0xe24
-+#define rTxAGC_B_Ofdm54_Ofdm24_JAguar 0xe28
-+#define rTxAGC_B_MCS3_MCS0_JAguar 0xe2c
-+#define rTxAGC_B_MCS7_MCS4_JAguar 0xe30
-+#define rTxAGC_B_MCS11_MCS8_JAguar 0xe34
-+#define rTxAGC_B_MCS15_MCS12_JAguar 0xe38
-+#define rTxAGC_B_Nss1Index3_Nss1Index0_JAguar 0xe3c
-+#define rTxAGC_B_Nss1Index7_Nss1Index4_JAguar 0xe40
-+#define rTxAGC_B_Nss2Index1_Nss1Index8_JAguar 0xe44
-+#define rTxAGC_B_Nss2Index5_Nss2Index2_JAguar 0xe48
-+#define rTxAGC_B_Nss2Index9_Nss2Index6_JAguar 0xe4c
-+#define bTxAGC_byte0_Jaguar 0xff
-+#define bTxAGC_byte1_Jaguar 0xff00
-+#define bTxAGC_byte2_Jaguar 0xff0000
-+#define bTxAGC_byte3_Jaguar 0xff000000
-+
-+/* IQK YN: temporaily mask this part
-+ * #define rFPGA0_IQK 0xe28
-+ * #define rTx_IQK_Tone_A 0xe30
-+ * #define rRx_IQK_Tone_A 0xe34
-+ * #define rTx_IQK_PI_A 0xe38
-+ * #define rRx_IQK_PI_A 0xe3c */
-+
-+/* #define rTx_IQK 0xe40 */
-+/* #define rRx_IQK 0xe44 */
-+/* #define rIQK_AGC_Pts 0xe48 */
-+/* #define rIQK_AGC_Rsp 0xe4c */
-+/* #define rTx_IQK_Tone_B 0xe50 */
-+/* #define rRx_IQK_Tone_B 0xe54 */
-+/* #define rTx_IQK_PI_B 0xe58 */
-+/* #define rRx_IQK_PI_B 0xe5c */
-+/* #define rIQK_AGC_Cont 0xe60 */
-+
-+
-+/* AFE-related */
-+#define rA_AFEPwr1_Jaguar 0xc60 /* dynamic AFE power control */
-+#define rA_AFEPwr2_Jaguar 0xc64 /* dynamic AFE power control */
-+#define rA_Rx_WaitCCA_Tx_CCKRFON_Jaguar 0xc68
-+#define rA_Tx_CCKBBON_OFDMRFON_Jaguar 0xc6c
-+#define rA_Tx_OFDMBBON_Tx2Rx_Jaguar 0xc70
-+#define rA_Tx2Tx_RXCCK_Jaguar 0xc74
-+#define rA_Rx_OFDM_WaitRIFS_Jaguar 0xc78
-+#define rA_Rx2Rx_BT_Jaguar 0xc7c
-+#define rA_sleep_nav_Jaguar 0xc80
-+#define rA_pmpd_Jaguar 0xc84
-+#define rB_AFEPwr1_Jaguar 0xe60 /* dynamic AFE power control */
-+#define rB_AFEPwr2_Jaguar 0xe64 /* dynamic AFE power control */
-+#define rB_Rx_WaitCCA_Tx_CCKRFON_Jaguar 0xe68
-+#define rB_Tx_CCKBBON_OFDMRFON_Jaguar 0xe6c
-+#define rB_Tx_OFDMBBON_Tx2Rx_Jaguar 0xe70
-+#define rB_Tx2Tx_RXCCK_Jaguar 0xe74
-+#define rB_Rx_OFDM_WaitRIFS_Jaguar 0xe78
-+#define rB_Rx2Rx_BT_Jaguar 0xe7c
-+#define rB_sleep_nav_Jaguar 0xe80
-+#define rB_pmpd_Jaguar 0xe84
-+
-+
-+/* YN: mask these registers temporaily
-+ * #define rTx_Power_Before_IQK_A 0xe94
-+ * #define rTx_Power_After_IQK_A 0xe9c */
-+
-+/* #define rRx_Power_Before_IQK_A 0xea0 */
-+/* #define rRx_Power_Before_IQK_A_2 0xea4 */
-+/* #define rRx_Power_After_IQK_A 0xea8 */
-+/* #define rRx_Power_After_IQK_A_2 0xeac */
-+
-+/* #define rTx_Power_Before_IQK_B 0xeb4 */
-+/* #define rTx_Power_After_IQK_B 0xebc */
-+
-+/* #define rRx_Power_Before_IQK_B 0xec0 */
-+/* #define rRx_Power_Before_IQK_B_2 0xec4 */
-+/* #define rRx_Power_After_IQK_B 0xec8 */
-+/* #define rRx_Power_After_IQK_B_2 0xecc */
-+
-+
-+/* RSSI Dump */
-+#define rA_RSSIDump_Jaguar 0xBF0
-+#define rB_RSSIDump_Jaguar 0xBF1
-+#define rS1_RXevmDump_Jaguar 0xBF4
-+#define rS2_RXevmDump_Jaguar 0xBF5
-+#define rA_RXsnrDump_Jaguar 0xBF6
-+#define rB_RXsnrDump_Jaguar 0xBF7
-+#define rA_CfoShortDump_Jaguar 0xBF8
-+#define rB_CfoShortDump_Jaguar 0xBFA
-+#define rA_CfoLongDump_Jaguar 0xBEC
-+#define rB_CfoLongDump_Jaguar 0xBEE
-+
-+
-+/* RF Register
-+ * */
-+#define RF_AC_Jaguar 0x00 /* */
-+#define RF_RF_Top_Jaguar 0x07 /* */
-+#define RF_TXLOK_Jaguar 0x08 /* */
-+#define RF_TXAPK_Jaguar 0x0B
-+#define RF_CHNLBW_Jaguar 0x18 /* RF channel and BW switch */
-+#define RF_RCK1_Jaguar 0x1c /* */
-+#define RF_RCK2_Jaguar 0x1d
-+#define RF_RCK3_Jaguar 0x1e
-+#define RF_ModeTableAddr 0x30
-+#define RF_ModeTableData0 0x31
-+#define RF_ModeTableData1 0x32
-+#define RF_TxLCTank_Jaguar 0x54
-+#define RF_APK_Jaguar 0x63
-+#define RF_LCK 0xB4
-+#define RF_WeLut_Jaguar 0xEF
-+
-+#define bRF_CHNLBW_MOD_AG_Jaguar 0x70300
-+#define bRF_CHNLBW_BW 0xc00
-+
-+
-+/*
-+ * RL6052 Register definition
-+ * */
-+#define RF_AC 0x00 /* */
-+#define RF_IPA_A 0x0C /* */
-+#define RF_TXBIAS_A 0x0D
-+#define RF_BS_PA_APSET_G9_G11 0x0E
-+#define RF_MODE1 0x10 /* */
-+#define RF_MODE2 0x11 /* */
-+#define RF_CHNLBW 0x18 /* RF channel and BW switch */
-+#define RF_RCK_OS 0x30 /* RF TX PA control */
-+#define RF_TXPA_G1 0x31 /* RF TX PA control */
-+#define RF_TXPA_G2 0x32 /* RF TX PA control */
-+#define RF_TXPA_G3 0x33 /* RF TX PA control */
-+#define RF_0x52 0x52
-+#define RF_WE_LUT 0xEF
-+
-+#define RF_TX_GAIN_OFFSET_8812A(_val) ((abs((_val)) << 1) | (((_val) > 0) ? BIT0 : 0))
-+#define RF_TX_GAIN_OFFSET_8821A(_val) ((abs((_val)) << 1) | (((_val) > 0) ? BIT0 : 0))
-+
-+/*
-+ * Bit Mask
-+ *
-+ * 1. Page1(0x100) */
-+#define bBBResetB 0x100 /* Useless now? */
-+#define bGlobalResetB 0x200
-+#define bOFDMTxStart 0x4
-+#define bCCKTxStart 0x8
-+#define bCRC32Debug 0x100
-+#define bPMACLoopback 0x10
-+#define bTxLSIG 0xffffff
-+#define bOFDMTxRate 0xf
-+#define bOFDMTxReserved 0x10
-+#define bOFDMTxLength 0x1ffe0
-+#define bOFDMTxParity 0x20000
-+#define bTxHTSIG1 0xffffff
-+#define bTxHTMCSRate 0x7f
-+#define bTxHTBW 0x80
-+#define bTxHTLength 0xffff00
-+#define bTxHTSIG2 0xffffff
-+#define bTxHTSmoothing 0x1
-+#define bTxHTSounding 0x2
-+#define bTxHTReserved 0x4
-+#define bTxHTAggreation 0x8
-+#define bTxHTSTBC 0x30
-+#define bTxHTAdvanceCoding 0x40
-+#define bTxHTShortGI 0x80
-+#define bTxHTNumberHT_LTF 0x300
-+#define bTxHTCRC8 0x3fc00
-+#define bCounterReset 0x10000
-+#define bNumOfOFDMTx 0xffff
-+#define bNumOfCCKTx 0xffff0000
-+#define bTxIdleInterval 0xffff
-+#define bOFDMService 0xffff0000
-+#define bTxMACHeader 0xffffffff
-+#define bTxDataInit 0xff
-+#define bTxHTMode 0x100
-+#define bTxDataType 0x30000
-+#define bTxRandomSeed 0xffffffff
-+#define bCCKTxPreamble 0x1
-+#define bCCKTxSFD 0xffff0000
-+#define bCCKTxSIG 0xff
-+#define bCCKTxService 0xff00
-+#define bCCKLengthExt 0x8000
-+#define bCCKTxLength 0xffff0000
-+#define bCCKTxCRC16 0xffff
-+#define bCCKTxStatus 0x1
-+#define bOFDMTxStatus 0x2
-+
-+
-+/*
-+ * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF
-+ * 1. Page1(0x100)
-+ * */
-+#define rPMAC_Reset 0x100
-+#define rPMAC_TxStart 0x104
-+#define rPMAC_TxLegacySIG 0x108
-+#define rPMAC_TxHTSIG1 0x10c
-+#define rPMAC_TxHTSIG2 0x110
-+#define rPMAC_PHYDebug 0x114
-+#define rPMAC_TxPacketNum 0x118
-+#define rPMAC_TxIdle 0x11c
-+#define rPMAC_TxMACHeader0 0x120
-+#define rPMAC_TxMACHeader1 0x124
-+#define rPMAC_TxMACHeader2 0x128
-+#define rPMAC_TxMACHeader3 0x12c
-+#define rPMAC_TxMACHeader4 0x130
-+#define rPMAC_TxMACHeader5 0x134
-+#define rPMAC_TxDataType 0x138
-+#define rPMAC_TxRandomSeed 0x13c
-+#define rPMAC_CCKPLCPPreamble 0x140
-+#define rPMAC_CCKPLCPHeader 0x144
-+#define rPMAC_CCKCRC16 0x148
-+#define rPMAC_OFDMRxCRC32OK 0x170
-+#define rPMAC_OFDMRxCRC32Er 0x174
-+#define rPMAC_OFDMRxParityEr 0x178
-+#define rPMAC_OFDMRxCRC8Er 0x17c
-+#define rPMAC_CCKCRxRC16Er 0x180
-+#define rPMAC_CCKCRxRC32Er 0x184
-+#define rPMAC_CCKCRxRC32OK 0x188
-+#define rPMAC_TxStatus 0x18c
-+
-+/*
-+ * 3. Page8(0x800)
-+ * */
-+#define rFPGA0_RFMOD 0x800 /* RF mode & CCK TxSC */ /* RF BW Setting?? */
-+
-+#define rFPGA0_TxInfo 0x804 /* Status report?? */
-+#define rFPGA0_PSDFunction 0x808
-+#define rFPGA0_TxGainStage 0x80c /* Set TX PWR init gain? */
-+
-+#define rFPGA0_XA_HSSIParameter1 0x820 /* RF 3 wire register */
-+#define rFPGA0_XA_HSSIParameter2 0x824
-+#define rFPGA0_XB_HSSIParameter1 0x828
-+#define rFPGA0_XB_HSSIParameter2 0x82c
-+
-+#define rFPGA0_XAB_SwitchControl 0x858 /* RF Channel switch */
-+#define rFPGA0_XCD_SwitchControl 0x85c
-+
-+#define rFPGA0_XAB_RFParameter 0x878 /* RF Parameter */
-+#define rFPGA0_XCD_RFParameter 0x87c
-+
-+#define rFPGA0_AnalogParameter1 0x880 /* Crystal cap setting RF-R/W protection for parameter4?? */
-+#define rFPGA0_AnalogParameter2 0x884
-+#define rFPGA0_AnalogParameter3 0x888
-+#define rFPGA0_AdDaClockEn 0x888 /* enable ad/da clock1 for dual-phy */
-+#define rFPGA0_AnalogParameter4 0x88c
-+#define rFPGA0_XB_LSSIReadBack 0x8a4
-+#define rFPGA0_XCD_RFPara 0x8b4
-+
-+/*
-+ * 4. Page9(0x900)
-+ * */
-+#define rFPGA1_RFMOD 0x900 /* RF mode & OFDM TxSC */ /* RF BW Setting?? */
-+
-+#define rFPGA1_TxBlock 0x904 /* Useless now */
-+#define rFPGA1_DebugSelect 0x908 /* Useless now */
-+#define rFPGA1_TxInfo 0x90c /* Useless now */ /* Status report?? */
-+
-+/*
-+ * PageA(0xA00)
-+ * */
-+#define rCCK0_System 0xa00
-+#define rCCK0_AFESetting 0xa04 /* Disable init gain now */ /* Select RX path by RSSI */
-+#define rCCK0_DSPParameter2 0xa1c /* SQ threshold */
-+#define rCCK0_TxFilter1 0xa20
-+#define rCCK0_TxFilter2 0xa24
-+#define rCCK0_DebugPort 0xa28 /* debug port and Tx filter3 */
-+#define rCCK0_FalseAlarmReport 0xa2c /* 0xa2d useless now 0xa30-a4f channel report */
-+
-+/*
-+ * PageB(0xB00)
-+ * */
-+#define rPdp_AntA 0xb00
-+#define rPdp_AntA_4 0xb04
-+#define rConfig_Pmpd_AntA 0xb28
-+#define rConfig_AntA 0xb68
-+#define rConfig_AntB 0xb6c
-+#define rPdp_AntB 0xb70
-+#define rPdp_AntB_4 0xb74
-+#define rConfig_Pmpd_AntB 0xb98
-+#define rAPK 0xbd8
-+
-+/*
-+ * 6. PageC(0xC00)
-+ * */
-+#define rOFDM0_LSTF 0xc00
-+
-+#define rOFDM0_TRxPathEnable 0xc04
-+#define rOFDM0_TRMuxPar 0xc08
-+#define rOFDM0_TRSWIsolation 0xc0c
-+
-+#define rOFDM0_XARxAFE 0xc10 /* RxIQ DC offset, Rx digital filter, DC notch filter */
-+#define rOFDM0_XARxIQImbalance 0xc14 /* RxIQ imblance matrix */
-+#define rOFDM0_XBRxAFE 0xc18
-+#define rOFDM0_XBRxIQImbalance 0xc1c
-+#define rOFDM0_XCRxAFE 0xc20
-+#define rOFDM0_XCRxIQImbalance 0xc24
-+#define rOFDM0_XDRxAFE 0xc28
-+#define rOFDM0_XDRxIQImbalance 0xc2c
-+
-+#define rOFDM0_RxDetector1 0xc30 /* PD, BW & SBD */ /* DM tune init gain */
-+#define rOFDM0_RxDetector2 0xc34 /* SBD & Fame Sync. */
-+#define rOFDM0_RxDetector3 0xc38 /* Frame Sync. */
-+#define rOFDM0_RxDetector4 0xc3c /* PD, SBD, Frame Sync & Short-GI */
-+
-+#define rOFDM0_RxDSP 0xc40 /* Rx Sync Path */
-+#define rOFDM0_CFOandDAGC 0xc44 /* CFO & DAGC */
-+#define rOFDM0_CCADropThreshold 0xc48 /* CCA Drop threshold */
-+#define rOFDM0_ECCAThreshold 0xc4c /* energy CCA */
-+
-+#define rOFDM0_XAAGCCore1 0xc50 /* DIG */
-+#define rOFDM0_XAAGCCore2 0xc54
-+#define rOFDM0_XBAGCCore1 0xc58
-+#define rOFDM0_XBAGCCore2 0xc5c
-+#define rOFDM0_XCAGCCore1 0xc60
-+#define rOFDM0_XCAGCCore2 0xc64
-+#define rOFDM0_XDAGCCore1 0xc68
-+#define rOFDM0_XDAGCCore2 0xc6c
-+
-+#define rOFDM0_AGCParameter1 0xc70
-+#define rOFDM0_AGCParameter2 0xc74
-+#define rOFDM0_AGCRSSITable 0xc78
-+#define rOFDM0_HTSTFAGC 0xc7c
-+
-+#define rOFDM0_XATxIQImbalance 0xc80 /* TX PWR TRACK and DIG */
-+#define rOFDM0_XATxAFE 0xc84
-+#define rOFDM0_XBTxIQImbalance 0xc88
-+#define rOFDM0_XBTxAFE 0xc8c
-+#define rOFDM0_XCTxIQImbalance 0xc90
-+#define rOFDM0_XCTxAFE 0xc94
-+#define rOFDM0_XDTxIQImbalance 0xc98
-+#define rOFDM0_XDTxAFE 0xc9c
-+
-+#define rOFDM0_RxIQExtAnta 0xca0
-+#define rOFDM0_TxCoeff1 0xca4
-+#define rOFDM0_TxCoeff2 0xca8
-+#define rOFDM0_TxCoeff3 0xcac
-+#define rOFDM0_TxCoeff4 0xcb0
-+#define rOFDM0_TxCoeff5 0xcb4
-+#define rOFDM0_TxCoeff6 0xcb8
-+#define rOFDM0_RxHPParameter 0xce0
-+#define rOFDM0_TxPseudoNoiseWgt 0xce4
-+#define rOFDM0_FrameSync 0xcf0
-+#define rOFDM0_DFSReport 0xcf4
-+
-+/*
-+ * 7. PageD(0xD00)
-+ * */
-+#define rOFDM1_LSTF 0xd00
-+#define rOFDM1_TRxPathEnable 0xd04
-+
-+/*
-+ * 8. PageE(0xE00)
-+ * */
-+#define rTxAGC_A_Rate18_06 0xe00
-+#define rTxAGC_A_Rate54_24 0xe04
-+#define rTxAGC_A_CCK1_Mcs32 0xe08
-+#define rTxAGC_A_Mcs03_Mcs00 0xe10
-+#define rTxAGC_A_Mcs07_Mcs04 0xe14
-+#define rTxAGC_A_Mcs11_Mcs08 0xe18
-+#define rTxAGC_A_Mcs15_Mcs12 0xe1c
-+
-+#define rTxAGC_B_Rate18_06 0x830
-+#define rTxAGC_B_Rate54_24 0x834
-+#define rTxAGC_B_CCK1_55_Mcs32 0x838
-+#define rTxAGC_B_Mcs03_Mcs00 0x83c
-+#define rTxAGC_B_Mcs07_Mcs04 0x848
-+#define rTxAGC_B_Mcs11_Mcs08 0x84c
-+#define rTxAGC_B_Mcs15_Mcs12 0x868
-+#define rTxAGC_B_CCK11_A_CCK2_11 0x86c
-+
-+#define rFPGA0_IQK 0xe28
-+#define rTx_IQK_Tone_A 0xe30
-+#define rRx_IQK_Tone_A 0xe34
-+#define rTx_IQK_PI_A 0xe38
-+#define rRx_IQK_PI_A 0xe3c
-+
-+#define rTx_IQK 0xe40
-+#define rRx_IQK 0xe44
-+#define rIQK_AGC_Pts 0xe48
-+#define rIQK_AGC_Rsp 0xe4c
-+#define rTx_IQK_Tone_B 0xe50
-+#define rRx_IQK_Tone_B 0xe54
-+#define rTx_IQK_PI_B 0xe58
-+#define rRx_IQK_PI_B 0xe5c
-+#define rIQK_AGC_Cont 0xe60
-+
-+#define rBlue_Tooth 0xe6c
-+#define rRx_Wait_CCA 0xe70
-+#define rTx_CCK_RFON 0xe74
-+#define rTx_CCK_BBON 0xe78
-+#define rTx_OFDM_RFON 0xe7c
-+#define rTx_OFDM_BBON 0xe80
-+#define rTx_To_Rx 0xe84
-+#define rTx_To_Tx 0xe88
-+#define rRx_CCK 0xe8c
-+
-+#define rTx_Power_Before_IQK_A 0xe94
-+#define rTx_Power_After_IQK_A 0xe9c
-+
-+#define rRx_Power_Before_IQK_A 0xea0
-+#define rRx_Power_Before_IQK_A_2 0xea4
-+#define rRx_Power_After_IQK_A 0xea8
-+#define rRx_Power_After_IQK_A_2 0xeac
-+
-+#define rTx_Power_Before_IQK_B 0xeb4
-+#define rTx_Power_After_IQK_B 0xebc
-+
-+#define rRx_Power_Before_IQK_B 0xec0
-+#define rRx_Power_Before_IQK_B_2 0xec4
-+#define rRx_Power_After_IQK_B 0xec8
-+#define rRx_Power_After_IQK_B_2 0xecc
-+
-+#define rRx_OFDM 0xed0
-+#define rRx_Wait_RIFS 0xed4
-+#define rRx_TO_Rx 0xed8
-+#define rStandby 0xedc
-+#define rSleep 0xee0
-+#define rPMPD_ANAEN 0xeec
-+
-+
-+/* 2. Page8(0x800) */
-+#define bRFMOD 0x1 /* Reg 0x800 rFPGA0_RFMOD */
-+#define bJapanMode 0x2
-+#define bCCKTxSC 0x30
-+#define bCCKEn 0x1000000
-+#define bOFDMEn 0x2000000
-+#define bXBTxAGC 0xf00 /* Reg 80c rFPGA0_TxGainStage */
-+#define bXCTxAGC 0xf000
-+#define bXDTxAGC 0xf0000
-+
-+/* 4. PageA(0xA00) */
-+#define bCCKBBMode 0x3 /* Useless */
-+#define bCCKTxPowerSaving 0x80
-+#define bCCKRxPowerSaving 0x40
-+
-+#define bCCKSideBand 0x10 /* Reg 0xa00 rCCK0_System 20/40 switch */
-+
-+#define bCCKScramble 0x8 /* Useless */
-+#define bCCKAntDiversity 0x8000
-+#define bCCKCarrierRecovery 0x4000
-+#define bCCKTxRate 0x3000
-+#define bCCKDCCancel 0x0800
-+#define bCCKISICancel 0x0400
-+#define bCCKMatchFilter 0x0200
-+#define bCCKEqualizer 0x0100
-+#define bCCKPreambleDetect 0x800000
-+#define bCCKFastFalseCCA 0x400000
-+#define bCCKChEstStart 0x300000
-+#define bCCKCCACount 0x080000
-+#define bCCKcs_lim 0x070000
-+#define bCCKBistMode 0x80000000
-+#define bCCKCCAMask 0x40000000
-+#define bCCKTxDACPhase 0x4
-+#define bCCKRxADCPhase 0x20000000 /* r_rx_clk */
-+#define bCCKr_cp_mode0 0x0100
-+#define bCCKTxDCOffset 0xf0
-+#define bCCKRxDCOffset 0xf
-+#define bCCKCCAMode 0xc000
-+#define bCCKFalseCS_lim 0x3f00
-+#define bCCKCS_ratio 0xc00000
-+#define bCCKCorgBit_sel 0x300000
-+#define bCCKPD_lim 0x0f0000
-+#define bCCKNewCCA 0x80000000
-+#define bCCKRxHPofIG 0x8000
-+#define bCCKRxIG 0x7f00
-+#define bCCKLNAPolarity 0x800000
-+#define bCCKRx1stGain 0x7f0000
-+#define bCCKRFExtend 0x20000000 /* CCK Rx Iinital gain polarity */
-+#define bCCKRxAGCSatLevel 0x1f000000
-+#define bCCKRxAGCSatCount 0xe0
-+#define bCCKRxRFSettle 0x1f /* AGCsamp_dly */
-+#define bCCKFixedRxAGC 0x8000
-+/* #define bCCKRxAGCFormat 0x4000 */ /* remove to HSSI register 0x824 */
-+#define bCCKAntennaPolarity 0x2000
-+#define bCCKTxFilterType 0x0c00
-+#define bCCKRxAGCReportType 0x0300
-+#define bCCKRxDAGCEn 0x80000000
-+#define bCCKRxDAGCPeriod 0x20000000
-+#define bCCKRxDAGCSatLevel 0x1f000000
-+#define bCCKTimingRecovery 0x800000
-+#define bCCKTxC0 0x3f0000
-+#define bCCKTxC1 0x3f000000
-+#define bCCKTxC2 0x3f
-+#define bCCKTxC3 0x3f00
-+#define bCCKTxC4 0x3f0000
-+#define bCCKTxC5 0x3f000000
-+#define bCCKTxC6 0x3f
-+#define bCCKTxC7 0x3f00
-+#define bCCKDebugPort 0xff0000
-+#define bCCKDACDebug 0x0f000000
-+#define bCCKFalseAlarmEnable 0x8000
-+#define bCCKFalseAlarmRead 0x4000
-+#define bCCKTRSSI 0x7f
-+#define bCCKRxAGCReport 0xfe
-+#define bCCKRxReport_AntSel 0x80000000
-+#define bCCKRxReport_MFOff 0x40000000
-+#define bCCKRxRxReport_SQLoss 0x20000000
-+#define bCCKRxReport_Pktloss 0x10000000
-+#define bCCKRxReport_Lockedbit 0x08000000
-+#define bCCKRxReport_RateError 0x04000000
-+#define bCCKRxReport_RxRate 0x03000000
-+#define bCCKRxFACounterLower 0xff
-+#define bCCKRxFACounterUpper 0xff000000
-+#define bCCKRxHPAGCStart 0xe000
-+#define bCCKRxHPAGCFinal 0x1c00
-+#define bCCKRxFalseAlarmEnable 0x8000
-+#define bCCKFACounterFreeze 0x4000
-+#define bCCKTxPathSel 0x10000000
-+#define bCCKDefaultRxPath 0xc000000
-+#define bCCKOptionRxPath 0x3000000
-+
-+/* 6. PageE(0xE00) */
-+#define bSTBCEn 0x4 /* Useless */
-+#define bAntennaMapping 0x10
-+#define bNss 0x20
-+#define bCFOAntSumD 0x200
-+#define bPHYCounterReset 0x8000000
-+#define bCFOReportGet 0x4000000
-+#define bOFDMContinueTx 0x10000000
-+#define bOFDMSingleCarrier 0x20000000
-+#define bOFDMSingleTone 0x40000000
-+
-+
-+/*
-+ * Other Definition
-+ * */
-+
-+#define bEnable 0x1 /* Useless */
-+#define bDisable 0x0
-+
-+/* byte endable for srwrite */
-+#define bByte0 0x1 /* Useless */
-+#define bByte1 0x2
-+#define bByte2 0x4
-+#define bByte3 0x8
-+#define bWord0 0x3
-+#define bWord1 0xc
-+#define bDWord 0xf
-+
-+/* for PutRegsetting & GetRegSetting BitMask */
-+#define bMaskByte0 0xff /* Reg 0xc50 rOFDM0_XAAGCCore~0xC6f */
-+#define bMaskByte1 0xff00
-+#define bMaskByte2 0xff0000
-+#define bMaskByte3 0xff000000
-+#define bMaskHWord 0xffff0000
-+#define bMaskLWord 0x0000ffff
-+#define bMaskDWord 0xffffffff
-+#define bMaskH3Bytes 0xffffff00
-+#define bMask12Bits 0xfff
-+#define bMaskH4Bits 0xf0000000
-+#define bMaskOFDM_D 0xffc00000
-+#define bMaskCCK 0x3f3f3f3f
-+
-+
-+/*--------------------------Define Parameters-------------------------------*/
-+
-+
-+#endif
-diff --git linux-5.8/3rdparty/rtl8812au/include/Hal8812PwrSeq.h linux-5.8/3rdparty/rtl8812au/include/Hal8812PwrSeq.h
-new file mode 100644
-index 000000000..498faf811
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/include/Hal8812PwrSeq.h
-@@ -0,0 +1,208 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+
-+
-+#ifndef __HAL8812PWRSEQ_H__
-+#define __HAL8812PWRSEQ_H__
-+
-+#include "HalPwrSeqCmd.h"
-+
-+/*
-+ Check document WB-110628-DZ-RTL8195 (Jaguar) Power Architecture-R04.pdf
-+ There are 6 HW Power States:
-+ 0: POFF--Power Off
-+ 1: PDN--Power Down
-+ 2: CARDEMU--Card Emulation
-+ 3: ACT--Active Mode
-+ 4: LPS--Low Power State
-+ 5: SUS--Suspend
-+
-+ The transision from different states are defined below
-+ TRANS_CARDEMU_TO_ACT
-+ TRANS_ACT_TO_CARDEMU
-+ TRANS_CARDEMU_TO_SUS
-+ TRANS_SUS_TO_CARDEMU
-+ TRANS_CARDEMU_TO_PDN
-+ TRANS_ACT_TO_LPS
-+ TRANS_LPS_TO_ACT
-+
-+ TRANS_END
-+*/
-+#define RTL8812_TRANS_CARDEMU_TO_ACT_STEPS 15
-+#define RTL8812_TRANS_ACT_TO_CARDEMU_STEPS 15
-+#define RTL8812_TRANS_CARDEMU_TO_SUS_STEPS 15
-+#define RTL8812_TRANS_SUS_TO_CARDEMU_STEPS 15
-+#define RTL8812_TRANS_CARDEMU_TO_PDN_STEPS 15
-+#define RTL8812_TRANS_PDN_TO_CARDEMU_STEPS 15
-+#define RTL8812_TRANS_ACT_TO_LPS_STEPS 15
-+#define RTL8812_TRANS_LPS_TO_ACT_STEPS 15
-+#define RTL8812_TRANS_END_STEPS 1
-+
-+
-+#define RTL8812_TRANS_CARDEMU_TO_ACT \
-+ /* format */ \
-+ /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
-+ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0},/* disable SW LPS 0x04[10]=0*/ \
-+ {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, BIT1},/* wait till 0x04[17] = 1 power ready*/ \
-+ /*{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0}, disable HWPDN 0x04[15]=0*/ \
-+ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, 0},/* disable WL suspend*/ \
-+ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* polling until return 0*/ \
-+ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT0, 0},/**/ \
-+ {0x0024, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0}, /* 0x24[1] Choose the type of buffer after xosc: nand*/ \
-+ {0x0028, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3, 0}, /* 0x28[33] Choose the type of buffer after xosc: nand*/
-+
-+#define RTL8812_TRANS_ACT_TO_CARDEMU \
-+ /* format */ \
-+ /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
-+ {0x0c00, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x04}, /* 0xc00[7:0] = 4 turn off 3-wire */ \
-+ {0x0e00, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x04}, /* 0xe00[7:0] = 4 turn off 3-wire */ \
-+ {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0}, /* 0x2[0] = 0 RESET BB, CLOSE RF */ \
-+ {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/ \
-+ {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0}, /* Whole BB is reset*/ \
-+ /*{0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},//0x1F[7:0] = 0 turn off RF*/ \
-+ /*{0x004E, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},//0x4C[23] = 0x4E[7] = 0, switch DPDT_SEL_P output from register 0x65[2] */ \
-+ {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x2A}, /* 0x07[7:0] = 0x28 sps pwm mode 0x2a for BT coex*/ \
-+ {0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x02, 0},/*0x8[1] = 0 ANA clk = 500k */ \
-+ /*{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0 | BIT1, 0}, // 0x02[1:0] = 0 reset BB */ \
-+ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*0x04[9] = 1 turn off MAC by HW state machine*/ \
-+ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, 0}, /*wait till 0x04[9] = 0 polling until return 0 to disable*/
-+
-+#define RTL8812_TRANS_CARDEMU_TO_SUS \
-+ /* format */ \
-+ /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
-+ {0x0042, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xF0, 0xcc},\
-+ {0x0042, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xF0, 0xEC},\
-+ {0x0043, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x07},/* gpio11 input mode, gpio10~8 output mode */ \
-+ {0x0045, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/* gpio 0~7 output same value as input ?? */ \
-+ {0x0046, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xff},/* gpio0~7 output mode */ \
-+ {0x0047, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/* 0x47[7:0] = 00 gpio mode */ \
-+ {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/* suspend option all off */ \
-+ {0x0014, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x80, BIT7},/*0x14[7] = 1 turn on ZCD */ \
-+ {0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x01, BIT0},/* 0x15[0] =1 trun on ZCD */ \
-+ {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x10, BIT4},/*0x23[4] = 1 hpon LDO sleep mode */ \
-+ {0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x02, 0},/*0x8[1] = 0 ANA clk = 500k */ \
-+ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, BIT3}, /*0x04[11] = 2b'11 enable WL suspend for PCIe*/
-+
-+#define RTL8812_TRANS_SUS_TO_CARDEMU \
-+ /* format */ \
-+ /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
-+ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, 0}, /*0x04[11] = 2b'01enable WL suspend*/ \
-+ {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x10, 0},/*0x23[4] = 0 hpon LDO sleep mode leave */ \
-+ {0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x01, 0},/* 0x15[0] =0 trun off ZCD */ \
-+ {0x0014, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x80, 0},/*0x14[7] = 0 turn off ZCD */ \
-+ {0x0046, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/* gpio0~7 input mode */ \
-+ {0x0043, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/* gpio11 input mode, gpio10~8 input mode */
-+
-+#define RTL8812_TRANS_CARDEMU_TO_CARDDIS \
-+ /* format */ \
-+ /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
-+ /**{0x0194, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0}, //0x194[0]=0 , disable 32K clock*/ \
-+ /**{0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x94}, //0x93 = 0x94 , 90[30] =0 enable 500k ANA clock .switch clock from 12M to 500K , 90 [26] =0 disable EEprom loader clock*/ \
-+ {0x0003, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0}, /*0x03[2] = 0, reset 8051*/ \
-+ {0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x05}, /*0x80 = 05h if reload fw, fill the default value of host_CPU handshake field*/ \
-+ {0x0042, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xF0, 0xcc},\
-+ {0x0042, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xF0, 0xEC},\
-+ {0x0043, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x07},/* gpio11 input mode, gpio10~8 output mode */ \
-+ {0x0045, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/* gpio 0~7 output same value as input ?? */ \
-+ {0x0046, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xff},/* gpio0~7 output mode */ \
-+ {0x0047, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/* 0x47[7:0] = 00 gpio mode */ \
-+ {0x0014, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x80, BIT7},/*0x14[7] = 1 turn on ZCD */ \
-+ {0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x01, BIT0},/* 0x15[0] =1 trun on ZCD */ \
-+ {0x0012, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x01, 0},/*0x12[0] = 0 force PFM mode */ \
-+ {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x10, BIT4},/*0x23[4] = 1 hpon LDO sleep mode */ \
-+ {0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x02, 0},/*0x8[1] = 0 ANA clk = 500k */ \
-+ {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07 = 0x20 , SOP option to disable BG/MB*/ \
-+ {0x001f, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0}, /*0x01f[1]=0 , disable RFC_0 control REG_RF_CTRL_8812 */ \
-+ {0x0076, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0}, /*0x076[1]=0 , disable RFC_1 control REG_OPT_CTRL_8812 +2 */ \
-+ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, BIT3}, /*0x04[11] = 2b'01 enable WL suspend*/
-+
-+#define RTL8812_TRANS_CARDDIS_TO_CARDEMU \
-+ /* format */ \
-+ /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
-+ {0x0012, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/*0x12[0] = 1 force PWM mode */ \
-+ {0x0014, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x80, 0},/*0x14[7] = 0 turn off ZCD */ \
-+ {0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x01, 0},/* 0x15[0] =0 trun off ZCD */ \
-+ {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x10, 0},/*0x23[4] = 0 hpon LDO leave sleep mode */ \
-+ {0x0046, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/* gpio0~7 input mode */ \
-+ {0x0043, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/* gpio11 input mode, gpio10~8 input mode */ \
-+ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0}, /*0x04[10] = 0, enable SW LPS PCIE only*/ \
-+ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, 0}, /*0x04[11] = 2b'01enable WL suspend*/ \
-+ {0x0003, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, BIT2}, /*0x03[2] = 1, enable 8051*/ \
-+ {0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/*PCIe DMA start*/ \
-+ {0x0024, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1}, /* 0x24[1] Choose the type of buffer after xosc: schmitt trigger*/ \
-+ {0x0028, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3, BIT3}, /* 0x28[33] Choose the type of buffer after xosc: schmitt trigger*/
-+
-+
-+#define RTL8812_TRANS_CARDEMU_TO_PDN \
-+ /* format */ \
-+ /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
-+ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7},/* 0x04[15] = 1*/
-+
-+#define RTL8812_TRANS_PDN_TO_CARDEMU \
-+ /* format */ \
-+ /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
-+ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/* 0x04[15] = 0*/
-+
-+#define RTL8812_TRANS_ACT_TO_LPS \
-+ /* format */ \
-+ /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
-+ {0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF},/*PCIe DMA stop*/ \
-+ {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x7F},/*Tx Pause*/ \
-+ {0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
-+ {0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
-+ {0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
-+ {0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
-+ {0x0c00, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x04}, /* 0xc00[7:0] = 4 turn off 3-wire */ \
-+ {0x0e00, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x04}, /* 0xe00[7:0] = 4 turn off 3-wire */ \
-+ {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled, and clock are gated, and RF closed*/ \
-+ {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/ \
-+ {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0}, /* Whole BB is reset*/ \
-+ {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x03},/*Reset MAC TRX*/ \
-+ {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*check if removed later*/ \
-+ {0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5},/*Respond TxOK to scheduler*/
-+
-+
-+#define RTL8812_TRANS_LPS_TO_ACT \
-+ /* format */ \
-+ /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
-+ {0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM*/ \
-+ {0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/ \
-+ {0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/ \
-+ {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /*Delay*/ \
-+ {0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*. 0x08[4] = 0 switch TSF to 40M*/ \
-+ {0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT7, 0}, /*Polling 0x109[7]=0 TSF in 40M*/ \
-+ {0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6 | BIT7, 0}, /*. 0x29[7:6] = 2b'00 enable BB clock*/ \
-+ {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*. 0x101[1] = 1*/ \
-+ {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF}, /*. 0x100[7:0] = 0xFF enable WMAC TRX*/ \
-+ {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1 | BIT0, BIT1 | BIT0}, /*. 0x02[1:0] = 2b'11 enable BB macro*/ \
-+ {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, /*. 0x522 = 0*/
-+
-+#define RTL8812_TRANS_END \
-+ /* format */ \
-+ /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
-+ {0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, 0, PWR_CMD_END, 0, 0},
-+
-+
-+extern WLAN_PWR_CFG rtl8812_power_on_flow[RTL8812_TRANS_CARDEMU_TO_ACT_STEPS + RTL8812_TRANS_END_STEPS];
-+extern WLAN_PWR_CFG rtl8812_radio_off_flow[RTL8812_TRANS_ACT_TO_CARDEMU_STEPS + RTL8812_TRANS_END_STEPS];
-+extern WLAN_PWR_CFG rtl8812_card_disable_flow[RTL8812_TRANS_ACT_TO_CARDEMU_STEPS + RTL8812_TRANS_CARDEMU_TO_PDN_STEPS + RTL8812_TRANS_END_STEPS];
-+extern WLAN_PWR_CFG rtl8812_card_enable_flow[RTL8812_TRANS_ACT_TO_CARDEMU_STEPS + RTL8812_TRANS_CARDEMU_TO_PDN_STEPS + RTL8812_TRANS_END_STEPS];
-+extern WLAN_PWR_CFG rtl8812_suspend_flow[RTL8812_TRANS_ACT_TO_CARDEMU_STEPS + RTL8812_TRANS_CARDEMU_TO_SUS_STEPS + RTL8812_TRANS_END_STEPS];
-+extern WLAN_PWR_CFG rtl8812_resume_flow[RTL8812_TRANS_ACT_TO_CARDEMU_STEPS + RTL8812_TRANS_CARDEMU_TO_SUS_STEPS + RTL8812_TRANS_END_STEPS];
-+extern WLAN_PWR_CFG rtl8812_hwpdn_flow[RTL8812_TRANS_ACT_TO_CARDEMU_STEPS + RTL8812_TRANS_CARDEMU_TO_PDN_STEPS + RTL8812_TRANS_END_STEPS];
-+extern WLAN_PWR_CFG rtl8812_enter_lps_flow[RTL8812_TRANS_ACT_TO_LPS_STEPS + RTL8812_TRANS_END_STEPS];
-+extern WLAN_PWR_CFG rtl8812_leave_lps_flow[RTL8812_TRANS_LPS_TO_ACT_STEPS + RTL8812_TRANS_END_STEPS];
-+
-+#endif /* __HAL8812PWRSEQ_H__ */
-diff --git linux-5.8/3rdparty/rtl8812au/include/Hal8814PhyCfg.h linux-5.8/3rdparty/rtl8812au/include/Hal8814PhyCfg.h
-new file mode 100644
-index 000000000..96f07942e
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/include/Hal8814PhyCfg.h
-@@ -0,0 +1,264 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __INC_HAL8814PHYCFG_H__
-+#define __INC_HAL8814PHYCFG_H__
-+
-+
-+/*--------------------------Define Parameters-------------------------------*/
-+#define LOOP_LIMIT 5
-+#define MAX_STALL_TIME 50 /* us */
-+#define AntennaDiversityValue 0x80 /* (Adapter->bSoftwareAntennaDiversity ? 0x00 : 0x80) */
-+#define MAX_TXPWR_IDX_NMODE_92S 63
-+#define Reset_Cnt_Limit 3
-+
-+
-+#ifdef CONFIG_PCI_HCI
-+ #define MAX_AGGR_NUM 0x0B
-+#else
-+ #define MAX_AGGR_NUM 0x07
-+#endif /* CONFIG_PCI_HCI */
-+
-+
-+/*--------------------------Define Parameters-------------------------------*/
-+
-+/*------------------------------Define structure----------------------------*/
-+
-+
-+/* BB/RF related */
-+
-+#define SIC_ENABLE 0
-+
-+/*------------------------------Define structure----------------------------*/
-+
-+
-+/*------------------------Export global variable----------------------------*/
-+/*------------------------Export global variable----------------------------*/
-+
-+
-+/*------------------------Export Marco Definition---------------------------*/
-+/*------------------------Export Marco Definition---------------------------*/
-+
-+
-+/*--------------------------Exported Function prototype---------------------*/
-+/* 1. BB register R/W API */
-+
-+extern u32
-+PHY_QueryBBReg8814A(IN PADAPTER Adapter,
-+ IN u32 RegAddr,
-+ IN u32 BitMask);
-+
-+
-+VOID
-+PHY_SetBBReg8814A(IN PADAPTER Adapter,
-+ IN u32 RegAddr,
-+ IN u32 BitMask,
-+ IN u32 Data);
-+
-+
-+extern u32
-+PHY_QueryRFReg8814A(IN PADAPTER Adapter,
-+ IN enum rf_path eRFPath,
-+ IN u32 RegAddr,
-+ IN u32 BitMask);
-+
-+
-+void
-+PHY_SetRFReg8814A(IN PADAPTER Adapter,
-+ IN enum rf_path eRFPath,
-+ IN u32 RegAddr,
-+ IN u32 BitMask,
-+ IN u32 Data);
-+
-+/* 1 3. Initial BB/RF config by reading MAC/BB/RF txt. */
-+s32
-+phy_BB8814A_Config_ParaFile(
-+ IN PADAPTER Adapter
-+);
-+
-+VOID
-+PHY_ConfigBB_8814A(
-+ IN PADAPTER Adapter
-+);
-+
-+
-+VOID
-+phy_ADC_CLK_8814A(
-+ IN PADAPTER Adapter
-+);
-+
-+s32
-+PHY_RFConfig8814A(
-+ IN PADAPTER Adapter
-+);
-+
-+/*
-+ * RF Power setting
-+ *
-+ * BOOLEAN PHY_SetRFPowerState8814A(PADAPTER Adapter, rt_rf_power_state eRFPowerState); */
-+
-+/* 1 5. Tx Power setting API */
-+
-+VOID
-+PHY_GetTxPowerLevel8814(
-+ IN PADAPTER Adapter,
-+ OUT ps4Byte powerlevel
-+);
-+
-+VOID
-+PHY_SetTxPowerLevel8814(
-+ IN PADAPTER Adapter,
-+ IN u8 Channel
-+);
-+
-+u8
-+phy_get_tx_power_index_8814a(
-+ IN PADAPTER Adapter,
-+ IN enum rf_path RFPath,
-+ IN u8 Rate,
-+ IN enum channel_width BandWidth,
-+ IN u8 Channel
-+);
-+
-+u8
-+PHY_GetTxPowerIndex8814A(
-+ IN PADAPTER Adapter,
-+ IN enum rf_path RFPath,
-+ IN u8 Rate,
-+ IN u8 BandWidth,
-+ IN u8 Channel,
-+ struct txpwr_idx_comp *tic
-+);
-+
-+VOID
-+PHY_SetTxPowerIndex_8814A(
-+ IN PADAPTER Adapter,
-+ IN u32 PowerIndex,
-+ IN enum rf_path RFPath,
-+ IN u8 Rate
-+);
-+
-+
-+BOOLEAN
-+PHY_UpdateTxPowerDbm8814A(
-+ IN PADAPTER Adapter,
-+ IN s4Byte powerInDbm
-+);
-+
-+
-+u32
-+PHY_GetTxBBSwing_8814A(
-+ IN PADAPTER Adapter,
-+ IN BAND_TYPE Band,
-+ IN enum rf_path RFPath
-+);
-+
-+
-+
-+/* 1 6. Channel setting API */
-+#if 0
-+VOID
-+PHY_SwChnlTimerCallback8814A(
-+ IN struct timer_list *p_timer
-+);
-+#endif
-+VOID
-+PHY_SwChnlWorkItemCallback8814A(
-+ IN PVOID pContext
-+);
-+
-+
-+VOID
-+HAL_HandleSwChnl8814A(
-+ IN PADAPTER pAdapter,
-+ IN u8 channel
-+);
-+
-+VOID
-+PHY_SwChnlSynchronously8814A(IN PADAPTER pAdapter,
-+ IN u8 channel);
-+
-+VOID
-+PHY_SwChnlAndSetBWModeCallback8814A(IN PVOID pContext);
-+
-+
-+VOID
-+PHY_HandleSwChnlAndSetBW8814A(
-+ IN PADAPTER Adapter,
-+ IN BOOLEAN bSwitchChannel,
-+ IN BOOLEAN bSetBandWidth,
-+ IN u8 ChannelNum,
-+ IN enum channel_width ChnlWidth,
-+ IN u8 ChnlOffsetOf40MHz,
-+ IN u8 ChnlOffsetOf80MHz,
-+ IN u8 CenterFrequencyIndex1
-+);
-+
-+
-+BOOLEAN
-+PHY_QueryRFPathSwitch_8814A(IN PADAPTER pAdapter);
-+
-+
-+
-+#if (USE_WORKITEM)
-+VOID
-+RtCheckForHangWorkItemCallback8814A(
-+ IN PVOID pContext
-+);
-+#endif
-+
-+BOOLEAN
-+SetAntennaConfig8814A(
-+ IN PADAPTER Adapter,
-+ IN u8 DefaultAnt
-+);
-+
-+VOID
-+PHY_SetRFEReg8814A(
-+ IN PADAPTER Adapter,
-+ IN BOOLEAN bInit,
-+ IN u8 Band
-+);
-+
-+
-+s32
-+PHY_SwitchWirelessBand8814A(
-+ IN PADAPTER Adapter,
-+ IN u8 Band
-+);
-+
-+VOID
-+PHY_SetIO_8814A(
-+ PADAPTER pAdapter
-+);
-+
-+VOID
-+PHY_SetSwChnlBWMode8814(
-+ IN PADAPTER Adapter,
-+ IN u8 channel,
-+ IN enum channel_width Bandwidth,
-+ IN u8 Offset40,
-+ IN u8 Offset80
-+);
-+
-+s32 PHY_MACConfig8814(PADAPTER Adapter);
-+int PHY_BBConfig8814(PADAPTER Adapter);
-+VOID PHY_Set_SecCCATH_by_RXANT_8814A(PADAPTER pAdapter, u4Byte ulAntennaRx);
-+
-+
-+
-+/*--------------------------Exported Function prototype---------------------*/
-+
-+/*--------------------------Exported Function prototype---------------------*/
-+#endif /* __INC_HAL8192CPHYCFG_H */
-diff --git linux-5.8/3rdparty/rtl8812au/include/Hal8814PhyReg.h linux-5.8/3rdparty/rtl8812au/include/Hal8814PhyReg.h
-new file mode 100644
-index 000000000..21851a898
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/include/Hal8814PhyReg.h
-@@ -0,0 +1,863 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __INC_HAL8814PHYREG_H__
-+#define __INC_HAL8814PHYREG_H__
-+/*--------------------------Define Parameters-------------------------------*/
-+/*
-+ * BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF
-+ * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF
-+ * 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00
-+ * 3. RF register 0x00-2E
-+ * 4. Bit Mask for BB/RF register
-+ * 5. Other defintion for BB/RF R/W
-+ * */
-+
-+
-+/* BB Register Definition */
-+
-+#define rCCAonSec_Jaguar 0x838
-+#define rPwed_TH_Jaguar 0x830
-+#define rL1_Weight_Jaguar 0x840
-+#define r_L1_SBD_start_time 0x844
-+
-+/* BW and sideband setting */
-+#define rBWIndication_Jaguar 0x834
-+#define rL1PeakTH_Jaguar 0x848
-+#define rRFMOD_Jaguar 0x8ac /* RF mode */
-+#define rADC_Buf_Clk_Jaguar 0x8c4
-+#define rADC_Buf_40_Clk_Jaguar2 0x8c8
-+#define rRFECTRL_Jaguar 0x900
-+#define bRFMOD_Jaguar 0xc3
-+#define rCCK_System_Jaguar 0xa00 /* for cck sideband */
-+#define bCCK_System_Jaguar 0x10
-+
-+/* Block & Path enable */
-+#define rOFDMCCKEN_Jaguar 0x808 /* OFDM/CCK block enable */
-+#define bOFDMEN_Jaguar 0x20000000
-+#define bCCKEN_Jaguar 0x10000000
-+#define rRxPath_Jaguar 0x808 /* Rx antenna */
-+#define bRxPath_Jaguar 0xff
-+#define rTxPath_Jaguar 0x80c /* Tx antenna */
-+#define bTxPath_Jaguar 0x0fffffff
-+#define rCCK_RX_Jaguar 0xa04 /* for cck rx path selection */
-+#define bCCK_RX_Jaguar 0x0c000000
-+#define rVhtlen_Use_Lsig_Jaguar 0x8c3 /* Use LSIG for VHT length */
-+
-+#define rRxPath_Jaguar2 0xa04 /* Rx antenna */
-+#define rTxAnt_1Nsts_Jaguar2 0x93c /* Tx antenna for 1Nsts */
-+#define rTxAnt_23Nsts_Jaguar2 0x940 /* Tx antenna for 2Nsts and 3Nsts */
-+
-+
-+/* RF read/write-related */
-+#define rHSSIRead_Jaguar 0x8b0 /* RF read addr */
-+#define bHSSIRead_addr_Jaguar 0xff
-+#define bHSSIRead_trigger_Jaguar 0x100
-+#define rA_PIRead_Jaguar 0xd04 /* RF readback with PI */
-+#define rB_PIRead_Jaguar 0xd44 /* RF readback with PI */
-+#define rA_SIRead_Jaguar 0xd08 /* RF readback with SI */
-+#define rB_SIRead_Jaguar 0xd48 /* RF readback with SI */
-+#define rRead_data_Jaguar 0xfffff
-+#define rA_LSSIWrite_Jaguar 0xc90 /* RF write addr */
-+#define rB_LSSIWrite_Jaguar 0xe90 /* RF write addr */
-+#define bLSSIWrite_data_Jaguar 0x000fffff
-+#define bLSSIWrite_addr_Jaguar 0x0ff00000
-+
-+#define rC_PIRead_Jaguar2 0xd84 /* RF readback with PI */
-+#define rD_PIRead_Jaguar2 0xdC4 /* RF readback with PI */
-+#define rC_SIRead_Jaguar2 0xd88 /* RF readback with SI */
-+#define rD_SIRead_Jaguar2 0xdC8 /* RF readback with SI */
-+#define rC_LSSIWrite_Jaguar2 0x1890 /* RF write addr */
-+#define rD_LSSIWrite_Jaguar2 0x1A90 /* RF write addr */
-+
-+
-+/* YN: mask the following register definition temporarily */
-+#define rFPGA0_XA_RFInterfaceOE 0x860 /* RF Channel switch */
-+#define rFPGA0_XB_RFInterfaceOE 0x864
-+
-+#define rFPGA0_XAB_RFInterfaceSW 0x870 /* RF Interface Software Control */
-+#define rFPGA0_XCD_RFInterfaceSW 0x874
-+
-+/* #define rFPGA0_XAB_RFParameter 0x878 */ /* RF Parameter
-+ * #define rFPGA0_XCD_RFParameter 0x87c */
-+
-+/* #define rFPGA0_AnalogParameter1 0x880 */ /* Crystal cap setting RF-R/W protection for parameter4??
-+ * #define rFPGA0_AnalogParameter2 0x884
-+ * #define rFPGA0_AnalogParameter3 0x888
-+ * #define rFPGA0_AdDaClockEn 0x888 */ /* enable ad/da clock1 for dual-phy
-+ * #define rFPGA0_AnalogParameter4 0x88c */
-+
-+
-+/* CCK TX scaling */
-+#define rCCK_TxFilter1_Jaguar 0xa20
-+#define bCCK_TxFilter1_C0_Jaguar 0x00ff0000
-+#define bCCK_TxFilter1_C1_Jaguar 0xff000000
-+#define rCCK_TxFilter2_Jaguar 0xa24
-+#define bCCK_TxFilter2_C2_Jaguar 0x000000ff
-+#define bCCK_TxFilter2_C3_Jaguar 0x0000ff00
-+#define bCCK_TxFilter2_C4_Jaguar 0x00ff0000
-+#define bCCK_TxFilter2_C5_Jaguar 0xff000000
-+#define rCCK_TxFilter3_Jaguar 0xa28
-+#define bCCK_TxFilter3_C6_Jaguar 0x000000ff
-+#define bCCK_TxFilter3_C7_Jaguar 0x0000ff00
-+/* NBI & CSI Mask setting */
-+#define rCSI_Mask_Setting1_Jaguar 0x874
-+#define rCSI_Fix_Mask0_Jaguar 0x880
-+#define rCSI_Fix_Mask1_Jaguar 0x884
-+#define rCSI_Fix_Mask2_Jaguar 0x888
-+#define rCSI_Fix_Mask3_Jaguar 0x88c
-+#define rCSI_Fix_Mask4_Jaguar 0x890
-+#define rCSI_Fix_Mask5_Jaguar 0x894
-+#define rCSI_Fix_Mask6_Jaguar 0x898
-+#define rCSI_Fix_Mask7_Jaguar 0x89c
-+#define rNBI_Setting_Jaguar 0x87c
-+
-+
-+/* YN: mask the following register definition temporarily
-+ * #define rPdp_AntA 0xb00
-+ * #define rPdp_AntA_4 0xb04
-+ * #define rConfig_Pmpd_AntA 0xb28
-+ * #define rConfig_AntA 0xb68
-+ * #define rConfig_AntB 0xb6c
-+ * #define rPdp_AntB 0xb70
-+ * #define rPdp_AntB_4 0xb74
-+ * #define rConfig_Pmpd_AntB 0xb98
-+ * #define rAPK 0xbd8 */
-+
-+/* RXIQC */
-+#define rA_RxIQC_AB_Jaguar 0xc10 /* RxIQ imblance matrix coeff. A & B */
-+#define rA_RxIQC_CD_Jaguar 0xc14 /* RxIQ imblance matrix coeff. C & D */
-+#define rA_TxScale_Jaguar 0xc1c /* Pah_A TX scaling factor */
-+#define rB_TxScale_Jaguar 0xe1c /* Path_B TX scaling factor */
-+#define rB_RxIQC_AB_Jaguar 0xe10 /* RxIQ imblance matrix coeff. A & B */
-+#define rB_RxIQC_CD_Jaguar 0xe14 /* RxIQ imblance matrix coeff. C & D */
-+#define b_RxIQC_AC_Jaguar 0x02ff /* bit mask for IQC matrix element A & C */
-+#define b_RxIQC_BD_Jaguar 0x02ff0000 /* bit mask for IQC matrix element A & C */
-+
-+#define rC_TxScale_Jaguar2 0x181c /* Pah_C TX scaling factor */
-+#define rD_TxScale_Jaguar2 0x1A1c /* Path_D TX scaling factor */
-+#define rRF_TxGainOffset 0x55
-+
-+/* DIG-related */
-+#define rA_IGI_Jaguar 0xc50 /* Initial Gain for path-A */
-+#define rB_IGI_Jaguar 0xe50 /* Initial Gain for path-B */
-+#define rC_IGI_Jaguar2 0x1850 /* Initial Gain for path-C */
-+#define rD_IGI_Jaguar2 0x1A50 /* Initial Gain for path-D */
-+
-+#define rOFDM_FalseAlarm1_Jaguar 0xf48 /* counter for break */
-+#define rOFDM_FalseAlarm2_Jaguar 0xf4c /* counter for spoofing */
-+#define rCCK_FalseAlarm_Jaguar 0xa5c /* counter for cck false alarm */
-+#define b_FalseAlarm_Jaguar 0xffff
-+#define rCCK_CCA_Jaguar 0xa08 /* cca threshold */
-+#define bCCK_CCA_Jaguar 0x00ff0000
-+
-+/* Tx Power Ttraining-related */
-+#define rA_TxPwrTraing_Jaguar 0xc54
-+#define rB_TxPwrTraing_Jaguar 0xe54
-+
-+/* Report-related */
-+#define rOFDM_ShortCFOAB_Jaguar 0xf60
-+#define rOFDM_LongCFOAB_Jaguar 0xf64
-+#define rOFDM_EndCFOAB_Jaguar 0xf70
-+#define rOFDM_AGCReport_Jaguar 0xf84
-+#define rOFDM_RxSNR_Jaguar 0xf88
-+#define rOFDM_RxEVMCSI_Jaguar 0xf8c
-+#define rOFDM_SIGReport_Jaguar 0xf90
-+
-+/* Misc functions */
-+#define rEDCCA_Jaguar 0x8a4 /* EDCCA */
-+#define bEDCCA_Jaguar 0xffff
-+#define rAGC_table_Jaguar 0x82c /* AGC tabel select */
-+#define bAGC_table_Jaguar 0x3
-+#define b_sel5g_Jaguar 0x1000 /* sel5g */
-+#define b_LNA_sw_Jaguar 0x8000 /* HW/WS control for LNA */
-+#define rFc_area_Jaguar 0x860 /* fc_area */
-+#define bFc_area_Jaguar 0x1ffe000
-+#define rSingleTone_ContTx_Jaguar 0x914
-+
-+#define rAGC_table_Jaguar2 0x958 /* AGC tabel select */
-+#define rDMA_trigger_Jaguar2 0x95C /* ADC sample mode */
-+
-+
-+/* RFE */
-+#define rA_RFE_Pinmux_Jaguar 0xcb0 /* Path_A RFE cotrol pinmux */
-+#define rB_RFE_Pinmux_Jaguar 0xeb0 /* Path_B RFE control pinmux */
-+#define rA_RFE_Inv_Jaguar 0xcb4 /* Path_A RFE cotrol */
-+#define rB_RFE_Inv_Jaguar 0xeb4 /* Path_B RFE control */
-+#define rA_RFE_Jaguar 0xcb8 /* Path_A RFE cotrol */
-+#define rB_RFE_Jaguar 0xeb8 /* Path_B RFE control */
-+#define rA_RFE_Inverse_Jaguar 0xCBC /* Path_A RFE control inverse */
-+#define rB_RFE_Inverse_Jaguar 0xEBC /* Path_B RFE control inverse */
-+#define r_ANTSEL_SW_Jaguar 0x900 /* ANTSEL SW Control */
-+#define bMask_RFEInv_Jaguar 0x3ff00000
-+#define bMask_AntselPathFollow_Jaguar 0x00030000
-+
-+#define rC_RFE_Pinmux_Jaguar 0x18B4 /* Path_C RFE cotrol pinmux */
-+#define rD_RFE_Pinmux_Jaguar 0x1AB4 /* Path_D RFE cotrol pinmux */
-+#define rA_RFE_Sel_Jaguar2 0x1990
-+
-+
-+
-+/* TX AGC */
-+#define rTxAGC_A_CCK11_CCK1_JAguar 0xc20
-+#define rTxAGC_A_Ofdm18_Ofdm6_JAguar 0xc24
-+#define rTxAGC_A_Ofdm54_Ofdm24_JAguar 0xc28
-+#define rTxAGC_A_MCS3_MCS0_JAguar 0xc2c
-+#define rTxAGC_A_MCS7_MCS4_JAguar 0xc30
-+#define rTxAGC_A_MCS11_MCS8_JAguar 0xc34
-+#define rTxAGC_A_MCS15_MCS12_JAguar 0xc38
-+#define rTxAGC_A_Nss1Index3_Nss1Index0_JAguar 0xc3c
-+#define rTxAGC_A_Nss1Index7_Nss1Index4_JAguar 0xc40
-+#define rTxAGC_A_Nss2Index1_Nss1Index8_JAguar 0xc44
-+#define rTxAGC_A_Nss2Index5_Nss2Index2_JAguar 0xc48
-+#define rTxAGC_A_Nss2Index9_Nss2Index6_JAguar 0xc4c
-+#define rTxAGC_B_CCK11_CCK1_JAguar 0xe20
-+#define rTxAGC_B_Ofdm18_Ofdm6_JAguar 0xe24
-+#define rTxAGC_B_Ofdm54_Ofdm24_JAguar 0xe28
-+#define rTxAGC_B_MCS3_MCS0_JAguar 0xe2c
-+#define rTxAGC_B_MCS7_MCS4_JAguar 0xe30
-+#define rTxAGC_B_MCS11_MCS8_JAguar 0xe34
-+#define rTxAGC_B_MCS15_MCS12_JAguar 0xe38
-+#define rTxAGC_B_Nss1Index3_Nss1Index0_JAguar 0xe3c
-+#define rTxAGC_B_Nss1Index7_Nss1Index4_JAguar 0xe40
-+#define rTxAGC_B_Nss2Index1_Nss1Index8_JAguar 0xe44
-+#define rTxAGC_B_Nss2Index5_Nss2Index2_JAguar 0xe48
-+#define rTxAGC_B_Nss2Index9_Nss2Index6_JAguar 0xe4c
-+#define bTxAGC_byte0_Jaguar 0xff
-+#define bTxAGC_byte1_Jaguar 0xff00
-+#define bTxAGC_byte2_Jaguar 0xff0000
-+#define bTxAGC_byte3_Jaguar 0xff000000
-+
-+
-+/* TX AGC */
-+#define rTxAGC_A_CCK11_CCK1_Jaguar2 0xc20
-+#define rTxAGC_A_Ofdm18_Ofdm6_Jaguar2 0xc24
-+#define rTxAGC_A_Ofdm54_Ofdm24_Jaguar2 0xc28
-+#define rTxAGC_A_MCS3_MCS0_Jaguar2 0xc2c
-+#define rTxAGC_A_MCS7_MCS4_Jaguar2 0xc30
-+#define rTxAGC_A_MCS11_MCS8_Jaguar2 0xc34
-+#define rTxAGC_A_MCS15_MCS12_Jaguar2 0xc38
-+#define rTxAGC_A_MCS19_MCS16_Jaguar2 0xcd8
-+#define rTxAGC_A_MCS23_MCS20_Jaguar2 0xcdc
-+#define rTxAGC_A_Nss1Index3_Nss1Index0_Jaguar2 0xc3c
-+#define rTxAGC_A_Nss1Index7_Nss1Index4_Jaguar2 0xc40
-+#define rTxAGC_A_Nss2Index1_Nss1Index8_Jaguar2 0xc44
-+#define rTxAGC_A_Nss2Index5_Nss2Index2_Jaguar2 0xc48
-+#define rTxAGC_A_Nss2Index9_Nss2Index6_Jaguar2 0xc4c
-+#define rTxAGC_A_Nss3Index3_Nss3Index0_Jaguar2 0xce0
-+#define rTxAGC_A_Nss3Index7_Nss3Index4_Jaguar2 0xce4
-+#define rTxAGC_A_Nss3Index9_Nss3Index8_Jaguar2 0xce8
-+#define rTxAGC_B_CCK11_CCK1_Jaguar2 0xe20
-+#define rTxAGC_B_Ofdm18_Ofdm6_Jaguar2 0xe24
-+#define rTxAGC_B_Ofdm54_Ofdm24_Jaguar2 0xe28
-+#define rTxAGC_B_MCS3_MCS0_Jaguar2 0xe2c
-+#define rTxAGC_B_MCS7_MCS4_Jaguar2 0xe30
-+#define rTxAGC_B_MCS11_MCS8_Jaguar2 0xe34
-+#define rTxAGC_B_MCS15_MCS12_Jaguar2 0xe38
-+#define rTxAGC_B_MCS19_MCS16_Jaguar2 0xed8
-+#define rTxAGC_B_MCS23_MCS20_Jaguar2 0xedc
-+#define rTxAGC_B_Nss1Index3_Nss1Index0_Jaguar2 0xe3c
-+#define rTxAGC_B_Nss1Index7_Nss1Index4_Jaguar2 0xe40
-+#define rTxAGC_B_Nss2Index1_Nss1Index8_Jaguar2 0xe44
-+#define rTxAGC_B_Nss2Index5_Nss2Index2_Jaguar2 0xe48
-+#define rTxAGC_B_Nss2Index9_Nss2Index6_Jaguar2 0xe4c
-+#define rTxAGC_B_Nss3Index3_Nss3Index0_Jaguar2 0xee0
-+#define rTxAGC_B_Nss3Index7_Nss3Index4_Jaguar2 0xee4
-+#define rTxAGC_B_Nss3Index9_Nss3Index8_Jaguar2 0xee8
-+#define rTxAGC_C_CCK11_CCK1_Jaguar2 0x1820
-+#define rTxAGC_C_Ofdm18_Ofdm6_Jaguar2 0x1824
-+#define rTxAGC_C_Ofdm54_Ofdm24_Jaguar2 0x1828
-+#define rTxAGC_C_MCS3_MCS0_Jaguar2 0x182c
-+#define rTxAGC_C_MCS7_MCS4_Jaguar2 0x1830
-+#define rTxAGC_C_MCS11_MCS8_Jaguar2 0x1834
-+#define rTxAGC_C_MCS15_MCS12_Jaguar2 0x1838
-+#define rTxAGC_C_MCS19_MCS16_Jaguar2 0x18d8
-+#define rTxAGC_C_MCS23_MCS20_Jaguar2 0x18dc
-+#define rTxAGC_C_Nss1Index3_Nss1Index0_Jaguar2 0x183c
-+#define rTxAGC_C_Nss1Index7_Nss1Index4_Jaguar2 0x1840
-+#define rTxAGC_C_Nss2Index1_Nss1Index8_Jaguar2 0x1844
-+#define rTxAGC_C_Nss2Index5_Nss2Index2_Jaguar2 0x1848
-+#define rTxAGC_C_Nss2Index9_Nss2Index6_Jaguar2 0x184c
-+#define rTxAGC_C_Nss3Index3_Nss3Index0_Jaguar2 0x18e0
-+#define rTxAGC_C_Nss3Index7_Nss3Index4_Jaguar2 0x18e4
-+#define rTxAGC_C_Nss3Index9_Nss3Index8_Jaguar2 0x18e8
-+#define rTxAGC_D_CCK11_CCK1_Jaguar2 0x1a20
-+#define rTxAGC_D_Ofdm18_Ofdm6_Jaguar2 0x1a24
-+#define rTxAGC_D_Ofdm54_Ofdm24_Jaguar2 0x1a28
-+#define rTxAGC_D_MCS3_MCS0_Jaguar2 0x1a2c
-+#define rTxAGC_D_MCS7_MCS4_Jaguar2 0x1a30
-+#define rTxAGC_D_MCS11_MCS8_Jaguar2 0x1a34
-+#define rTxAGC_D_MCS15_MCS12_Jaguar2 0x1a38
-+#define rTxAGC_D_MCS19_MCS16_Jaguar2 0x1ad8
-+#define rTxAGC_D_MCS23_MCS20_Jaguar2 0x1adc
-+#define rTxAGC_D_Nss1Index3_Nss1Index0_Jaguar2 0x1a3c
-+#define rTxAGC_D_Nss1Index7_Nss1Index4_Jaguar2 0x1a40
-+#define rTxAGC_D_Nss2Index1_Nss1Index8_Jaguar2 0x1a44
-+#define rTxAGC_D_Nss2Index5_Nss2Index2_Jaguar2 0x1a48
-+#define rTxAGC_D_Nss2Index9_Nss2Index6_Jaguar2 0x1a4c
-+#define rTxAGC_D_Nss3Index3_Nss3Index0_Jaguar2 0x1ae0
-+#define rTxAGC_D_Nss3Index7_Nss3Index4_Jaguar2 0x1ae4
-+#define rTxAGC_D_Nss3Index9_Nss3Index8_Jaguar2 0x1ae8
-+/* IQK YN: temporaily mask this part
-+ * #define rFPGA0_IQK 0xe28
-+ * #define rTx_IQK_Tone_A 0xe30
-+ * #define rRx_IQK_Tone_A 0xe34
-+ * #define rTx_IQK_PI_A 0xe38
-+ * #define rRx_IQK_PI_A 0xe3c */
-+
-+/* #define rTx_IQK 0xe40 */
-+/* #define rRx_IQK 0xe44 */
-+/* #define rIQK_AGC_Pts 0xe48 */
-+/* #define rIQK_AGC_Rsp 0xe4c */
-+/* #define rTx_IQK_Tone_B 0xe50 */
-+/* #define rRx_IQK_Tone_B 0xe54 */
-+/* #define rTx_IQK_PI_B 0xe58 */
-+/* #define rRx_IQK_PI_B 0xe5c */
-+/* #define rIQK_AGC_Cont 0xe60 */
-+
-+
-+/* AFE-related */
-+#define rA_AFEPwr1_Jaguar 0xc60 /* dynamic AFE power control */
-+#define rA_AFEPwr2_Jaguar 0xc64 /* dynamic AFE power control */
-+#define rA_Rx_WaitCCA_Tx_CCKRFON_Jaguar 0xc68
-+#define rA_Tx_CCKBBON_OFDMRFON_Jaguar 0xc6c
-+#define rA_Tx_OFDMBBON_Tx2Rx_Jaguar 0xc70
-+#define rA_Tx2Tx_RXCCK_Jaguar 0xc74
-+#define rA_Rx_OFDM_WaitRIFS_Jaguar 0xc78
-+#define rA_Rx2Rx_BT_Jaguar 0xc7c
-+#define rA_sleep_nav_Jaguar 0xc80
-+#define rA_pmpd_Jaguar 0xc84
-+#define rB_AFEPwr1_Jaguar 0xe60 /* dynamic AFE power control */
-+#define rB_AFEPwr2_Jaguar 0xe64 /* dynamic AFE power control */
-+#define rB_Rx_WaitCCA_Tx_CCKRFON_Jaguar 0xe68
-+#define rB_Tx_CCKBBON_OFDMRFON_Jaguar 0xe6c
-+#define rB_Tx_OFDMBBON_Tx2Rx_Jaguar 0xe70
-+#define rB_Tx2Tx_RXCCK_Jaguar 0xe74
-+#define rB_Rx_OFDM_WaitRIFS_Jaguar 0xe78
-+#define rB_Rx2Rx_BT_Jaguar 0xe7c
-+#define rB_sleep_nav_Jaguar 0xe80
-+#define rB_pmpd_Jaguar 0xe84
-+
-+
-+/* YN: mask these registers temporaily
-+ * #define rTx_Power_Before_IQK_A 0xe94
-+ * #define rTx_Power_After_IQK_A 0xe9c */
-+
-+/* #define rRx_Power_Before_IQK_A 0xea0 */
-+/* #define rRx_Power_Before_IQK_A_2 0xea4 */
-+/* #define rRx_Power_After_IQK_A 0xea8 */
-+/* #define rRx_Power_After_IQK_A_2 0xeac */
-+
-+/* #define rTx_Power_Before_IQK_B 0xeb4 */
-+/* #define rTx_Power_After_IQK_B 0xebc */
-+
-+/* #define rRx_Power_Before_IQK_B 0xec0 */
-+/* #define rRx_Power_Before_IQK_B_2 0xec4 */
-+/* #define rRx_Power_After_IQK_B 0xec8 */
-+/* #define rRx_Power_After_IQK_B_2 0xecc */
-+
-+
-+/* RSSI Dump */
-+#define rA_RSSIDump_Jaguar 0xBF0
-+#define rB_RSSIDump_Jaguar 0xBF1
-+#define rS1_RXevmDump_Jaguar 0xBF4
-+#define rS2_RXevmDump_Jaguar 0xBF5
-+#define rA_RXsnrDump_Jaguar 0xBF6
-+#define rB_RXsnrDump_Jaguar 0xBF7
-+#define rA_CfoShortDump_Jaguar 0xBF8
-+#define rB_CfoShortDump_Jaguar 0xBFA
-+#define rA_CfoLongDump_Jaguar 0xBEC
-+#define rB_CfoLongDump_Jaguar 0xBEE
-+
-+
-+/* RF Register
-+ * */
-+#define RF_AC_Jaguar 0x00 /* */
-+#define RF_RF_Top_Jaguar 0x07 /* */
-+#define RF_TXLOK_Jaguar 0x08 /* */
-+#define RF_TXAPK_Jaguar 0x0B
-+#define RF_CHNLBW_Jaguar 0x18 /* RF channel and BW switch */
-+#define RF_RCK1_Jaguar 0x1c /* */
-+#define RF_RCK2_Jaguar 0x1d
-+#define RF_RCK3_Jaguar 0x1e
-+#define RF_ModeTableAddr 0x30
-+#define RF_ModeTableData0 0x31
-+#define RF_ModeTableData1 0x32
-+#define RF_TxLCTank_Jaguar 0x54
-+#define RF_APK_Jaguar 0x63
-+#define RF_LCK 0xB4
-+#define RF_WeLut_Jaguar 0xEF
-+
-+#define bRF_CHNLBW_MOD_AG_Jaguar 0x70300
-+#define bRF_CHNLBW_BW 0xc00
-+
-+
-+/*
-+ * RL6052 Register definition
-+ * */
-+#define RF_AC 0x00 /* */
-+#define RF_IPA_A 0x0C /* */
-+#define RF_TXBIAS_A 0x0D
-+#define RF_BS_PA_APSET_G9_G11 0x0E
-+#define RF_MODE1 0x10 /* */
-+#define RF_MODE2 0x11 /* */
-+#define RF_CHNLBW 0x18 /* RF channel and BW switch */
-+#define RF_RCK_OS 0x30 /* RF TX PA control */
-+#define RF_TXPA_G1 0x31 /* RF TX PA control */
-+#define RF_TXPA_G2 0x32 /* RF TX PA control */
-+#define RF_TXPA_G3 0x33 /* RF TX PA control */
-+#define RF_0x52 0x52
-+#define RF_WE_LUT 0xEF
-+
-+/*
-+ * Bit Mask
-+ *
-+ * 1. Page1(0x100) */
-+#define bBBResetB 0x100 /* Useless now? */
-+#define bGlobalResetB 0x200
-+#define bOFDMTxStart 0x4
-+#define bCCKTxStart 0x8
-+#define bCRC32Debug 0x100
-+#define bPMACLoopback 0x10
-+#define bTxLSIG 0xffffff
-+#define bOFDMTxRate 0xf
-+#define bOFDMTxReserved 0x10
-+#define bOFDMTxLength 0x1ffe0
-+#define bOFDMTxParity 0x20000
-+#define bTxHTSIG1 0xffffff
-+#define bTxHTMCSRate 0x7f
-+#define bTxHTBW 0x80
-+#define bTxHTLength 0xffff00
-+#define bTxHTSIG2 0xffffff
-+#define bTxHTSmoothing 0x1
-+#define bTxHTSounding 0x2
-+#define bTxHTReserved 0x4
-+#define bTxHTAggreation 0x8
-+#define bTxHTSTBC 0x30
-+#define bTxHTAdvanceCoding 0x40
-+#define bTxHTShortGI 0x80
-+#define bTxHTNumberHT_LTF 0x300
-+#define bTxHTCRC8 0x3fc00
-+#define bCounterReset 0x10000
-+#define bNumOfOFDMTx 0xffff
-+#define bNumOfCCKTx 0xffff0000
-+#define bTxIdleInterval 0xffff
-+#define bOFDMService 0xffff0000
-+#define bTxMACHeader 0xffffffff
-+#define bTxDataInit 0xff
-+#define bTxHTMode 0x100
-+#define bTxDataType 0x30000
-+#define bTxRandomSeed 0xffffffff
-+#define bCCKTxPreamble 0x1
-+#define bCCKTxSFD 0xffff0000
-+#define bCCKTxSIG 0xff
-+#define bCCKTxService 0xff00
-+#define bCCKLengthExt 0x8000
-+#define bCCKTxLength 0xffff0000
-+#define bCCKTxCRC16 0xffff
-+#define bCCKTxStatus 0x1
-+#define bOFDMTxStatus 0x2
-+
-+
-+/*
-+ * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF
-+ * 1. Page1(0x100)
-+ * */
-+#define rPMAC_Reset 0x100
-+#define rPMAC_TxStart 0x104
-+#define rPMAC_TxLegacySIG 0x108
-+#define rPMAC_TxHTSIG1 0x10c
-+#define rPMAC_TxHTSIG2 0x110
-+#define rPMAC_PHYDebug 0x114
-+#define rPMAC_TxPacketNum 0x118
-+#define rPMAC_TxIdle 0x11c
-+#define rPMAC_TxMACHeader0 0x120
-+#define rPMAC_TxMACHeader1 0x124
-+#define rPMAC_TxMACHeader2 0x128
-+#define rPMAC_TxMACHeader3 0x12c
-+#define rPMAC_TxMACHeader4 0x130
-+#define rPMAC_TxMACHeader5 0x134
-+#define rPMAC_TxDataType 0x138
-+#define rPMAC_TxRandomSeed 0x13c
-+#define rPMAC_CCKPLCPPreamble 0x140
-+#define rPMAC_CCKPLCPHeader 0x144
-+#define rPMAC_CCKCRC16 0x148
-+#define rPMAC_OFDMRxCRC32OK 0x170
-+#define rPMAC_OFDMRxCRC32Er 0x174
-+#define rPMAC_OFDMRxParityEr 0x178
-+#define rPMAC_OFDMRxCRC8Er 0x17c
-+#define rPMAC_CCKCRxRC16Er 0x180
-+#define rPMAC_CCKCRxRC32Er 0x184
-+#define rPMAC_CCKCRxRC32OK 0x188
-+#define rPMAC_TxStatus 0x18c
-+
-+/*
-+ * 3. Page8(0x800)
-+ * */
-+#define rFPGA0_RFMOD 0x800 /* RF mode & CCK TxSC */ /* RF BW Setting?? */
-+
-+#define rFPGA0_TxInfo 0x804 /* Status report?? */
-+#define rFPGA0_PSDFunction 0x808
-+#define rFPGA0_TxGainStage 0x80c /* Set TX PWR init gain? */
-+
-+#define rFPGA0_XA_HSSIParameter1 0x820 /* RF 3 wire register */
-+#define rFPGA0_XA_HSSIParameter2 0x824
-+#define rFPGA0_XB_HSSIParameter1 0x828
-+#define rFPGA0_XB_HSSIParameter2 0x82c
-+
-+#define rFPGA0_XA_LSSIParameter 0x840
-+#define rFPGA0_XB_LSSIParameter 0x844
-+
-+#define rFPGA0_XAB_SwitchControl 0x858 /* RF Channel switch */
-+#define rFPGA0_XCD_SwitchControl 0x85c
-+
-+#define rFPGA0_XAB_RFParameter 0x878 /* RF Parameter */
-+#define rFPGA0_XCD_RFParameter 0x87c
-+
-+#define rFPGA0_AnalogParameter1 0x880 /* Crystal cap setting RF-R/W protection for parameter4?? */
-+#define rFPGA0_AnalogParameter2 0x884
-+#define rFPGA0_AnalogParameter3 0x888
-+#define rFPGA0_AdDaClockEn 0x888 /* enable ad/da clock1 for dual-phy */
-+#define rFPGA0_AnalogParameter4 0x88c
-+
-+#define rFPGA0_XA_LSSIReadBack 0x8a0 /* Tranceiver LSSI Readback */
-+#define rFPGA0_XB_LSSIReadBack 0x8a4
-+#define rFPGA0_XC_LSSIReadBack 0x8a8
-+#define rFPGA0_XD_LSSIReadBack 0x8ac
-+
-+#define rFPGA0_XCD_RFPara 0x8b4
-+#define rFPGA0_PSDReport 0x8b4 /* Useless now */
-+#define TransceiverA_HSPI_Readback 0x8b8 /* Transceiver A HSPI Readback */
-+#define TransceiverB_HSPI_Readback 0x8bc /* Transceiver B HSPI Readback */
-+#define rFPGA0_XAB_RFInterfaceRB 0x8e0 /* Useless now */ /* RF Interface Readback Value */
-+#define rFPGA0_XCD_RFInterfaceRB 0x8e4 /* Useless now */
-+
-+/*
-+ * 4. Page9(0x900)
-+ * */
-+#define rFPGA1_RFMOD 0x900 /* RF mode & OFDM TxSC */ /* RF BW Setting?? */
-+#define REG_BB_TX_PATH_SEL_1_8814A 0x93c
-+#define REG_BB_TX_PATH_SEL_2_8814A 0x940
-+#define rFPGA1_TxBlock 0x904 /* Useless now */
-+#define rFPGA1_DebugSelect 0x908 /* Useless now */
-+#define rFPGA1_TxInfo 0x90c /* Useless now */ /* Status report?? */
-+/*Page 19 for TxBF*/
-+#define REG_BB_TXBF_ANT_SET_BF1_8814A 0x19ac
-+#define REG_BB_TXBF_ANT_SET_BF0_8814A 0x19b4
-+/*
-+ * PageA(0xA00)
-+ * */
-+#define rCCK0_System 0xa00
-+#define rCCK0_AFESetting 0xa04 /* Disable init gain now */ /* Select RX path by RSSI */
-+#define rCCK0_DSPParameter2 0xa1c /* SQ threshold */
-+#define rCCK0_TxFilter1 0xa20
-+#define rCCK0_TxFilter2 0xa24
-+#define rCCK0_DebugPort 0xa28 /* debug port and Tx filter3 */
-+#define rCCK0_FalseAlarmReport 0xa2c /* 0xa2d useless now 0xa30-a4f channel report */
-+
-+/*
-+ * PageB(0xB00)
-+ * */
-+#define rPdp_AntA 0xb00
-+#define rPdp_AntA_4 0xb04
-+#define rConfig_Pmpd_AntA 0xb28
-+#define rConfig_AntA 0xb68
-+#define rConfig_AntB 0xb6c
-+#define rPdp_AntB 0xb70
-+#define rPdp_AntB_4 0xb74
-+#define rConfig_Pmpd_AntB 0xb98
-+#define rAPK 0xbd8
-+
-+/*
-+ * 6. PageC(0xC00)
-+ * */
-+#define rOFDM0_LSTF 0xc00
-+
-+#define rOFDM0_TRxPathEnable 0xc04
-+#define rOFDM0_TRMuxPar 0xc08
-+#define rOFDM0_TRSWIsolation 0xc0c
-+
-+#define rOFDM0_XARxAFE 0xc10 /* RxIQ DC offset, Rx digital filter, DC notch filter */
-+#define rOFDM0_XARxIQImbalance 0xc14 /* RxIQ imblance matrix */
-+#define rOFDM0_XBRxAFE 0xc18
-+#define rOFDM0_XBRxIQImbalance 0xc1c
-+#define rOFDM0_XCRxAFE 0xc20
-+#define rOFDM0_XCRxIQImbalance 0xc24
-+#define rOFDM0_XDRxAFE 0xc28
-+#define rOFDM0_XDRxIQImbalance 0xc2c
-+
-+#define rOFDM0_RxDetector1 0xc30 /* PD, BW & SBD */ /* DM tune init gain */
-+#define rOFDM0_RxDetector2 0xc34 /* SBD & Fame Sync. */
-+#define rOFDM0_RxDetector3 0xc38 /* Frame Sync. */
-+#define rOFDM0_RxDetector4 0xc3c /* PD, SBD, Frame Sync & Short-GI */
-+
-+#define rOFDM0_RxDSP 0xc40 /* Rx Sync Path */
-+#define rOFDM0_CFOandDAGC 0xc44 /* CFO & DAGC */
-+#define rOFDM0_CCADropThreshold 0xc48 /* CCA Drop threshold */
-+#define rOFDM0_ECCAThreshold 0xc4c /* energy CCA */
-+
-+#define rOFDM0_XAAGCCore1 0xc50 /* DIG */
-+#define rOFDM0_XAAGCCore2 0xc54
-+#define rOFDM0_XBAGCCore1 0xc58
-+#define rOFDM0_XBAGCCore2 0xc5c
-+#define rOFDM0_XCAGCCore1 0xc60
-+#define rOFDM0_XCAGCCore2 0xc64
-+#define rOFDM0_XDAGCCore1 0xc68
-+#define rOFDM0_XDAGCCore2 0xc6c
-+
-+#define rOFDM0_AGCParameter1 0xc70
-+#define rOFDM0_AGCParameter2 0xc74
-+#define rOFDM0_AGCRSSITable 0xc78
-+#define rOFDM0_HTSTFAGC 0xc7c
-+
-+#define rOFDM0_XATxIQImbalance 0xc80 /* TX PWR TRACK and DIG */
-+#define rOFDM0_XATxAFE 0xc84
-+#define rOFDM0_XBTxIQImbalance 0xc88
-+#define rOFDM0_XBTxAFE 0xc8c
-+#define rOFDM0_XCTxIQImbalance 0xc90
-+#define rOFDM0_XCTxAFE 0xc94
-+#define rOFDM0_XDTxIQImbalance 0xc98
-+#define rOFDM0_XDTxAFE 0xc9c
-+
-+#define rOFDM0_RxIQExtAnta 0xca0
-+#define rOFDM0_TxCoeff1 0xca4
-+#define rOFDM0_TxCoeff2 0xca8
-+#define rOFDM0_TxCoeff3 0xcac
-+#define rOFDM0_TxCoeff4 0xcb0
-+#define rOFDM0_TxCoeff5 0xcb4
-+#define rOFDM0_TxCoeff6 0xcb8
-+#define rOFDM0_RxHPParameter 0xce0
-+#define rOFDM0_TxPseudoNoiseWgt 0xce4
-+#define rOFDM0_FrameSync 0xcf0
-+#define rOFDM0_DFSReport 0xcf4
-+
-+/*
-+ * 7. PageD(0xD00)
-+ * */
-+#define rOFDM1_LSTF 0xd00
-+#define rOFDM1_TRxPathEnable 0xd04
-+
-+/*
-+ * 8. PageE(0xE00)
-+ * */
-+#define rTxAGC_A_Rate18_06 0xe00
-+#define rTxAGC_A_Rate54_24 0xe04
-+#define rTxAGC_A_CCK1_Mcs32 0xe08
-+#define rTxAGC_A_Mcs03_Mcs00 0xe10
-+#define rTxAGC_A_Mcs07_Mcs04 0xe14
-+#define rTxAGC_A_Mcs11_Mcs08 0xe18
-+#define rTxAGC_A_Mcs15_Mcs12 0xe1c
-+
-+#define rTxAGC_B_Rate18_06 0x830
-+#define rTxAGC_B_Rate54_24 0x834
-+#define rTxAGC_B_CCK1_55_Mcs32 0x838
-+#define rTxAGC_B_Mcs03_Mcs00 0x83c
-+#define rTxAGC_B_Mcs07_Mcs04 0x848
-+#define rTxAGC_B_Mcs11_Mcs08 0x84c
-+#define rTxAGC_B_Mcs15_Mcs12 0x868
-+#define rTxAGC_B_CCK11_A_CCK2_11 0x86c
-+
-+#define rFPGA0_IQK 0xe28
-+#define rTx_IQK_Tone_A 0xe30
-+#define rRx_IQK_Tone_A 0xe34
-+#define rTx_IQK_PI_A 0xe38
-+#define rRx_IQK_PI_A 0xe3c
-+
-+#define rTx_IQK 0xe40
-+#define rRx_IQK 0xe44
-+#define rIQK_AGC_Pts 0xe48
-+#define rIQK_AGC_Rsp 0xe4c
-+#define rTx_IQK_Tone_B 0xe50
-+#define rRx_IQK_Tone_B 0xe54
-+#define rTx_IQK_PI_B 0xe58
-+#define rRx_IQK_PI_B 0xe5c
-+#define rIQK_AGC_Cont 0xe60
-+
-+#define rBlue_Tooth 0xe6c
-+#define rRx_Wait_CCA 0xe70
-+#define rTx_CCK_RFON 0xe74
-+#define rTx_CCK_BBON 0xe78
-+#define rTx_OFDM_RFON 0xe7c
-+#define rTx_OFDM_BBON 0xe80
-+#define rTx_To_Rx 0xe84
-+#define rTx_To_Tx 0xe88
-+#define rRx_CCK 0xe8c
-+
-+#define rTx_Power_Before_IQK_A 0xe94
-+#define rTx_Power_After_IQK_A 0xe9c
-+
-+#define rRx_Power_Before_IQK_A 0xea0
-+#define rRx_Power_Before_IQK_A_2 0xea4
-+#define rRx_Power_After_IQK_A 0xea8
-+#define rRx_Power_After_IQK_A_2 0xeac
-+
-+#define rTx_Power_Before_IQK_B 0xeb4
-+#define rTx_Power_After_IQK_B 0xebc
-+
-+#define rRx_Power_Before_IQK_B 0xec0
-+#define rRx_Power_Before_IQK_B_2 0xec4
-+#define rRx_Power_After_IQK_B 0xec8
-+#define rRx_Power_After_IQK_B_2 0xecc
-+
-+#define rRx_OFDM 0xed0
-+#define rRx_Wait_RIFS 0xed4
-+#define rRx_TO_Rx 0xed8
-+#define rStandby 0xedc
-+#define rSleep 0xee0
-+#define rPMPD_ANAEN 0xeec
-+
-+
-+/* 2. Page8(0x800) */
-+#define bRFMOD 0x1 /* Reg 0x800 rFPGA0_RFMOD */
-+#define bJapanMode 0x2
-+#define bCCKTxSC 0x30
-+#define bCCKEn 0x1000000
-+#define bOFDMEn 0x2000000
-+#define bXBTxAGC 0xf00 /* Reg 80c rFPGA0_TxGainStage */
-+#define bXCTxAGC 0xf000
-+#define bXDTxAGC 0xf0000
-+
-+/* 4. PageA(0xA00) */
-+#define bCCKBBMode 0x3 /* Useless */
-+#define bCCKTxPowerSaving 0x80
-+#define bCCKRxPowerSaving 0x40
-+
-+#define bCCKSideBand 0x10 /* Reg 0xa00 rCCK0_System 20/40 switch */
-+
-+#define bCCKScramble 0x8 /* Useless */
-+#define bCCKAntDiversity 0x8000
-+#define bCCKCarrierRecovery 0x4000
-+#define bCCKTxRate 0x3000
-+#define bCCKDCCancel 0x0800
-+#define bCCKISICancel 0x0400
-+#define bCCKMatchFilter 0x0200
-+#define bCCKEqualizer 0x0100
-+#define bCCKPreambleDetect 0x800000
-+#define bCCKFastFalseCCA 0x400000
-+#define bCCKChEstStart 0x300000
-+#define bCCKCCACount 0x080000
-+#define bCCKcs_lim 0x070000
-+#define bCCKBistMode 0x80000000
-+#define bCCKCCAMask 0x40000000
-+#define bCCKTxDACPhase 0x4
-+#define bCCKRxADCPhase 0x20000000 /* r_rx_clk */
-+#define bCCKr_cp_mode0 0x0100
-+#define bCCKTxDCOffset 0xf0
-+#define bCCKRxDCOffset 0xf
-+#define bCCKCCAMode 0xc000
-+#define bCCKFalseCS_lim 0x3f00
-+#define bCCKCS_ratio 0xc00000
-+#define bCCKCorgBit_sel 0x300000
-+#define bCCKPD_lim 0x0f0000
-+#define bCCKNewCCA 0x80000000
-+#define bCCKRxHPofIG 0x8000
-+#define bCCKRxIG 0x7f00
-+#define bCCKLNAPolarity 0x800000
-+#define bCCKRx1stGain 0x7f0000
-+#define bCCKRFExtend 0x20000000 /* CCK Rx Iinital gain polarity */
-+#define bCCKRxAGCSatLevel 0x1f000000
-+#define bCCKRxAGCSatCount 0xe0
-+#define bCCKRxRFSettle 0x1f /* AGCsamp_dly */
-+#define bCCKFixedRxAGC 0x8000
-+/* #define bCCKRxAGCFormat 0x4000 */ /* remove to HSSI register 0x824 */
-+#define bCCKAntennaPolarity 0x2000
-+#define bCCKTxFilterType 0x0c00
-+#define bCCKRxAGCReportType 0x0300
-+#define bCCKRxDAGCEn 0x80000000
-+#define bCCKRxDAGCPeriod 0x20000000
-+#define bCCKRxDAGCSatLevel 0x1f000000
-+#define bCCKTimingRecovery 0x800000
-+#define bCCKTxC0 0x3f0000
-+#define bCCKTxC1 0x3f000000
-+#define bCCKTxC2 0x3f
-+#define bCCKTxC3 0x3f00
-+#define bCCKTxC4 0x3f0000
-+#define bCCKTxC5 0x3f000000
-+#define bCCKTxC6 0x3f
-+#define bCCKTxC7 0x3f00
-+#define bCCKDebugPort 0xff0000
-+#define bCCKDACDebug 0x0f000000
-+#define bCCKFalseAlarmEnable 0x8000
-+#define bCCKFalseAlarmRead 0x4000
-+#define bCCKTRSSI 0x7f
-+#define bCCKRxAGCReport 0xfe
-+#define bCCKRxReport_AntSel 0x80000000
-+#define bCCKRxReport_MFOff 0x40000000
-+#define bCCKRxRxReport_SQLoss 0x20000000
-+#define bCCKRxReport_Pktloss 0x10000000
-+#define bCCKRxReport_Lockedbit 0x08000000
-+#define bCCKRxReport_RateError 0x04000000
-+#define bCCKRxReport_RxRate 0x03000000
-+#define bCCKRxFACounterLower 0xff
-+#define bCCKRxFACounterUpper 0xff000000
-+#define bCCKRxHPAGCStart 0xe000
-+#define bCCKRxHPAGCFinal 0x1c00
-+#define bCCKRxFalseAlarmEnable 0x8000
-+#define bCCKFACounterFreeze 0x4000
-+#define bCCKTxPathSel 0x10000000
-+#define bCCKDefaultRxPath 0xc000000
-+#define bCCKOptionRxPath 0x3000000
-+
-+#define RF_T_METER_88E 0x42
-+
-+/* 6. PageE(0xE00) */
-+#define bSTBCEn 0x4 /* Useless */
-+#define bAntennaMapping 0x10
-+#define bNss 0x20
-+#define bCFOAntSumD 0x200
-+#define bPHYCounterReset 0x8000000
-+#define bCFOReportGet 0x4000000
-+#define bOFDMContinueTx 0x10000000
-+#define bOFDMSingleCarrier 0x20000000
-+#define bOFDMSingleTone 0x40000000
-+
-+
-+/*
-+ * Other Definition
-+ * */
-+
-+#define bEnable 0x1 /* Useless */
-+#define bDisable 0x0
-+
-+/* byte endable for srwrite */
-+#define bByte0 0x1 /* Useless */
-+#define bByte1 0x2
-+#define bByte2 0x4
-+#define bByte3 0x8
-+#define bWord0 0x3
-+#define bWord1 0xc
-+#define bDWord 0xf
-+
-+/* for PutRegsetting & GetRegSetting BitMask */
-+#define bMaskByte0 0xff /* Reg 0xc50 rOFDM0_XAAGCCore~0xC6f */
-+#define bMaskByte1 0xff00
-+#define bMaskByte2 0xff0000
-+#define bMaskByte3 0xff000000
-+#define bMaskHWord 0xffff0000
-+#define bMaskLWord 0x0000ffff
-+#define bMaskDWord 0xffffffff
-+#define bMaskH3Bytes 0xffffff00
-+#define bMask12Bits 0xfff
-+#define bMaskH4Bits 0xf0000000
-+#define bMaskOFDM_D 0xffc00000
-+#define bMaskCCK 0x3f3f3f3f
-+#define bMask7bits 0x7f
-+#define bMaskByte2HighNibble 0x00f00000
-+#define bMaskByte3LowNibble 0x0f000000
-+#define bMaskL3Bytes 0x00ffffff
-+
-+/*--------------------------Define Parameters-------------------------------*/
-+
-+
-+#endif
-diff --git linux-5.8/3rdparty/rtl8812au/include/Hal8814PwrSeq.h linux-5.8/3rdparty/rtl8812au/include/Hal8814PwrSeq.h
-new file mode 100644
-index 000000000..020ddbcba
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/include/Hal8814PwrSeq.h
-@@ -0,0 +1,231 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+
-+
-+#ifndef __HAL8814PWRSEQ_H__
-+#define __HAL8814PWRSEQ_H__
-+
-+#include "HalPwrSeqCmd.h"
-+
-+/*
-+ Check document WB-110628-DZ-RTL8195 (Jaguar) Power Architecture-R04.pdf
-+ There are 6 HW Power States:
-+ 0: POFF--Power Off
-+ 1: PDN--Power Down
-+ 2: CARDEMU--Card Emulation
-+ 3: ACT--Active Mode
-+ 4: LPS--Low Power State
-+ 5: SUS--Suspend
-+
-+ The transision from different states are defined below
-+ TRANS_CARDEMU_TO_ACT
-+ TRANS_ACT_TO_CARDEMU
-+ TRANS_CARDEMU_TO_SUS
-+ TRANS_SUS_TO_CARDEMU
-+ TRANS_CARDEMU_TO_PDN
-+ TRANS_ACT_TO_LPS
-+ TRANS_LPS_TO_ACT
-+
-+ TRANS_END
-+*/
-+#define RTL8814A_TRANS_CARDEMU_TO_ACT_STEPS 16
-+#define RTL8814A_TRANS_ACT_TO_CARDEMU_STEPS 20
-+#define RTL8814A_TRANS_CARDEMU_TO_SUS_STEPS 17
-+#define RTL8814A_TRANS_SUS_TO_CARDEMU_STEPS 15
-+#define RTL8814A_TRANS_CARDEMU_TO_PDN_STEPS 17
-+#define RTL8814A_TRANS_PDN_TO_CARDEMU_STEPS 16
-+#define RTL8814A_TRANS_ACT_TO_LPS_STEPS 20
-+#define RTL8814A_TRANS_LPS_TO_ACT_STEPS 15
-+#define RTL8814A_TRANS_END_STEPS 1
-+
-+
-+#define RTL8814A_TRANS_CARDEMU_TO_ACT \
-+ /* format */ \
-+ /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
-+ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0},/* disable SW LPS 0x04[10]=0*/ \
-+ {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, BIT1},/* wait till 0x04[17] = 1 power ready*/ \
-+ {0x002B, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0}, /* ??0x28[24]=1, enable pll phase select*/ \
-+ {0x0015, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT3 | BIT2 | BIT1), (BIT3 | BIT2 | BIT1)},/* 0x14[11:9]=3'b111, OCP current threshold = 1.5A */ \
-+ {0x002D, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x0E, 0x08},/* 0x2C[11:9]=3'b100, select lpf R3 */ \
-+ {0x002D, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x70, 0x50},/* 0x2C[14:12]=3'b101, select lpf Rs*/ \
-+ {0x007B, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6, BIT6},/* 0x78[30]=1'b1, SDM order select*/ \
-+ /*{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0}, */ /* disable HWPDN 0x04[15]=0*/ \
-+ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, 0},/* disable WL suspend*/ \
-+ {0x00F0, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/* */ \
-+ {0x0081, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x30, 0x20},/* */ \
-+ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* polling until return 0*/ \
-+ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT0, 0},/**/
-+
-+#define RTL8814A_TRANS_ACT_TO_CARDEMU \
-+ /* format */ \
-+ /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
-+ {0x0c00, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x04}, /* 0xc00[7:0] = 4 turn off 3-wire */ \
-+ {0x0e00, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x04}, /* 0xe00[7:0] = 4 turn off 3-wire */ \
-+ {0x0002, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0}, /* 0x2[0] = 0 RESET BB, CLOSE RF */ \
-+ {0x0002, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US}, /*Delay 1us*/ \
-+ {0x0002, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0}, /* Whole BB is reset*/ \
-+ {0x1002, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0}, /* 0x2[0] = 0 RESET BB, CLOSE RF */ \
-+ {0x0002, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US}, /*Delay 1us*/ \
-+ {0x1002, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0}, /* Whole BB is reset*/ \
-+ {0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, /*0x1F[7:0] = 0 turn off RF*/ \
-+ /*{0x004E, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},*/ /*0x4C[23] = 0x4E[7] = 0, switch DPDT_SEL_P output from register 0x65[2] */ \
-+ {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x28}, /* 0x07[7:0] = 0x28 sps pwm mode 0x2a for BT coex*/ \
-+ {0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x02, 0}, /*0x8[1] = 0 ANA clk = 500k */ \
-+ /*{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0 | BIT1, 0},*/ /* 0x02[1:0] = 0 reset BB */ \
-+ {0x0066, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0}, /*0x66[7]=0, disable ckreq for gpio7 output SUS */ \
-+ {0x0041, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*0x41[4]=0, disable sic for gpio7 output SUS */ \
-+ {0x0042, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0}, /*0x42[1]=0, disable ckout for gpio7 output SUS */ \
-+ {0x004e, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5}, /*0x4E[5]=1, disable LED2 for gpio7 output SUS */ \
-+ {0x0041, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0}, /*0x41[0]=0, disable uart for gpio7 output SUS */ \
-+ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*0x04[9] = 1 turn off MAC by HW state machine*/ \
-+ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, 0}, /*wait till 0x04[9] = 0 polling until return 0 to disable*/
-+
-+#define RTL8814A_TRANS_CARDEMU_TO_SUS \
-+ /* format */ \
-+ /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
-+ {0x0061, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x0F, 0x0c},\
-+ {0x0061, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x0F, 0x0E},\
-+ {0x0062, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x0F, 0x07},/* gpio11 input mode, gpio10~8 output mode */ \
-+ {0x0045, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/* gpio 0~7 output same value as input ?? */ \
-+ {0x0046, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xff},/* gpio0~7 output mode */ \
-+ {0x0047, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/* 0x47[7:0] = 00 gpio mode */ \
-+ {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/* suspend option all off */ \
-+ {0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5},/*0x14[13] = 1 turn on ZCD */ \
-+ {0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6, BIT6},/* 0x14[14] =1 trun on ZCD */ \
-+ {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4},/*0x23[4] = 1 hpon LDO sleep mode */ \
-+ {0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*0x8[1] = 0 ANA clk = 500k */ \
-+ {0x0091, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xA0, 0xA0}, /* 0x91[7]=1 0x91[5]=1 , disable sps, ldo sleep mode */ \
-+ {0x0070, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, BIT3}, /* 0x70[3]=1 enable mainbias polling */ \
-+ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, BIT3}, /*0x04[11] = 1 enable WL suspend */
-+
-+#define RTL8814A_TRANS_SUS_TO_CARDEMU \
-+ /* format */ \
-+ /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
-+ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, 0}, /*0x04[11] = 0 enable WL suspend*/ \
-+ {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x10, 0},/*0x23[4] = 0 hpon LDO sleep mode leave */ \
-+ {0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6, 0},/* 0x14[14] =0 trun off ZCD */ \
-+ {0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, 0},/*0x14[13] = 0 turn off ZCD */ \
-+ {0x0046, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/* gpio0~7 input mode */ \
-+ {0x0062, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/* gpio11 input mode, gpio10~8 input mode */
-+
-+#define RTL8814A_TRANS_CARDEMU_TO_CARDDIS \
-+ /* format */ \
-+ /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
-+ /**{0x0194, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0}, //0x194[0]=0 , disable 32K clock*/ \
-+ /**{0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x94}, //0x93 = 0x94 , 90[30] =0 enable 500k ANA clock .switch clock from 12M to 500K , 90 [26] =0 disable EEprom loader clock*/ \
-+ {0x0003, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0}, /*0x03[2] = 0, reset 3081*/ \
-+ {0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x01}, /*0x80 = 05h if reload fw, fill the default value of host_CPU handshake field*/ \
-+ {0x0081, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x30}, /*0x80 = 05h if reload fw, fill the default value of host_CPU handshake field*/ \
-+ /*{0x0042, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xF0, 0xcc},*/ \
-+ /*{0x0042, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xF0, 0xEC},*/ \
-+ /*{0x0043, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x07},*/ /* gpio11 input mode, gpio10~8 output mode */ \
-+ {0x0045, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/* gpio 0~7 output same value as input ?? */ \
-+ {0x0046, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xff},/* gpio0~7 output mode */ \
-+ {0x0047, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/* 0x47[7:0] = 00 gpio mode */ \
-+ {0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6, BIT6},/* 0x15[6] =1 trun on ZCD output */ \
-+ {0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5},/*0x15[5] = 1 turn on ZCD */ \
-+ {0x0012, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6, 0},/*0x12[6] = 0 force PFM mode */ \
-+ {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4},/*0x23[4] = 1 hpon LDO sleep mode */ \
-+ {0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*0x8[1] = 0 ANA clk = 500k */ \
-+ {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07 = 0x20 , SOP option to disable BG/MB*/ \
-+ {0x001f, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0}, /* 0x01f[1]=0 , disable RFC_0 control REG_RF_CTRL_8814A */ \
-+ {0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0}, /* 0x020[1]=0 , disable RFC_1 control REG_RF_CTRL_8814A */ \
-+ {0x0021, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0}, /* 0x021[1]=0 , disable RFC_2 control REG_RF_CTRL_8814A */ \
-+ {0x0076, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0}, /* 0x076[1]=0 , disable RFC_3 control REG_OPT_CTRL_8814A +2 */ \
-+ {0x0091, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xA0, 0xA0}, /* 0x91[7]=1 0x91[5]=1 , disable sps, ldo sleep mode */ \
-+ {0x0070, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, BIT3}, /* 0x70[3]=1 enable mainbias polling */ \
-+ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, BIT3}, /*0x04[11] = 1 enable WL suspend*/
-+
-+#define RTL8814A_TRANS_CARDDIS_TO_CARDEMU \
-+ /* format */ \
-+ /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
-+ {0x0012, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6, BIT6},/*0x12[6] = 1 force PWM mode */ \
-+ {0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, 0},/*0x15[5] = 0 turn off ZCD */ \
-+ {0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6, 0},/* 0x15[6] =0 trun off ZCD output */ \
-+ {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0},/*0x23[4] = 0 hpon LDO leave sleep mode */ \
-+ {0x0046, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/* gpio0~7 input mode */ \
-+ {0x0062, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00}, /* gpio11 input mode, gpio10~8 input mode */ \
-+ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0}, /*0x04[10] = 0, enable SW LPS PCIE only*/ \
-+ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, 0}, /*0x04[11] = 0, enable WL suspend*/ \
-+ /*{0x0003, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, BIT2},*/ /*0x03[2] = 1, enable 3081*/ \
-+ {0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/*PCIe DMA start*/ \
-+ {0x0071, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0},/*0x70[10] = 0, CPHY_MBIAS_EN disable*/
-+
-+
-+#define RTL8814A_TRANS_CARDEMU_TO_PDN \
-+ /* format */ \
-+ /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
-+ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7},/* 0x04[15] = 1*/
-+
-+#define RTL8814A_TRANS_PDN_TO_CARDEMU \
-+ /* format */ \
-+ /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
-+ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/* 0x04[15] = 0*/
-+
-+#define RTL8814A_TRANS_ACT_TO_LPS \
-+ /* format */ \
-+ /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
-+ {0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF},/*PCIe DMA stop*/ \
-+ {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x7F},/*Tx Pause*/ \
-+ {0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
-+ {0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
-+ {0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
-+ {0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
-+ {0x0c00, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x04}, /* 0xc00[7:0] = 4 turn off 3-wire */ \
-+ {0x0e00, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x04}, /* 0xe00[7:0] = 4 turn off 3-wire */ \
-+ {0x0002, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled, and clock are gated, and RF closed*/ \
-+ {0x0002, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/ \
-+ {0x0002, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0}, /* Whole BB is reset*/ \
-+ {0x1002, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled, and clock are gated, and RF closed*/ \
-+ {0x0002, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/ \
-+ {0x1002, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0}, /* Whole BB is reset*/ \
-+ {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x03},/*Reset MAC TRX*/ \
-+ {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*check if removed later*/ \
-+ {0x05F1, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/*Respond TxOK to scheduler*/
-+
-+
-+#define RTL8814A_TRANS_LPS_TO_ACT \
-+ /* format */ \
-+ /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
-+ {0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM*/ \
-+ {0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/ \
-+ {0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/ \
-+ {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /* Delay*/ \
-+ {0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*. 0x08[4] = 0 switch TSF to 40M*/ \
-+ {0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT7, 0}, /* Polling 0x109[7]=0 TSF in 40M*/ \
-+ /*{0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6 | BIT7, 0}, */ /*. ??0x29[7:6] = 2b'00 enable BB clock*/ \
-+ {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*. 0x101[1] = 1*/ \
-+ {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF}, /*. 0x100[7:0] = 0xFF enable WMAC TRX*/ \
-+ {0x0002, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1 | BIT0, BIT1 | BIT0}, /*. 0x02[1:0] = 2b'11 enable BB macro*/ \
-+ {0x1002, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1 | BIT0, BIT1 | BIT0}, /*. 0x1002[1:0] = 2b'11 enable BB macro*/ \
-+ {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, /*. 0x522 = 0*/
-+
-+#define RTL8814A_TRANS_END \
-+ /* format */ \
-+ /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
-+ {0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, 0, PWR_CMD_END, 0, 0},
-+
-+
-+extern WLAN_PWR_CFG rtl8814A_power_on_flow[RTL8814A_TRANS_CARDEMU_TO_ACT_STEPS + RTL8814A_TRANS_END_STEPS];
-+extern WLAN_PWR_CFG rtl8814A_radio_off_flow[RTL8814A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8814A_TRANS_END_STEPS];
-+extern WLAN_PWR_CFG rtl8814A_card_disable_flow[RTL8814A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8814A_TRANS_CARDEMU_TO_PDN_STEPS + RTL8814A_TRANS_END_STEPS];
-+extern WLAN_PWR_CFG rtl8814A_card_enable_flow[RTL8814A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8814A_TRANS_CARDEMU_TO_PDN_STEPS + RTL8814A_TRANS_END_STEPS];
-+extern WLAN_PWR_CFG rtl8814A_suspend_flow[RTL8814A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8814A_TRANS_CARDEMU_TO_SUS_STEPS + RTL8814A_TRANS_END_STEPS];
-+extern WLAN_PWR_CFG rtl8814A_resume_flow[RTL8814A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8814A_TRANS_CARDEMU_TO_SUS_STEPS + RTL8814A_TRANS_END_STEPS];
-+extern WLAN_PWR_CFG rtl8814A_hwpdn_flow[RTL8814A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8814A_TRANS_CARDEMU_TO_PDN_STEPS + RTL8814A_TRANS_END_STEPS];
-+extern WLAN_PWR_CFG rtl8814A_enter_lps_flow[RTL8814A_TRANS_ACT_TO_LPS_STEPS + RTL8814A_TRANS_END_STEPS];
-+extern WLAN_PWR_CFG rtl8814A_leave_lps_flow[RTL8814A_TRANS_LPS_TO_ACT_STEPS + RTL8814A_TRANS_END_STEPS];
-+
-+#endif /* __HAL8814PWRSEQ_H__ */
-diff --git linux-5.8/3rdparty/rtl8812au/include/Hal8821APwrSeq.h linux-5.8/3rdparty/rtl8812au/include/Hal8821APwrSeq.h
-new file mode 100644
-index 000000000..568b8e5fc
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/include/Hal8821APwrSeq.h
-@@ -0,0 +1,200 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2016 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef REALTEK_POWER_SEQUENCE_8821
-+#define REALTEK_POWER_SEQUENCE_8821
-+
-+#include "HalPwrSeqCmd.h"
-+
-+/*
-+ Check document WM-20130516-JackieLau-RTL8821A_Power_Architecture-R10.vsd
-+ There are 6 HW Power States:
-+ 0: POFF--Power Off
-+ 1: PDN--Power Down
-+ 2: CARDEMU--Card Emulation
-+ 3: ACT--Active Mode
-+ 4: LPS--Low Power State
-+ 5: SUS--Suspend
-+
-+ The transision from different states are defined below
-+ TRANS_CARDEMU_TO_ACT
-+ TRANS_ACT_TO_CARDEMU
-+ TRANS_CARDEMU_TO_SUS
-+ TRANS_SUS_TO_CARDEMU
-+ TRANS_CARDEMU_TO_PDN
-+ TRANS_ACT_TO_LPS
-+ TRANS_LPS_TO_ACT
-+
-+ TRANS_END
-+*/
-+#define RTL8821A_TRANS_CARDEMU_TO_ACT_STEPS 25
-+#define RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS 15
-+#define RTL8821A_TRANS_CARDEMU_TO_SUS_STEPS 15
-+#define RTL8821A_TRANS_SUS_TO_CARDEMU_STEPS 15
-+#define RTL8821A_TRANS_CARDDIS_TO_CARDEMU_STEPS 15
-+#define RTL8821A_TRANS_CARDEMU_TO_PDN_STEPS 15
-+#define RTL8821A_TRANS_PDN_TO_CARDEMU_STEPS 15
-+#define RTL8821A_TRANS_ACT_TO_LPS_STEPS 15
-+#define RTL8821A_TRANS_LPS_TO_ACT_STEPS 15
-+#define RTL8821A_TRANS_END_STEPS 1
-+
-+
-+#define RTL8821A_TRANS_CARDEMU_TO_ACT \
-+ /* format */ \
-+ /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
-+ {0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0}, /*0x20[0] = 1b'1 enable LDOA12 MACRO block for all interface*/ \
-+ {0x0067, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*0x67[0] = 0 to disable BT_GPS_SEL pins*/ \
-+ {0x0001, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 1, PWRSEQ_DELAY_MS},/*Delay 1ms*/ \
-+ {0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, 0}, /*0x00[5] = 1b'0 release analog Ips to digital ,1:isolation*/ \
-+ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT4 | BIT3 | BIT2), 0},/* disable SW LPS 0x04[10]=0 and WLSUS_EN 0x04[12:11]=0*/ \
-+ {0x0075, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0 , BIT0},/* Disable USB suspend */ \
-+ {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, BIT1},/* wait till 0x04[17] = 1 power ready*/ \
-+ {0x0075, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0 , 0},/* Enable USB suspend */ \
-+ {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* release WLON reset 0x04[16]=1*/ \
-+ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/* disable HWPDN 0x04[15]=0*/ \
-+ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT4 | BIT3), 0},/* disable WL suspend*/ \
-+ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* polling until return 0*/ \
-+ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT0, 0},/**/ \
-+ {0x004F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/*0x4C[24] = 0x4F[0] = 1, switch DPDT_SEL_P output from WL BB */\
-+ {0x0067, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT5 | BIT4), (BIT5 | BIT4)},/*0x66[13] = 0x67[5] = 1, switch for PAPE_G/PAPE_A from WL BB ; 0x66[12] = 0x67[4] = 1, switch LNAON from WL BB */\
-+ {0x0025, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6, 0},/*anapar_mac<118> , 0x25[6]=0 by wlan single function*/\
-+ {0x0049, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1},/*Enable falling edge triggering interrupt*/\
-+ {0x0063, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1},/*Enable GPIO9 interrupt mode*/\
-+ {0x0062, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*Enable GPIO9 input mode*/\
-+ {0x0058, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/*Enable HSISR GPIO[C:0] interrupt*/\
-+ {0x005A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1},/*Enable HSISR GPIO9 interrupt*/\
-+ {0x007A, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x3A},/*0x7A = 0x3A start BT*/\
-+ {0x002E, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF , 0x82 },/* 0x2C[23:12]=0x820 ; XTAL trim */ \
-+ {0x0010, PWR_CUT_A_MSK , PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6 , BIT6 },/* 0x10[6]=1 ; MP·s¼W¹ï©ó0x2Cªº±±¨îÅv¡A¶·§â0x10[6]³]¬°1¤~¯àÅýWLAN±±¨î */ \
-+
-+
-+#define RTL8821A_TRANS_ACT_TO_CARDEMU \
-+ /* format */ \
-+ /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
-+ {0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/*0x1F[7:0] = 0 turn off RF*/ \
-+ {0x004F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*0x4C[24] = 0x4F[0] = 0, switch DPDT_SEL_P output from register 0x65[2] */\
-+ {0x0049, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*Enable rising edge triggering interrupt*/ \
-+ {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* release WLON reset 0x04[16]=1*/ \
-+ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*0x04[9] = 1 turn off MAC by HW state machine*/ \
-+ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, 0}, /*wait till 0x04[9] = 0 polling until return 0 to disable*/ \
-+ {0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5}, /*0x00[5] = 1b'1 analog Ips to digital ,1:isolation*/ \
-+ {0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0}, /*0x20[0] = 1b'0 disable LDOA12 MACRO block*/ \
-+
-+
-+#define RTL8821A_TRANS_CARDEMU_TO_SUS \
-+ /* format */ \
-+ /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
-+ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4 | BIT3, (BIT4 | BIT3)}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \
-+ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/ \
-+ {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/ \
-+ {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SDIO SOP option to disable BG/MB/ACK/SWR*/ \
-+ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, BIT3 | BIT4}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \
-+ {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/ \
-+ {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/
-+
-+#define RTL8821A_TRANS_SUS_TO_CARDEMU \
-+ /* format */ \
-+ /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
-+ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT7, 0}, /*clear suspend enable and power down enable*/ \
-+ {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/ \
-+ {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\
-+ {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*0x23[4] = 1b'0 12H LDO enter normal mode*/ \
-+ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/
-+
-+#define RTL8821A_TRANS_CARDEMU_TO_CARDDIS \
-+ /* format */ \
-+ /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
-+ {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07 = 0x20 , SOP option to disable BG/MB*/ \
-+ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/ \
-+ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, BIT2}, /*0x04[10] = 1, enable SW LPS*/ \
-+ {0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 1}, /*0x48[16] = 1 to enable GPIO9 as EXT WAKEUP*/ \
-+ {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/ \
-+ {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/ \
-+ {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/
-+
-+#define RTL8821A_TRANS_CARDDIS_TO_CARDEMU \
-+ /* format */ \
-+ /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
-+ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT7, 0}, /*clear suspend enable and power down enable*/ \
-+ {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/ \
-+ {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\
-+ {0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0}, /*0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/ \
-+ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/\
-+ {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*0x23[4] = 1b'0 12H LDO enter normal mode*/ \
-+ {0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/*PCIe DMA start*/
-+
-+
-+#define RTL8821A_TRANS_CARDEMU_TO_PDN \
-+ /* format */ \
-+ /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
-+ {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/ \
-+ {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK | PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SOP option to disable BG/MB/ACK/SWR*/ \
-+ {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/* 0x04[16] = 0*/\
-+ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7},/* 0x04[15] = 1*/
-+
-+#define RTL8821A_TRANS_PDN_TO_CARDEMU \
-+ /* format */ \
-+ /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
-+ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/* 0x04[15] = 0*/
-+
-+#define RTL8821A_TRANS_ACT_TO_LPS \
-+ /* format */ \
-+ /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
-+ {0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF},/*PCIe DMA stop*/ \
-+ {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF},/*Tx Pause*/ \
-+ {0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
-+ {0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
-+ {0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
-+ {0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
-+ {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled, and clock are gated*/ \
-+ {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/ \
-+ {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*Whole BB is reset*/ \
-+ {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x03},/*Reset MAC TRX*/ \
-+ {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*check if removed later*/ \
-+ {0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/*When driver enter Sus/ Disable, enable LOP for BT*/ \
-+ {0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5},/*Respond TxOK to scheduler*/ \
-+
-+
-+#define RTL8821A_TRANS_LPS_TO_ACT \
-+ /* format */ \
-+ /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
-+ {0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM*/\
-+ {0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/\
-+ {0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/\
-+ {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /*Delay*/\
-+ {0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*. 0x08[4] = 0 switch TSF to 40M*/\
-+ {0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT7, 0}, /*Polling 0x109[7]=0 TSF in 40M*/\
-+ {0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6 | BIT7, 0}, /*. 0x29[7:6] = 2b'00 enable BB clock*/\
-+ {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*. 0x101[1] = 1*/\
-+ {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF}, /*. 0x100[7:0] = 0xFF enable WMAC TRX*/\
-+ {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1 | BIT0, BIT1 | BIT0}, /*. 0x02[1:0] = 2b'11 enable BB macro*/\
-+ {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, /*. 0x522 = 0*/
-+
-+#define RTL8821A_TRANS_END \
-+ /* format */ \
-+ /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
-+ {0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, 0, PWR_CMD_END, 0, 0},
-+
-+
-+ extern WLAN_PWR_CFG rtl8821A_power_on_flow[RTL8821A_TRANS_CARDEMU_TO_ACT_STEPS + RTL8821A_TRANS_END_STEPS];
-+ extern WLAN_PWR_CFG rtl8821A_radio_off_flow[RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8821A_TRANS_END_STEPS];
-+ extern WLAN_PWR_CFG rtl8821A_card_disable_flow[RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8821A_TRANS_CARDEMU_TO_PDN_STEPS + RTL8821A_TRANS_END_STEPS];
-+ extern WLAN_PWR_CFG rtl8821A_card_enable_flow[RTL8821A_TRANS_CARDDIS_TO_CARDEMU_STEPS + RTL8821A_TRANS_CARDEMU_TO_ACT_STEPS + RTL8821A_TRANS_END_STEPS];
-+ extern WLAN_PWR_CFG rtl8821A_suspend_flow[RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8821A_TRANS_CARDEMU_TO_SUS_STEPS + RTL8821A_TRANS_END_STEPS];
-+ extern WLAN_PWR_CFG rtl8821A_resume_flow[RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8821A_TRANS_CARDEMU_TO_SUS_STEPS + RTL8821A_TRANS_END_STEPS];
-+ extern WLAN_PWR_CFG rtl8821A_hwpdn_flow[RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8821A_TRANS_CARDEMU_TO_PDN_STEPS + RTL8821A_TRANS_END_STEPS];
-+ extern WLAN_PWR_CFG rtl8821A_enter_lps_flow[RTL8821A_TRANS_ACT_TO_LPS_STEPS + RTL8821A_TRANS_END_STEPS];
-+ extern WLAN_PWR_CFG rtl8821A_leave_lps_flow[RTL8821A_TRANS_LPS_TO_ACT_STEPS + RTL8821A_TRANS_END_STEPS];
-+
-+#endif
-diff --git linux-5.8/3rdparty/rtl8812au/include/HalPwrSeqCmd.h linux-5.8/3rdparty/rtl8812au/include/HalPwrSeqCmd.h
-new file mode 100644
-index 000000000..f67ed22d1
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/include/HalPwrSeqCmd.h
-@@ -0,0 +1,130 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __HALPWRSEQCMD_H__
-+#define __HALPWRSEQCMD_H__
-+
-+#include
-+
-+/*---------------------------------------------*/
-+/* 3 The value of cmd: 4 bits
-+ *---------------------------------------------*/
-+#define PWR_CMD_READ 0x00
-+/* offset: the read register offset
-+ * msk: the mask of the read value
-+ * value: N/A, left by 0
-+ * note: dirver shall implement this function by read & msk */
-+
-+#define PWR_CMD_WRITE 0x01
-+/* offset: the read register offset
-+ * msk: the mask of the write bits
-+ * value: write value
-+ * note: driver shall implement this cmd by read & msk after write */
-+
-+#define PWR_CMD_POLLING 0x02
-+/* offset: the read register offset
-+ * msk: the mask of the polled value
-+ * value: the value to be polled, masked by the msd field.
-+ * note: driver shall implement this cmd by
-+ * do {
-+ * if( (Read(offset) & msk) == (value & msk) )
-+ * break;
-+ * } while(not timeout); */
-+
-+#define PWR_CMD_DELAY 0x03
-+/* offset: the value to delay
-+ * msk: N/A
-+ * value: the unit of delay, 0: us, 1: ms */
-+
-+#define PWR_CMD_END 0x04
-+/* offset: N/A
-+ * msk: N/A
-+ * value: N/A */
-+
-+/*---------------------------------------------*/
-+/* 3 The value of base: 4 bits
-+ *---------------------------------------------
-+ * define the base address of each block */
-+#define PWR_BASEADDR_MAC 0x00
-+#define PWR_BASEADDR_USB 0x01
-+#define PWR_BASEADDR_PCIE 0x02
-+#define PWR_BASEADDR_SDIO 0x03
-+
-+/*---------------------------------------------*/
-+/* 3 The value of interface_msk: 4 bits
-+ *---------------------------------------------*/
-+#define PWR_INTF_SDIO_MSK BIT(0)
-+#define PWR_INTF_USB_MSK BIT(1)
-+#define PWR_INTF_PCI_MSK BIT(2)
-+#define PWR_INTF_ALL_MSK (BIT(0) | BIT(1) | BIT(2) | BIT(3))
-+
-+/*---------------------------------------------*/
-+/* 3 The value of fab_msk: 4 bits
-+ *---------------------------------------------*/
-+#define PWR_FAB_TSMC_MSK BIT(0)
-+#define PWR_FAB_UMC_MSK BIT(1)
-+#define PWR_FAB_ALL_MSK (BIT(0) | BIT(1) | BIT(2) | BIT(3))
-+
-+/*---------------------------------------------*/
-+/* 3 The value of cut_msk: 8 bits
-+ *---------------------------------------------*/
-+#define PWR_CUT_TESTCHIP_MSK BIT(0)
-+#define PWR_CUT_A_MSK BIT(1)
-+#define PWR_CUT_B_MSK BIT(2)
-+#define PWR_CUT_C_MSK BIT(3)
-+#define PWR_CUT_D_MSK BIT(4)
-+#define PWR_CUT_E_MSK BIT(5)
-+#define PWR_CUT_F_MSK BIT(6)
-+#define PWR_CUT_G_MSK BIT(7)
-+#define PWR_CUT_ALL_MSK 0xFF
-+
-+
-+typedef enum _PWRSEQ_CMD_DELAY_UNIT_ {
-+ PWRSEQ_DELAY_US,
-+ PWRSEQ_DELAY_MS,
-+} PWRSEQ_DELAY_UNIT;
-+
-+typedef struct _WL_PWR_CFG_ {
-+ u16 offset;
-+ u8 cut_msk;
-+ u8 fab_msk:4;
-+ u8 interface_msk:4;
-+ u8 base:4;
-+ u8 cmd:4;
-+ u8 msk;
-+ u8 value;
-+} WLAN_PWR_CFG, *PWLAN_PWR_CFG;
-+
-+
-+#define GET_PWR_CFG_OFFSET(__PWR_CMD) ((__PWR_CMD).offset)
-+#define GET_PWR_CFG_CUT_MASK(__PWR_CMD) ((__PWR_CMD).cut_msk)
-+#define GET_PWR_CFG_FAB_MASK(__PWR_CMD) ((__PWR_CMD).fab_msk)
-+#define GET_PWR_CFG_INTF_MASK(__PWR_CMD) ((__PWR_CMD).interface_msk)
-+#define GET_PWR_CFG_BASE(__PWR_CMD) ((__PWR_CMD).base)
-+#define GET_PWR_CFG_CMD(__PWR_CMD) ((__PWR_CMD).cmd)
-+#define GET_PWR_CFG_MASK(__PWR_CMD) ((__PWR_CMD).msk)
-+#define GET_PWR_CFG_VALUE(__PWR_CMD) ((__PWR_CMD).value)
-+
-+
-+/* ********************************************************************************
-+ * Prototype of protected function.
-+ * ******************************************************************************** */
-+u8 HalPwrSeqCmdParsing(
-+ PADAPTER padapter,
-+ u8 CutVersion,
-+ u8 FabVersion,
-+ u8 InterfaceType,
-+ WLAN_PWR_CFG PwrCfgCmd[]);
-+
-+#endif
-diff --git linux-5.8/3rdparty/rtl8812au/include/HalVerDef.h linux-5.8/3rdparty/rtl8812au/include/HalVerDef.h
-new file mode 100644
-index 000000000..ab1c578db
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/include/HalVerDef.h
-@@ -0,0 +1,201 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __HAL_VERSION_DEF_H__
-+#define __HAL_VERSION_DEF_H__
-+
-+#define TRUE _TRUE
-+#define FALSE _FALSE
-+
-+/* HAL_IC_TYPE_E */
-+typedef enum tag_HAL_IC_Type_Definition {
-+ CHIP_8192S = 0,
-+ CHIP_8188C = 1,
-+ CHIP_8192C = 2,
-+ CHIP_8192D = 3,
-+ CHIP_8723A = 4,
-+ CHIP_8188E = 5,
-+ CHIP_8812 = 6,
-+ CHIP_8821 = 7,
-+ CHIP_8723B = 8,
-+ CHIP_8192E = 9,
-+ CHIP_8814A = 10,
-+ CHIP_8703B = 11,
-+ CHIP_8188F = 12,
-+ CHIP_8822B = 13,
-+ CHIP_8723D = 14,
-+ CHIP_8821C = 15,
-+ CHIP_8710B = 16,
-+ CHIP_8192F = 17,
-+ CHIP_8188GTV = 18,
-+} HAL_IC_TYPE_E;
-+
-+/* HAL_CHIP_TYPE_E */
-+typedef enum tag_HAL_CHIP_Type_Definition {
-+ TEST_CHIP = 0,
-+ NORMAL_CHIP = 1,
-+ FPGA = 2,
-+} HAL_CHIP_TYPE_E;
-+
-+/* HAL_CUT_VERSION_E */
-+typedef enum tag_HAL_Cut_Version_Definition {
-+ A_CUT_VERSION = 0,
-+ B_CUT_VERSION = 1,
-+ C_CUT_VERSION = 2,
-+ D_CUT_VERSION = 3,
-+ E_CUT_VERSION = 4,
-+ F_CUT_VERSION = 5,
-+ G_CUT_VERSION = 6,
-+ H_CUT_VERSION = 7,
-+ I_CUT_VERSION = 8,
-+ J_CUT_VERSION = 9,
-+ K_CUT_VERSION = 10,
-+} HAL_CUT_VERSION_E;
-+
-+/* HAL_Manufacturer */
-+typedef enum tag_HAL_Manufacturer_Version_Definition {
-+ CHIP_VENDOR_TSMC = 0,
-+ CHIP_VENDOR_UMC = 1,
-+ CHIP_VENDOR_SMIC = 2,
-+} HAL_VENDOR_E;
-+
-+typedef enum tag_HAL_RF_Type_Definition {
-+ RF_TYPE_1T1R = 0,
-+ RF_TYPE_1T2R = 1,
-+ RF_TYPE_2T2R = 2,
-+ RF_TYPE_2T3R = 3,
-+ RF_TYPE_2T4R = 4,
-+ RF_TYPE_3T3R = 5,
-+ RF_TYPE_3T4R = 6,
-+ RF_TYPE_4T4R = 7,
-+} HAL_RF_TYPE_E;
-+
-+typedef struct tag_HAL_VERSION {
-+ HAL_IC_TYPE_E ICType;
-+ HAL_CHIP_TYPE_E ChipType;
-+ HAL_CUT_VERSION_E CUTVersion;
-+ HAL_VENDOR_E VendorType;
-+ HAL_RF_TYPE_E RFType;
-+ u8 ROMVer;
-+} HAL_VERSION, *PHAL_VERSION;
-+
-+/* VERSION_8192C VersionID;
-+ * HAL_VERSION VersionID; */
-+
-+/* Get element */
-+#define GET_CVID_IC_TYPE(version) ((HAL_IC_TYPE_E)(((HAL_VERSION)version).ICType))
-+#define GET_CVID_CHIP_TYPE(version) ((HAL_CHIP_TYPE_E)(((HAL_VERSION)version).ChipType))
-+#define GET_CVID_RF_TYPE(version) ((HAL_RF_TYPE_E)(((HAL_VERSION)version).RFType))
-+#define GET_CVID_MANUFACTUER(version) ((HAL_VENDOR_E)(((HAL_VERSION)version).VendorType))
-+#define GET_CVID_CUT_VERSION(version) ((HAL_CUT_VERSION_E)(((HAL_VERSION)version).CUTVersion))
-+#define GET_CVID_ROM_VERSION(version) ((((HAL_VERSION)version).ROMVer) & ROM_VERSION_MASK)
-+
-+/* ----------------------------------------------------------------------------
-+ * Common Macro. --
-+ * ----------------------------------------------------------------------------
-+ * HAL_VERSION VersionID */
-+
-+/* HAL_IC_TYPE_E */
-+#if 0
-+ #define IS_81XXC(version) (((GET_CVID_IC_TYPE(version) == CHIP_8192C) || (GET_CVID_IC_TYPE(version) == CHIP_8188C)) ? TRUE : FALSE)
-+ #define IS_8723_SERIES(version) ((GET_CVID_IC_TYPE(version) == CHIP_8723A) ? TRUE : FALSE)
-+ #define IS_92D(version) ((GET_CVID_IC_TYPE(version) == CHIP_8192D) ? TRUE : FALSE)
-+#endif
-+
-+#define IS_8188E(version) ((GET_CVID_IC_TYPE(version) == CHIP_8188E) ? TRUE : FALSE)
-+#define IS_8188F(version) ((GET_CVID_IC_TYPE(version) == CHIP_8188F) ? TRUE : FALSE)
-+#define IS_8188GTV(version) ((GET_CVID_IC_TYPE(version) == CHIP_8188GTV) ? TRUE : FALSE)
-+#define IS_8192E(version) ((GET_CVID_IC_TYPE(version) == CHIP_8192E) ? TRUE : FALSE)
-+#define IS_8812_SERIES(version) ((GET_CVID_IC_TYPE(version) == CHIP_8812) ? TRUE : FALSE)
-+#define IS_8821_SERIES(version) ((GET_CVID_IC_TYPE(version) == CHIP_8821) ? TRUE : FALSE)
-+#define IS_8814A_SERIES(version) ((GET_CVID_IC_TYPE(version) == CHIP_8814A) ? TRUE : FALSE)
-+#define IS_8723B_SERIES(version) ((GET_CVID_IC_TYPE(version) == CHIP_8723B) ? TRUE : FALSE)
-+#define IS_8703B_SERIES(version) ((GET_CVID_IC_TYPE(version) == CHIP_8703B) ? TRUE : FALSE)
-+#define IS_8822B_SERIES(version) ((GET_CVID_IC_TYPE(version) == CHIP_8822B) ? TRUE : FALSE)
-+#define IS_8821C_SERIES(version) ((GET_CVID_IC_TYPE(version) == CHIP_8821C) ? TRUE : FALSE)
-+#define IS_8723D_SERIES(version) ((GET_CVID_IC_TYPE(version) == CHIP_8723D) ? TRUE : FALSE)
-+#define IS_8710B_SERIES(version) ((GET_CVID_IC_TYPE(version) == CHIP_8710B) ? TRUE : FALSE)
-+
-+#define IS_8192F_SERIES(version)\
-+ ((GET_CVID_IC_TYPE(version) == CHIP_8192F) ? TRUE : FALSE)
-+/* HAL_CHIP_TYPE_E */
-+#define IS_TEST_CHIP(version) ((GET_CVID_CHIP_TYPE(version) == TEST_CHIP) ? TRUE : FALSE)
-+#define IS_NORMAL_CHIP(version) ((GET_CVID_CHIP_TYPE(version) == NORMAL_CHIP) ? TRUE : FALSE)
-+
-+/* HAL_CUT_VERSION_E */
-+#define IS_A_CUT(version) ((GET_CVID_CUT_VERSION(version) == A_CUT_VERSION) ? TRUE : FALSE)
-+#define IS_B_CUT(version) ((GET_CVID_CUT_VERSION(version) == B_CUT_VERSION) ? TRUE : FALSE)
-+#define IS_C_CUT(version) ((GET_CVID_CUT_VERSION(version) == C_CUT_VERSION) ? TRUE : FALSE)
-+#define IS_D_CUT(version) ((GET_CVID_CUT_VERSION(version) == D_CUT_VERSION) ? TRUE : FALSE)
-+#define IS_E_CUT(version) ((GET_CVID_CUT_VERSION(version) == E_CUT_VERSION) ? TRUE : FALSE)
-+#define IS_F_CUT(version) ((GET_CVID_CUT_VERSION(version) == F_CUT_VERSION) ? TRUE : FALSE)
-+#define IS_I_CUT(version) ((GET_CVID_CUT_VERSION(version) == I_CUT_VERSION) ? TRUE : FALSE)
-+#define IS_J_CUT(version) ((GET_CVID_CUT_VERSION(version) == J_CUT_VERSION) ? TRUE : FALSE)
-+#define IS_K_CUT(version) ((GET_CVID_CUT_VERSION(version) == K_CUT_VERSION) ? TRUE : FALSE)
-+
-+/* HAL_VENDOR_E */
-+#define IS_CHIP_VENDOR_TSMC(version) ((GET_CVID_MANUFACTUER(version) == CHIP_VENDOR_TSMC) ? TRUE : FALSE)
-+#define IS_CHIP_VENDOR_UMC(version) ((GET_CVID_MANUFACTUER(version) == CHIP_VENDOR_UMC) ? TRUE : FALSE)
-+#define IS_CHIP_VENDOR_SMIC(version) ((GET_CVID_MANUFACTUER(version) == CHIP_VENDOR_SMIC) ? TRUE : FALSE)
-+
-+/* HAL_RF_TYPE_E */
-+#define IS_1T1R(version) ((GET_CVID_RF_TYPE(version) == RF_TYPE_1T1R) ? TRUE : FALSE)
-+#define IS_1T2R(version) ((GET_CVID_RF_TYPE(version) == RF_TYPE_1T2R) ? TRUE : FALSE)
-+#define IS_2T2R(version) ((GET_CVID_RF_TYPE(version) == RF_TYPE_2T2R) ? TRUE : FALSE)
-+#define IS_3T3R(version) ((GET_CVID_RF_TYPE(version) == RF_TYPE_3T3R) ? TRUE : FALSE)
-+#define IS_3T4R(version) ((GET_CVID_RF_TYPE(version) == RF_TYPE_3T4R) ? TRUE : FALSE)
-+#define IS_4T4R(version) ((GET_CVID_RF_TYPE(version) == RF_TYPE_4T4R) ? TRUE : FALSE)
-+
-+
-+
-+/* ----------------------------------------------------------------------------
-+ * Chip version Macro. --
-+ * ---------------------------------------------------------------------------- */
-+#if 0
-+ #define IS_81XXC_TEST_CHIP(version) ((IS_81XXC(version) && (!IS_NORMAL_CHIP(version))) ? TRUE : FALSE)
-+
-+ #define IS_92C_SERIAL(version) ((IS_81XXC(version) && IS_2T2R(version)) ? TRUE : FALSE)
-+ #define IS_81xxC_VENDOR_UMC_A_CUT(version) (IS_81XXC(version) ? (IS_CHIP_VENDOR_UMC(version) ? (IS_A_CUT(version) ? TRUE : FALSE) : FALSE) : FALSE)
-+ #define IS_81xxC_VENDOR_UMC_B_CUT(version) (IS_81XXC(version) ? (IS_CHIP_VENDOR_UMC(version) ? (IS_B_CUT(version) ? TRUE : FALSE) : FALSE) : FALSE)
-+ #define IS_81xxC_VENDOR_UMC_C_CUT(version) (IS_81XXC(version) ? (IS_CHIP_VENDOR_UMC(version) ? (IS_C_CUT(version) ? TRUE : FALSE) : FALSE) : FALSE)
-+
-+ #define IS_NORMAL_CHIP92D(version) ((IS_92D(version)) ? ((GET_CVID_CHIP_TYPE(version) == NORMAL_CHIP) ? TRUE : FALSE) : FALSE)
-+
-+ #define IS_92D_SINGLEPHY(version) ((IS_92D(version)) ? (IS_2T2R(version) ? TRUE : FALSE) : FALSE)
-+ #define IS_92D_C_CUT(version) ((IS_92D(version)) ? (IS_C_CUT(version) ? TRUE : FALSE) : FALSE)
-+ #define IS_92D_D_CUT(version) ((IS_92D(version)) ? (IS_D_CUT(version) ? TRUE : FALSE) : FALSE)
-+ #define IS_92D_E_CUT(version) ((IS_92D(version)) ? (IS_E_CUT(version) ? TRUE : FALSE) : FALSE)
-+
-+ #define IS_8723A_A_CUT(version) ((IS_8723_SERIES(version)) ? (IS_A_CUT(version) ? TRUE : FALSE) : FALSE)
-+ #define IS_8723A_B_CUT(version) ((IS_8723_SERIES(version)) ? (IS_B_CUT(version) ? TRUE : FALSE) : FALSE)
-+#endif
-+#define IS_VENDOR_8188E_I_CUT_SERIES(_Adapter) ((IS_8188E(GET_HAL_DATA(_Adapter)->version_id)) ? ((GET_CVID_CUT_VERSION(GET_HAL_DATA(_Adapter)->version_id) >= I_CUT_VERSION) ? TRUE : FALSE) : FALSE)
-+#define IS_VENDOR_8812A_TEST_CHIP(_Adapter) ((IS_8812_SERIES(GET_HAL_DATA(_Adapter)->version_id)) ? ((IS_NORMAL_CHIP(GET_HAL_DATA(_Adapter)->version_id)) ? FALSE : TRUE) : FALSE)
-+#define IS_VENDOR_8812A_MP_CHIP(_Adapter) ((IS_8812_SERIES(GET_HAL_DATA(_Adapter)->version_id)) ? ((IS_NORMAL_CHIP(GET_HAL_DATA(_Adapter)->version_id)) ? TRUE : FALSE) : FALSE)
-+#define IS_VENDOR_8812A_C_CUT(_Adapter) ((IS_8812_SERIES(GET_HAL_DATA(_Adapter)->version_id)) ? ((GET_CVID_CUT_VERSION(GET_HAL_DATA(_Adapter)->version_id) == C_CUT_VERSION) ? TRUE : FALSE) : FALSE)
-+
-+#define IS_VENDOR_8821A_TEST_CHIP(_Adapter) ((IS_8821_SERIES(GET_HAL_DATA(_Adapter)->version_id)) ? ((IS_NORMAL_CHIP(GET_HAL_DATA(_Adapter)->version_id)) ? FALSE : TRUE) : FALSE)
-+#define IS_VENDOR_8821A_MP_CHIP(_Adapter) ((IS_8821_SERIES(GET_HAL_DATA(_Adapter)->version_id)) ? ((IS_NORMAL_CHIP(GET_HAL_DATA(_Adapter)->version_id)) ? TRUE : FALSE) : FALSE)
-+
-+#define IS_VENDOR_8192E_B_CUT(_Adapter) ((GET_CVID_CUT_VERSION(GET_HAL_DATA(_Adapter)->version_id) == B_CUT_VERSION) ? TRUE : FALSE)
-+
-+#define IS_VENDOR_8723B_TEST_CHIP(_Adapter) ((IS_8723B_SERIES(GET_HAL_DATA(_Adapter)->version_id)) ? ((IS_NORMAL_CHIP(GET_HAL_DATA(_Adapter)->version_id)) ? FALSE : TRUE) : FALSE)
-+#define IS_VENDOR_8723B_MP_CHIP(_Adapter) ((IS_8723B_SERIES(GET_HAL_DATA(_Adapter)->version_id)) ? ((IS_NORMAL_CHIP(GET_HAL_DATA(_Adapter)->version_id)) ? TRUE : FALSE) : FALSE)
-+
-+#define IS_VENDOR_8703B_TEST_CHIP(_Adapter) ((IS_8703B_SERIES(GET_HAL_DATA(_Adapter)->version_id)) ? ((IS_NORMAL_CHIP(GET_HAL_DATA(_Adapter)->version_id)) ? FALSE : TRUE) : FALSE)
-+#define IS_VENDOR_8703B_MP_CHIP(_Adapter) ((IS_8703B_SERIES(GET_HAL_DATA(_Adapter)->version_id)) ? ((IS_NORMAL_CHIP(GET_HAL_DATA(_Adapter)->version_id)) ? TRUE : FALSE) : FALSE)
-+#define IS_VENDOR_8814A_TEST_CHIP(_Adapter) ((IS_8814A_SERIES(GET_HAL_DATA(_Adapter)->version_id)) ? ((IS_NORMAL_CHIP(GET_HAL_DATA(_Adapter)->version_id)) ? FALSE : TRUE) : FALSE)
-+#define IS_VENDOR_8814A_MP_CHIP(_Adapter) ((IS_8814A_SERIES(GET_HAL_DATA(_Adapter)->version_id)) ? ((IS_NORMAL_CHIP(GET_HAL_DATA(_Adapter)->version_id)) ? TRUE : FALSE) : FALSE)
-+
-+#endif
-diff --git linux-5.8/3rdparty/rtl8812au/include/basic_types.h linux-5.8/3rdparty/rtl8812au/include/basic_types.h
-new file mode 100644
-index 000000000..a324abaf9
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/include/basic_types.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/include/basic_types.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/include/basic_types.h
+--- linux-5.11.4/3rdparty/rtl8812au/include/basic_types.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/include/basic_types.h 2021-03-07 18:16:17.084957471 +0200
@@ -0,0 +1,379 @@
+/******************************************************************************
+ *
@@ -372904,11 +366503,9 @@ index 000000000..a324abaf9
+#define TEST_FLAGS(__Flag, __testFlags) (((__Flag) & (__testFlags)) == (__testFlags))
+
+#endif /* __BASIC_TYPES_H__ */
-diff --git linux-5.8/3rdparty/rtl8812au/include/byteorder/big_endian.h linux-5.8/3rdparty/rtl8812au/include/byteorder/big_endian.h
-new file mode 100644
-index 000000000..6b1dc449e
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/include/byteorder/big_endian.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/include/byteorder/big_endian.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/include/byteorder/big_endian.h
+--- linux-5.11.4/3rdparty/rtl8812au/include/byteorder/big_endian.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/include/byteorder/big_endian.h 2021-03-07 18:16:17.084957471 +0200
@@ -0,0 +1,82 @@
+/******************************************************************************
+ *
@@ -372992,11 +366589,9 @@ index 000000000..6b1dc449e
+#include
+
+#endif /* _LINUX_BYTEORDER_BIG_ENDIAN_H */
-diff --git linux-5.8/3rdparty/rtl8812au/include/byteorder/generic.h linux-5.8/3rdparty/rtl8812au/include/byteorder/generic.h
-new file mode 100644
-index 000000000..f85114bf7
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/include/byteorder/generic.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/include/byteorder/generic.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/include/byteorder/generic.h
+--- linux-5.11.4/3rdparty/rtl8812au/include/byteorder/generic.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/include/byteorder/generic.h 2021-03-07 18:16:17.084957471 +0200
@@ -0,0 +1,207 @@
+/******************************************************************************
+ *
@@ -373205,11 +366800,9 @@ index 000000000..f85114bf7
+#endif
+
+#endif /* _LINUX_BYTEORDER_GENERIC_H */
-diff --git linux-5.8/3rdparty/rtl8812au/include/byteorder/little_endian.h linux-5.8/3rdparty/rtl8812au/include/byteorder/little_endian.h
-new file mode 100644
-index 000000000..c4b64512f
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/include/byteorder/little_endian.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/include/byteorder/little_endian.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/include/byteorder/little_endian.h
+--- linux-5.11.4/3rdparty/rtl8812au/include/byteorder/little_endian.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/include/byteorder/little_endian.h 2021-03-07 18:16:17.084957471 +0200
@@ -0,0 +1,84 @@
+/******************************************************************************
+ *
@@ -373295,153 +366888,9 @@ index 000000000..c4b64512f
+#include
+
+#endif /* _LINUX_BYTEORDER_LITTLE_ENDIAN_H */
-diff --git linux-5.8/3rdparty/rtl8812au/include/byteorder/swab.h linux-5.8/3rdparty/rtl8812au/include/byteorder/swab.h
-new file mode 100644
-index 000000000..a8dd46bd3
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/include/byteorder/swab.h
-@@ -0,0 +1,136 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef _LINUX_BYTEORDER_SWAB_H
-+#define _LINUX_BYTEORDER_SWAB_H
-+
-+#if !defined(CONFIG_PLATFORM_MSTAR)
-+#ifndef __u16
-+ typedef unsigned short __u16;
-+#endif
-+
-+#ifndef __u32
-+ typedef unsigned int __u32;
-+#endif
-+
-+#ifndef __u8
-+ typedef unsigned char __u8;
-+#endif
-+
-+#ifndef __u64
-+ typedef unsigned long long __u64;
-+#endif
-+
-+
-+__inline static __u16 ___swab16(__u16 x)
-+{
-+ __u16 __x = x;
-+ return
-+ (__u16)(
-+ (((__u16)(__x)&(__u16)0x00ffU) << 8) |
-+ (((__u16)(__x)&(__u16)0xff00U) >> 8));
-+
-+}
-+
-+__inline static __u32 ___swab32(__u32 x)
-+{
-+ __u32 __x = (x);
-+ return (__u32)(
-+ (((__u32)(__x)&(__u32)0x000000ffUL) << 24) |
-+ (((__u32)(__x)&(__u32)0x0000ff00UL) << 8) |
-+ (((__u32)(__x)&(__u32)0x00ff0000UL) >> 8) |
-+ (((__u32)(__x)&(__u32)0xff000000UL) >> 24));
-+}
-+
-+__inline static __u64 ___swab64(__u64 x)
-+{
-+ __u64 __x = (x);
-+
-+ return
-+ (__u64)(\
-+ (__u64)(((__u64)(__x)&(__u64)0x00000000000000ffULL) << 56) | \
-+ (__u64)(((__u64)(__x)&(__u64)0x000000000000ff00ULL) << 40) | \
-+ (__u64)(((__u64)(__x)&(__u64)0x0000000000ff0000ULL) << 24) | \
-+ (__u64)(((__u64)(__x)&(__u64)0x00000000ff000000ULL) << 8) | \
-+ (__u64)(((__u64)(__x)&(__u64)0x000000ff00000000ULL) >> 8) | \
-+ (__u64)(((__u64)(__x)&(__u64)0x0000ff0000000000ULL) >> 24) | \
-+ (__u64)(((__u64)(__x)&(__u64)0x00ff000000000000ULL) >> 40) | \
-+ (__u64)(((__u64)(__x)&(__u64)0xff00000000000000ULL) >> 56));
-+ \
-+}
-+#endif /* CONFIG_PLATFORM_MSTAR */
-+
-+#ifndef __arch__swab16
-+__inline static __u16 __arch__swab16(__u16 x)
-+{
-+ return ___swab16(x);
-+}
-+
-+#endif
-+
-+#ifndef __arch__swab32
-+__inline static __u32 __arch__swab32(__u32 x)
-+{
-+ __u32 __tmp = (x) ;
-+ return ___swab32(__tmp);
-+}
-+#endif
-+
-+#ifndef __arch__swab64
-+
-+__inline static __u64 __arch__swab64(__u64 x)
-+{
-+ __u64 __tmp = (x) ;
-+ return ___swab64(__tmp);
-+}
-+
-+
-+#endif
-+
-+#ifndef __swab16
-+ #define __swab16(x) __fswab16(x)
-+ #define __swab32(x) __fswab32(x)
-+ #define __swab64(x) __fswab64(x)
-+#endif /* __swab16 */
-+
-+#ifdef PLATFORM_FREEBSD
-+ __inline static __u16 __fswab16(__u16 x)
-+#else
-+ __inline static const __u16 __fswab16(__u16 x)
-+#endif /* PLATFORM_FREEBSD */
-+{
-+ return __arch__swab16(x);
-+}
-+#ifdef PLATFORM_FREEBSD
-+ __inline static __u32 __fswab32(__u32 x)
-+#else
-+ __inline static const __u32 __fswab32(__u32 x)
-+#endif /* PLATFORM_FREEBSD */
-+{
-+ return __arch__swab32(x);
-+}
-+
-+#if defined(PLATFORM_LINUX) || defined(PLATFORM_WINDOWS)
-+ #define swab16 __swab16
-+ #define swab32 __swab32
-+ #define swab64 __swab64
-+ #define swab16p __swab16p
-+ #define swab32p __swab32p
-+ #define swab64p __swab64p
-+ #define swab16s __swab16s
-+ #define swab32s __swab32s
-+ #define swab64s __swab64s
-+#endif
-+
-+#endif /* _LINUX_BYTEORDER_SWAB_H */
-diff --git linux-5.8/3rdparty/rtl8812au/include/byteorder/swabb.h linux-5.8/3rdparty/rtl8812au/include/byteorder/swabb.h
-new file mode 100644
-index 000000000..634519a0b
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/include/byteorder/swabb.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/include/byteorder/swabb.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/include/byteorder/swabb.h
+--- linux-5.11.4/3rdparty/rtl8812au/include/byteorder/swabb.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/include/byteorder/swabb.h 2021-03-07 18:16:17.084957471 +0200
@@ -0,0 +1,151 @@
+/******************************************************************************
+ *
@@ -373594,11 +367043,149 @@ index 000000000..634519a0b
+#endif
+
+#endif /* _LINUX_BYTEORDER_SWABB_H */
-diff --git linux-5.8/3rdparty/rtl8812au/include/circ_buf.h linux-5.8/3rdparty/rtl8812au/include/circ_buf.h
-new file mode 100644
-index 000000000..7a5b8ef1a
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/include/circ_buf.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/include/byteorder/swab.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/include/byteorder/swab.h
+--- linux-5.11.4/3rdparty/rtl8812au/include/byteorder/swab.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/include/byteorder/swab.h 2021-03-07 18:16:17.084957471 +0200
+@@ -0,0 +1,136 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef _LINUX_BYTEORDER_SWAB_H
++#define _LINUX_BYTEORDER_SWAB_H
++
++#if !defined(CONFIG_PLATFORM_MSTAR)
++#ifndef __u16
++ typedef unsigned short __u16;
++#endif
++
++#ifndef __u32
++ typedef unsigned int __u32;
++#endif
++
++#ifndef __u8
++ typedef unsigned char __u8;
++#endif
++
++#ifndef __u64
++ typedef unsigned long long __u64;
++#endif
++
++
++__inline static __u16 ___swab16(__u16 x)
++{
++ __u16 __x = x;
++ return
++ (__u16)(
++ (((__u16)(__x)&(__u16)0x00ffU) << 8) |
++ (((__u16)(__x)&(__u16)0xff00U) >> 8));
++
++}
++
++__inline static __u32 ___swab32(__u32 x)
++{
++ __u32 __x = (x);
++ return (__u32)(
++ (((__u32)(__x)&(__u32)0x000000ffUL) << 24) |
++ (((__u32)(__x)&(__u32)0x0000ff00UL) << 8) |
++ (((__u32)(__x)&(__u32)0x00ff0000UL) >> 8) |
++ (((__u32)(__x)&(__u32)0xff000000UL) >> 24));
++}
++
++__inline static __u64 ___swab64(__u64 x)
++{
++ __u64 __x = (x);
++
++ return
++ (__u64)(\
++ (__u64)(((__u64)(__x)&(__u64)0x00000000000000ffULL) << 56) | \
++ (__u64)(((__u64)(__x)&(__u64)0x000000000000ff00ULL) << 40) | \
++ (__u64)(((__u64)(__x)&(__u64)0x0000000000ff0000ULL) << 24) | \
++ (__u64)(((__u64)(__x)&(__u64)0x00000000ff000000ULL) << 8) | \
++ (__u64)(((__u64)(__x)&(__u64)0x000000ff00000000ULL) >> 8) | \
++ (__u64)(((__u64)(__x)&(__u64)0x0000ff0000000000ULL) >> 24) | \
++ (__u64)(((__u64)(__x)&(__u64)0x00ff000000000000ULL) >> 40) | \
++ (__u64)(((__u64)(__x)&(__u64)0xff00000000000000ULL) >> 56));
++ \
++}
++#endif /* CONFIG_PLATFORM_MSTAR */
++
++#ifndef __arch__swab16
++__inline static __u16 __arch__swab16(__u16 x)
++{
++ return ___swab16(x);
++}
++
++#endif
++
++#ifndef __arch__swab32
++__inline static __u32 __arch__swab32(__u32 x)
++{
++ __u32 __tmp = (x) ;
++ return ___swab32(__tmp);
++}
++#endif
++
++#ifndef __arch__swab64
++
++__inline static __u64 __arch__swab64(__u64 x)
++{
++ __u64 __tmp = (x) ;
++ return ___swab64(__tmp);
++}
++
++
++#endif
++
++#ifndef __swab16
++ #define __swab16(x) __fswab16(x)
++ #define __swab32(x) __fswab32(x)
++ #define __swab64(x) __fswab64(x)
++#endif /* __swab16 */
++
++#ifdef PLATFORM_FREEBSD
++ __inline static __u16 __fswab16(__u16 x)
++#else
++ __inline static const __u16 __fswab16(__u16 x)
++#endif /* PLATFORM_FREEBSD */
++{
++ return __arch__swab16(x);
++}
++#ifdef PLATFORM_FREEBSD
++ __inline static __u32 __fswab32(__u32 x)
++#else
++ __inline static const __u32 __fswab32(__u32 x)
++#endif /* PLATFORM_FREEBSD */
++{
++ return __arch__swab32(x);
++}
++
++#if defined(PLATFORM_LINUX) || defined(PLATFORM_WINDOWS)
++ #define swab16 __swab16
++ #define swab32 __swab32
++ #define swab64 __swab64
++ #define swab16p __swab16p
++ #define swab32p __swab32p
++ #define swab64p __swab64p
++ #define swab16s __swab16s
++ #define swab32s __swab32s
++ #define swab64s __swab64s
++#endif
++
++#endif /* _LINUX_BYTEORDER_SWAB_H */
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/include/circ_buf.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/include/circ_buf.h
+--- linux-5.11.4/3rdparty/rtl8812au/include/circ_buf.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/include/circ_buf.h 2021-03-07 18:16:17.084957471 +0200
@@ -0,0 +1,23 @@
+/******************************************************************************
+ *
@@ -373623,11 +367210,9 @@ index 000000000..7a5b8ef1a
+
+#endif //_CIRC_BUF_H_
+
-diff --git linux-5.8/3rdparty/rtl8812au/include/cmd_osdep.h linux-5.8/3rdparty/rtl8812au/include/cmd_osdep.h
-new file mode 100644
-index 000000000..e4ba2b6d3
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/include/cmd_osdep.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/include/cmd_osdep.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/include/cmd_osdep.h
+--- linux-5.11.4/3rdparty/rtl8812au/include/cmd_osdep.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/include/cmd_osdep.h 2021-03-07 18:16:17.084957471 +0200
@@ -0,0 +1,26 @@
+/******************************************************************************
+ *
@@ -373655,11 +367240,9 @@ index 000000000..e4ba2b6d3
+extern struct cmd_obj *_rtw_dequeue_cmd(_queue *queue);
+
+#endif
-diff --git linux-5.8/3rdparty/rtl8812au/include/cmn_info/rtw_sta_info.h linux-5.8/3rdparty/rtl8812au/include/cmn_info/rtw_sta_info.h
-new file mode 100644
-index 000000000..6910098af
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/include/cmn_info/rtw_sta_info.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/include/cmn_info/rtw_sta_info.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/include/cmn_info/rtw_sta_info.h
+--- linux-5.11.4/3rdparty/rtl8812au/include/cmn_info/rtw_sta_info.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/include/cmn_info/rtw_sta_info.h 2021-03-07 18:16:17.084957471 +0200
@@ -0,0 +1,257 @@
+/******************************************************************************
+ *
@@ -373918,11 +367501,9 @@ index 000000000..6910098af
+/*--------------------Function declaration-----------------------------*/
+
+#endif
-diff --git linux-5.8/3rdparty/rtl8812au/include/custom_gpio.h linux-5.8/3rdparty/rtl8812au/include/custom_gpio.h
-new file mode 100644
-index 000000000..49411b662
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/include/custom_gpio.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/include/custom_gpio.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/include/custom_gpio.h
+--- linux-5.11.4/3rdparty/rtl8812au/include/custom_gpio.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/include/custom_gpio.h 2021-03-07 18:16:17.084957471 +0200
@@ -0,0 +1,46 @@
+/******************************************************************************
+ *
@@ -373970,11 +367551,9 @@ index 000000000..49411b662
+extern void rtw_wifi_gpio_wlan_ctrl(int onoff);
+
+#endif
-diff --git linux-5.8/3rdparty/rtl8812au/include/drv_conf.h linux-5.8/3rdparty/rtl8812au/include/drv_conf.h
-new file mode 100644
-index 000000000..9fac340fd
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/include/drv_conf.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/include/drv_conf.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/include/drv_conf.h
+--- linux-5.11.4/3rdparty/rtl8812au/include/drv_conf.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/include/drv_conf.h 2021-03-07 18:16:17.084957471 +0200
@@ -0,0 +1,510 @@
+/******************************************************************************
+ *
@@ -374486,11 +368065,152 @@ index 000000000..9fac340fd
+#endif
+
+#endif /* __DRV_CONF_H__ */
-diff --git linux-5.8/3rdparty/rtl8812au/include/drv_types.h linux-5.8/3rdparty/rtl8812au/include/drv_types.h
-new file mode 100644
-index 000000000..e52608d59
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/include/drv_types.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/include/drv_types_ce.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/include/drv_types_ce.h
+--- linux-5.11.4/3rdparty/rtl8812au/include/drv_types_ce.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/include/drv_types_ce.h 2021-03-07 18:16:17.085957519 +0200
+@@ -0,0 +1,86 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __DRV_TYPES_CE_H__
++#define __DRV_TYPES_CE_H__
++
++#include
++#include
++
++#include
++
++#define MAX_ACTIVE_REG_PATH 256
++
++#define MAX_MCAST_LIST_NUM 32
++
++
++
++/* for ioctl */
++#define MAKE_DRIVER_VERSION(_MainVer, _MinorVer) ((((u32)(_MainVer))<<16)+_MinorVer)
++
++#define NIC_HEADER_SIZE 14 /* !< can be moved to typedef.h */
++#define NIC_MAX_PACKET_SIZE 1514 /* !< can be moved to typedef.h */
++#define NIC_MAX_SEND_PACKETS 10 /* max number of send packets the MiniportSendPackets function can accept, can be moved to typedef.h */
++#define NIC_VENDOR_DRIVER_VERSION MAKE_DRIVER_VERSION(0, 001) /* !< can be moved to typedef.h */
++#define NIC_MAX_PACKET_SIZE 1514 /* !< can be moved to typedef.h */
++
++typedef struct _MP_REG_ENTRY {
++
++ NDIS_STRING RegName; /* variable name text */
++ BOOLEAN bRequired; /* 1->required, 0->optional */
++
++ u8 Type; /* NdisParameterInteger/NdisParameterHexInteger/NdisParameterStringle/NdisParameterMultiString */
++ uint FieldOffset; /* offset to MP_ADAPTER field */
++ uint FieldSize; /* size (in bytes) of the field */
++
++#ifdef UNDER_AMD64
++ u64 Default;
++#else
++ u32 Default; /* default value to use */
++#endif
++
++ u32 Min; /* minimum value allowed */
++ u32 Max; /* maximum value allowed */
++} MP_REG_ENTRY, *PMP_REG_ENTRY;
++
++#ifdef CONFIG_USB_HCI
++typedef struct _USB_EXTENSION {
++ LPCUSB_FUNCS _lpUsbFuncs;
++ USB_HANDLE _hDevice;
++ PVOID pAdapter;
++
++#if 0
++ USB_ENDPOINT_DESCRIPTOR _endpACLIn;
++ USB_ENDPOINT_DESCRIPTOR _endpACLOutHigh;
++ USB_ENDPOINT_DESCRIPTOR _endpACLOutNormal;
++
++ USB_PIPE pPipeIn;
++ USB_PIPE pPipeOutNormal;
++ USB_PIPE pPipeOutHigh;
++#endif
++
++} USB_EXTENSION, *PUSB_EXTENSION;
++#endif
++
++
++typedef struct _OCTET_STRING {
++ u8 *Octet;
++ u16 Length;
++} OCTET_STRING, *POCTET_STRING;
++
++
++
++
++
++#endif
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/include/drv_types_gspi.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/include/drv_types_gspi.h
+--- linux-5.11.4/3rdparty/rtl8812au/include/drv_types_gspi.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/include/drv_types_gspi.h 2021-03-07 18:16:17.085957519 +0200
+@@ -0,0 +1,49 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __DRV_TYPES_GSPI_H__
++#define __DRV_TYPES_GSPI_H__
++
++/* SPI Header Files */
++#ifdef PLATFORM_LINUX
++ #include
++ #include
++ #include
++ /* #include */
++ #include
++ #include
++ #include
++ #include
++ #include
++ #include
++ #include
++#endif
++
++
++typedef struct gspi_data {
++ u8 func_number;
++
++ u8 tx_block_mode;
++ u8 rx_block_mode;
++ u32 block_transfer_len;
++
++#ifdef PLATFORM_LINUX
++ struct spi_device *func;
++
++ struct workqueue_struct *priv_wq;
++ struct delayed_work irq_work;
++#endif
++} GSPI_DATA, *PGSPI_DATA;
++
++#endif /* #ifndef __DRV_TYPES_GSPI_H__ */
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/include/drv_types.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/include/drv_types.h
+--- linux-5.11.4/3rdparty/rtl8812au/include/drv_types.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/include/drv_types.h 2021-03-07 18:16:17.085957519 +0200
@@ -0,0 +1,1834 @@
+/******************************************************************************
+ *
@@ -376326,158 +370046,9 @@ index 000000000..e52608d59
+#endif
+
+#endif /* __DRV_TYPES_H__ */
-diff --git linux-5.8/3rdparty/rtl8812au/include/drv_types_ce.h linux-5.8/3rdparty/rtl8812au/include/drv_types_ce.h
-new file mode 100644
-index 000000000..c00dea8e6
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/include/drv_types_ce.h
-@@ -0,0 +1,86 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __DRV_TYPES_CE_H__
-+#define __DRV_TYPES_CE_H__
-+
-+#include
-+#include
-+
-+#include
-+
-+#define MAX_ACTIVE_REG_PATH 256
-+
-+#define MAX_MCAST_LIST_NUM 32
-+
-+
-+
-+/* for ioctl */
-+#define MAKE_DRIVER_VERSION(_MainVer, _MinorVer) ((((u32)(_MainVer))<<16)+_MinorVer)
-+
-+#define NIC_HEADER_SIZE 14 /* !< can be moved to typedef.h */
-+#define NIC_MAX_PACKET_SIZE 1514 /* !< can be moved to typedef.h */
-+#define NIC_MAX_SEND_PACKETS 10 /* max number of send packets the MiniportSendPackets function can accept, can be moved to typedef.h */
-+#define NIC_VENDOR_DRIVER_VERSION MAKE_DRIVER_VERSION(0, 001) /* !< can be moved to typedef.h */
-+#define NIC_MAX_PACKET_SIZE 1514 /* !< can be moved to typedef.h */
-+
-+typedef struct _MP_REG_ENTRY {
-+
-+ NDIS_STRING RegName; /* variable name text */
-+ BOOLEAN bRequired; /* 1->required, 0->optional */
-+
-+ u8 Type; /* NdisParameterInteger/NdisParameterHexInteger/NdisParameterStringle/NdisParameterMultiString */
-+ uint FieldOffset; /* offset to MP_ADAPTER field */
-+ uint FieldSize; /* size (in bytes) of the field */
-+
-+#ifdef UNDER_AMD64
-+ u64 Default;
-+#else
-+ u32 Default; /* default value to use */
-+#endif
-+
-+ u32 Min; /* minimum value allowed */
-+ u32 Max; /* maximum value allowed */
-+} MP_REG_ENTRY, *PMP_REG_ENTRY;
-+
-+#ifdef CONFIG_USB_HCI
-+typedef struct _USB_EXTENSION {
-+ LPCUSB_FUNCS _lpUsbFuncs;
-+ USB_HANDLE _hDevice;
-+ PVOID pAdapter;
-+
-+#if 0
-+ USB_ENDPOINT_DESCRIPTOR _endpACLIn;
-+ USB_ENDPOINT_DESCRIPTOR _endpACLOutHigh;
-+ USB_ENDPOINT_DESCRIPTOR _endpACLOutNormal;
-+
-+ USB_PIPE pPipeIn;
-+ USB_PIPE pPipeOutNormal;
-+ USB_PIPE pPipeOutHigh;
-+#endif
-+
-+} USB_EXTENSION, *PUSB_EXTENSION;
-+#endif
-+
-+
-+typedef struct _OCTET_STRING {
-+ u8 *Octet;
-+ u16 Length;
-+} OCTET_STRING, *POCTET_STRING;
-+
-+
-+
-+
-+
-+#endif
-diff --git linux-5.8/3rdparty/rtl8812au/include/drv_types_gspi.h linux-5.8/3rdparty/rtl8812au/include/drv_types_gspi.h
-new file mode 100644
-index 000000000..c22c49722
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/include/drv_types_gspi.h
-@@ -0,0 +1,49 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __DRV_TYPES_GSPI_H__
-+#define __DRV_TYPES_GSPI_H__
-+
-+/* SPI Header Files */
-+#ifdef PLATFORM_LINUX
-+ #include
-+ #include
-+ #include
-+ /* #include */
-+ #include
-+ #include
-+ #include
-+ #include
-+ #include
-+ #include
-+ #include
-+#endif
-+
-+
-+typedef struct gspi_data {
-+ u8 func_number;
-+
-+ u8 tx_block_mode;
-+ u8 rx_block_mode;
-+ u32 block_transfer_len;
-+
-+#ifdef PLATFORM_LINUX
-+ struct spi_device *func;
-+
-+ struct workqueue_struct *priv_wq;
-+ struct delayed_work irq_work;
-+#endif
-+} GSPI_DATA, *PGSPI_DATA;
-+
-+#endif /* #ifndef __DRV_TYPES_GSPI_H__ */
-diff --git linux-5.8/3rdparty/rtl8812au/include/drv_types_linux.h linux-5.8/3rdparty/rtl8812au/include/drv_types_linux.h
-new file mode 100644
-index 000000000..91ca68b39
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/include/drv_types_linux.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/include/drv_types_linux.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/include/drv_types_linux.h
+--- linux-5.11.4/3rdparty/rtl8812au/include/drv_types_linux.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/include/drv_types_linux.h 2021-03-07 18:16:17.085957519 +0200
@@ -0,0 +1,19 @@
+/******************************************************************************
+ *
@@ -376498,11 +370069,9 @@ index 000000000..91ca68b39
+
+
+#endif
-diff --git linux-5.8/3rdparty/rtl8812au/include/drv_types_pci.h linux-5.8/3rdparty/rtl8812au/include/drv_types_pci.h
-new file mode 100644
-index 000000000..a3a492708
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/include/drv_types_pci.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/include/drv_types_pci.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/include/drv_types_pci.h
+--- linux-5.11.4/3rdparty/rtl8812au/include/drv_types_pci.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/include/drv_types_pci.h 2021-03-07 18:16:17.085957519 +0200
@@ -0,0 +1,266 @@
+/******************************************************************************
+ *
@@ -376770,11 +370339,9 @@ index 000000000..a3a492708
+
+
+#endif
-diff --git linux-5.8/3rdparty/rtl8812au/include/drv_types_sdio.h linux-5.8/3rdparty/rtl8812au/include/drv_types_sdio.h
-new file mode 100644
-index 000000000..9feca1216
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/include/drv_types_sdio.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/include/drv_types_sdio.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/include/drv_types_sdio.h
+--- linux-5.11.4/3rdparty/rtl8812au/include/drv_types_sdio.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/include/drv_types_sdio.h 2021-03-07 18:16:17.085957519 +0200
@@ -0,0 +1,90 @@
+/******************************************************************************
+ *
@@ -376866,11 +370433,9 @@ index 000000000..9feca1216
+#define RTW_SDIO_ADDR_F0_CHK(a) (a&RTW_SDIO_ADDR_F0_BIT ? 1 : 0)
+
+#endif
-diff --git linux-5.8/3rdparty/rtl8812au/include/drv_types_xp.h linux-5.8/3rdparty/rtl8812au/include/drv_types_xp.h
-new file mode 100644
-index 000000000..81c45047a
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/include/drv_types_xp.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/include/drv_types_xp.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/include/drv_types_xp.h
+--- linux-5.11.4/3rdparty/rtl8812au/include/drv_types_xp.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/include/drv_types_xp.h 2021-03-07 18:16:17.085957519 +0200
@@ -0,0 +1,88 @@
+/******************************************************************************
+ *
@@ -376960,11 +370525,9 @@ index 000000000..81c45047a
+
+
+#endif
-diff --git linux-5.8/3rdparty/rtl8812au/include/ethernet.h linux-5.8/3rdparty/rtl8812au/include/ethernet.h
-new file mode 100644
-index 000000000..2bafa4d98
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/include/ethernet.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/include/ethernet.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/include/ethernet.h
+--- linux-5.11.4/3rdparty/rtl8812au/include/ethernet.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/include/ethernet.h 2021-03-07 18:16:17.085957519 +0200
@@ -0,0 +1,36 @@
+/******************************************************************************
+ *
@@ -377002,11 +370565,9 @@ index 000000000..2bafa4d98
+
+
+#endif /* #ifndef __INC_ETHERNET_H */
-diff --git linux-5.8/3rdparty/rtl8812au/include/gspi_hal.h linux-5.8/3rdparty/rtl8812au/include/gspi_hal.h
-new file mode 100644
-index 000000000..6da0f071d
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/include/gspi_hal.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/include/gspi_hal.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/include/gspi_hal.h
+--- linux-5.11.4/3rdparty/rtl8812au/include/gspi_hal.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/include/gspi_hal.h 2021-03-07 18:16:17.085957519 +0200
@@ -0,0 +1,30 @@
+/******************************************************************************
+ *
@@ -377038,11 +370599,9 @@ index 000000000..6da0f071d
+#endif
+
+#endif /* __GSPI_HAL_H__ */
-diff --git linux-5.8/3rdparty/rtl8812au/include/gspi_ops.h linux-5.8/3rdparty/rtl8812au/include/gspi_ops.h
-new file mode 100644
-index 000000000..bcfaad2e0
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/include/gspi_ops.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/include/gspi_ops.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/include/gspi_ops.h
+--- linux-5.11.4/3rdparty/rtl8812au/include/gspi_ops.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/include/gspi_ops.h 2021-03-07 18:16:17.085957519 +0200
@@ -0,0 +1,180 @@
+/******************************************************************************
+ *
@@ -377224,11 +370783,9 @@ index 000000000..bcfaad2e0
+#endif /* CONFIG_WOWLAN */
+
+#endif /* __GSPI_OPS_H__ */
-diff --git linux-5.8/3rdparty/rtl8812au/include/gspi_ops_linux.h linux-5.8/3rdparty/rtl8812au/include/gspi_ops_linux.h
-new file mode 100644
-index 000000000..0ba263de8
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/include/gspi_ops_linux.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/include/gspi_ops_linux.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/include/gspi_ops_linux.h
+--- linux-5.11.4/3rdparty/rtl8812au/include/gspi_ops_linux.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/include/gspi_ops_linux.h 2021-03-07 18:16:17.085957519 +0200
@@ -0,0 +1,18 @@
+/******************************************************************************
+ *
@@ -377248,11 +370805,9 @@ index 000000000..0ba263de8
+#define __SDIO_OPS_LINUX_H__
+
+#endif
-diff --git linux-5.8/3rdparty/rtl8812au/include/gspi_osintf.h linux-5.8/3rdparty/rtl8812au/include/gspi_osintf.h
-new file mode 100644
-index 000000000..6393f779d
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/include/gspi_osintf.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/include/gspi_osintf.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/include/gspi_osintf.h
+--- linux-5.11.4/3rdparty/rtl8812au/include/gspi_osintf.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/include/gspi_osintf.h 2021-03-07 18:16:17.085957519 +0200
@@ -0,0 +1,25 @@
+/******************************************************************************
+ *
@@ -377279,11 +370834,9 @@ index 000000000..6393f779d
+#endif
+
+#endif
-diff --git linux-5.8/3rdparty/rtl8812au/include/h2clbk.h linux-5.8/3rdparty/rtl8812au/include/h2clbk.h
-new file mode 100644
-index 000000000..4e22afcd8
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/include/h2clbk.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/include/h2clbk.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/include/h2clbk.h
+--- linux-5.11.4/3rdparty/rtl8812au/include/h2clbk.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/include/h2clbk.h 2021-03-07 18:16:17.085957519 +0200
@@ -0,0 +1,26 @@
+/******************************************************************************
+ *
@@ -377311,11 +370864,2681 @@ index 000000000..4e22afcd8
+void _lbk_evt(IN PADAPTER Adapter);
+
+void h2c_event_callback(unsigned char *dev, unsigned char *pbuf);
-diff --git linux-5.8/3rdparty/rtl8812au/include/hal_btcoex.h linux-5.8/3rdparty/rtl8812au/include/hal_btcoex.h
-new file mode 100644
-index 000000000..03021fee3
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/include/hal_btcoex.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/include/Hal8812PhyCfg.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/include/Hal8812PhyCfg.h
+--- linux-5.11.4/3rdparty/rtl8812au/include/Hal8812PhyCfg.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/include/Hal8812PhyCfg.h 2021-03-07 18:16:17.083957423 +0200
+@@ -0,0 +1,143 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __INC_HAL8812PHYCFG_H__
++#define __INC_HAL8812PHYCFG_H__
++
++
++/*--------------------------Define Parameters-------------------------------*/
++#define LOOP_LIMIT 5
++#define MAX_STALL_TIME 50 /* us */
++#define AntennaDiversityValue 0x80 /* (Adapter->bSoftwareAntennaDiversity ? 0x00 : 0x80) */
++#define MAX_TXPWR_IDX_NMODE_92S 63
++#define Reset_Cnt_Limit 3
++
++
++#ifdef CONFIG_PCI_HCI
++ #define MAX_AGGR_NUM 0x0B
++#else
++ #define MAX_AGGR_NUM 0x07
++#endif /* CONFIG_PCI_HCI */
++
++
++/*--------------------------Define Parameters-------------------------------*/
++
++/*------------------------------Define structure----------------------------*/
++
++
++/* BB/RF related */
++
++/*------------------------------Define structure----------------------------*/
++
++
++/*------------------------Export global variable----------------------------*/
++/*------------------------Export global variable----------------------------*/
++
++
++/*------------------------Export Marco Definition---------------------------*/
++/*------------------------Export Marco Definition---------------------------*/
++
++
++/*--------------------------Exported Function prototype---------------------*/
++/*
++ * BB and RF register read/write
++ * */
++u32 PHY_QueryBBReg8812(IN PADAPTER Adapter,
++ IN u32 RegAddr,
++ IN u32 BitMask);
++void PHY_SetBBReg8812(IN PADAPTER Adapter,
++ IN u32 RegAddr,
++ IN u32 BitMask,
++ IN u32 Data);
++u32 PHY_QueryRFReg8812(IN PADAPTER Adapter,
++ IN enum rf_path eRFPath,
++ IN u32 RegAddr,
++ IN u32 BitMask);
++void PHY_SetRFReg8812(IN PADAPTER Adapter,
++ IN enum rf_path eRFPath,
++ IN u32 RegAddr,
++ IN u32 BitMask,
++ IN u32 Data);
++
++/*
++ * Initialization related function
++ *
++ * MAC/BB/RF HAL config */
++int PHY_MACConfig8812(IN PADAPTER Adapter);
++int PHY_BBConfig8812(IN PADAPTER Adapter);
++void PHY_BB8812_Config_1T(IN PADAPTER Adapter);
++int PHY_RFConfig8812(IN PADAPTER Adapter);
++
++/* RF config */
++
++s32
++PHY_SwitchWirelessBand8812(
++ IN PADAPTER Adapter,
++ IN u8 Band
++);
++
++/*
++ * BB TX Power R/W
++ * */
++void PHY_GetTxPowerLevel8812(IN PADAPTER Adapter, OUT s32 *powerlevel);
++void PHY_SetTxPowerLevel8812(IN PADAPTER Adapter, IN u8 Channel);
++
++BOOLEAN PHY_UpdateTxPowerDbm8812(IN PADAPTER Adapter, IN int powerInDbm);
++u8 PHY_GetTxPowerIndex_8812A(
++ IN PADAPTER pAdapter,
++ IN enum rf_path RFPath,
++ IN u8 Rate,
++ IN u8 BandWidth,
++ IN u8 Channel,
++ struct txpwr_idx_comp *tic
++);
++
++u32 phy_get_tx_bb_swing_8812a(
++ IN PADAPTER Adapter,
++ IN BAND_TYPE Band,
++ IN enum rf_path RFPath
++);
++
++VOID
++PHY_SetTxPowerIndex_8812A(
++ IN PADAPTER Adapter,
++ IN u32 PowerIndex,
++ IN enum rf_path RFPath,
++ IN u8 Rate
++);
++
++/*
++ * channel switch related funciton
++ * */
++VOID
++PHY_SetSwChnlBWMode8812(
++ IN PADAPTER Adapter,
++ IN u8 channel,
++ IN enum channel_width Bandwidth,
++ IN u8 Offset40,
++ IN u8 Offset80
++);
++
++/*
++ * BB/MAC/RF other monitor API
++ * */
++
++VOID
++phy_set_rf_path_switch_8812a(
++ IN struct dm_struct *phydm,
++ IN bool bMain
++);
++
++/*--------------------------Exported Function prototype---------------------*/
++#endif /* __INC_HAL8192CPHYCFG_H */
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/include/Hal8812PhyReg.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/include/Hal8812PhyReg.h
+--- linux-5.11.4/3rdparty/rtl8812au/include/Hal8812PhyReg.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/include/Hal8812PhyReg.h 2021-03-07 18:16:17.084957471 +0200
+@@ -0,0 +1,735 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __INC_HAL8812PHYREG_H__
++#define __INC_HAL8812PHYREG_H__
++/*--------------------------Define Parameters-------------------------------*/
++/*
++ * BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF
++ * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF
++ * 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00
++ * 3. RF register 0x00-2E
++ * 4. Bit Mask for BB/RF register
++ * 5. Other defintion for BB/RF R/W
++ * */
++
++
++/* BB Register Definition */
++
++#define rCCAonSec_Jaguar 0x838
++#define rPwed_TH_Jaguar 0x830
++
++/* BW and sideband setting */
++#define rBWIndication_Jaguar 0x834
++#define rL1PeakTH_Jaguar 0x848
++#define rFPGA0_XA_LSSIReadBack 0x8a0 /*Tranceiver LSSI Readback*/
++#define rRFMOD_Jaguar 0x8ac /* RF mode */
++#define rADC_Buf_Clk_Jaguar 0x8c4
++#define rRFECTRL_Jaguar 0x900
++#define bRFMOD_Jaguar 0xc3
++#define rCCK_System_Jaguar 0xa00 /* for cck sideband */
++#define bCCK_System_Jaguar 0x10
++
++/* Block & Path enable */
++#define rOFDMCCKEN_Jaguar 0x808 /* OFDM/CCK block enable */
++#define bOFDMEN_Jaguar 0x20000000
++#define bCCKEN_Jaguar 0x10000000
++#define rRxPath_Jaguar 0x808 /* Rx antenna */
++#define bRxPath_Jaguar 0xff
++#define rTxPath_Jaguar 0x80c /* Tx antenna */
++#define bTxPath_Jaguar 0x0fffffff
++#define rCCK_RX_Jaguar 0xa04 /* for cck rx path selection */
++#define bCCK_RX_Jaguar 0x0c000000
++#define rVhtlen_Use_Lsig_Jaguar 0x8c3 /* Use LSIG for VHT length */
++
++/* RF read/write-related */
++#define rHSSIRead_Jaguar 0x8b0 /* RF read addr */
++#define bHSSIRead_addr_Jaguar 0xff
++#define bHSSIRead_trigger_Jaguar 0x100
++#define rA_PIRead_Jaguar 0xd04 /* RF readback with PI */
++#define rB_PIRead_Jaguar 0xd44 /* RF readback with PI */
++#define rA_SIRead_Jaguar 0xd08 /* RF readback with SI */
++#define rB_SIRead_Jaguar 0xd48 /* RF readback with SI */
++#define rRead_data_Jaguar 0xfffff
++#define rA_LSSIWrite_Jaguar 0xc90 /* RF write addr */
++#define rB_LSSIWrite_Jaguar 0xe90 /* RF write addr */
++#define bLSSIWrite_data_Jaguar 0x000fffff
++#define bLSSIWrite_addr_Jaguar 0x0ff00000
++
++
++
++/* YN: mask the following register definition temporarily */
++#define rFPGA0_XA_RFInterfaceOE 0x860 /* RF Channel switch */
++#define rFPGA0_XB_RFInterfaceOE 0x864
++
++#define rFPGA0_XAB_RFInterfaceSW 0x870 /* RF Interface Software Control */
++#define rFPGA0_XCD_RFInterfaceSW 0x874
++
++/* #define rFPGA0_XAB_RFParameter 0x878 */ /* RF Parameter
++ * #define rFPGA0_XCD_RFParameter 0x87c */
++
++/* #define rFPGA0_AnalogParameter1 0x880 */ /* Crystal cap setting RF-R/W protection for parameter4??
++ * #define rFPGA0_AnalogParameter2 0x884
++ * #define rFPGA0_AnalogParameter3 0x888
++ * #define rFPGA0_AdDaClockEn 0x888 */ /* enable ad/da clock1 for dual-phy
++ * #define rFPGA0_AnalogParameter4 0x88c */
++
++
++/* CCK TX scaling */
++#define rCCK_TxFilter1_Jaguar 0xa20
++#define bCCK_TxFilter1_C0_Jaguar 0x00ff0000
++#define bCCK_TxFilter1_C1_Jaguar 0xff000000
++#define rCCK_TxFilter2_Jaguar 0xa24
++#define bCCK_TxFilter2_C2_Jaguar 0x000000ff
++#define bCCK_TxFilter2_C3_Jaguar 0x0000ff00
++#define bCCK_TxFilter2_C4_Jaguar 0x00ff0000
++#define bCCK_TxFilter2_C5_Jaguar 0xff000000
++#define rCCK_TxFilter3_Jaguar 0xa28
++#define bCCK_TxFilter3_C6_Jaguar 0x000000ff
++#define bCCK_TxFilter3_C7_Jaguar 0x0000ff00
++
++
++/* YN: mask the following register definition temporarily
++ * #define rPdp_AntA 0xb00
++ * #define rPdp_AntA_4 0xb04
++ * #define rConfig_Pmpd_AntA 0xb28
++ * #define rConfig_AntA 0xb68
++ * #define rConfig_AntB 0xb6c
++ * #define rPdp_AntB 0xb70
++ * #define rPdp_AntB_4 0xb74
++ * #define rConfig_Pmpd_AntB 0xb98
++ * #define rAPK 0xbd8 */
++
++/* RXIQC */
++#define rA_RxIQC_AB_Jaguar 0xc10 /* RxIQ imblance matrix coeff. A & B */
++#define rA_RxIQC_CD_Jaguar 0xc14 /* RxIQ imblance matrix coeff. C & D */
++#define rA_TxScale_Jaguar 0xc1c /* Pah_A TX scaling factor */
++#define rB_TxScale_Jaguar 0xe1c /* Path_B TX scaling factor */
++#define rB_RxIQC_AB_Jaguar 0xe10 /* RxIQ imblance matrix coeff. A & B */
++#define rB_RxIQC_CD_Jaguar 0xe14 /* RxIQ imblance matrix coeff. C & D */
++#define b_RxIQC_AC_Jaguar 0x02ff /* bit mask for IQC matrix element A & C */
++#define b_RxIQC_BD_Jaguar 0x02ff0000 /* bit mask for IQC matrix element A & C */
++
++
++/* DIG-related */
++#define rA_IGI_Jaguar 0xc50 /* Initial Gain for path-A */
++#define rB_IGI_Jaguar 0xe50 /* Initial Gain for path-B */
++#define rOFDM_FalseAlarm1_Jaguar 0xf48 /* counter for break */
++#define rOFDM_FalseAlarm2_Jaguar 0xf4c /* counter for spoofing */
++#define rCCK_FalseAlarm_Jaguar 0xa5c /* counter for cck false alarm */
++#define b_FalseAlarm_Jaguar 0xffff
++#define rCCK_CCA_Jaguar 0xa08 /* cca threshold */
++#define bCCK_CCA_Jaguar 0x00ff0000
++
++/* Tx Power Ttraining-related */
++#define rA_TxPwrTraing_Jaguar 0xc54
++#define rB_TxPwrTraing_Jaguar 0xe54
++
++/* Report-related */
++#define rOFDM_ShortCFOAB_Jaguar 0xf60
++#define rOFDM_LongCFOAB_Jaguar 0xf64
++#define rOFDM_EndCFOAB_Jaguar 0xf70
++#define rOFDM_AGCReport_Jaguar 0xf84
++#define rOFDM_RxSNR_Jaguar 0xf88
++#define rOFDM_RxEVMCSI_Jaguar 0xf8c
++#define rOFDM_SIGReport_Jaguar 0xf90
++
++/* Misc functions */
++#define rEDCCA_Jaguar 0x8a4 /* EDCCA */
++#define bEDCCA_Jaguar 0xffff
++#define rAGC_table_Jaguar 0x82c /* AGC tabel select */
++#define bAGC_table_Jaguar 0x3
++#define b_sel5g_Jaguar 0x1000 /* sel5g */
++#define b_LNA_sw_Jaguar 0x8000 /* HW/WS control for LNA */
++#define rFc_area_Jaguar 0x860 /* fc_area */
++#define bFc_area_Jaguar 0x1ffe000
++#define rSingleTone_ContTx_Jaguar 0x914
++
++/* RFE */
++#define rA_RFE_Pinmux_Jaguar 0xcb0 /* Path_A RFE cotrol pinmux */
++#define rB_RFE_Pinmux_Jaguar 0xeb0 /* Path_B RFE control pinmux */
++#define rA_RFE_Inv_Jaguar 0xcb4 /* Path_A RFE cotrol */
++#define rB_RFE_Inv_Jaguar 0xeb4 /* Path_B RFE control */
++#define rA_RFE_Jaguar 0xcb8 /* Path_A RFE cotrol */
++#define rB_RFE_Jaguar 0xeb8 /* Path_B RFE control */
++#define rA_RFE_Inverse_Jaguar 0xCBC /* Path_A RFE control inverse */
++#define rB_RFE_Inverse_Jaguar 0xEBC /* Path_B RFE control inverse */
++#define r_ANTSEL_SW_Jaguar 0x900 /* ANTSEL SW Control */
++#define bMask_RFEInv_Jaguar 0x3ff00000
++#define bMask_AntselPathFollow_Jaguar 0x00030000
++
++/* TX AGC */
++#define rTxAGC_A_CCK11_CCK1_JAguar 0xc20
++#define rTxAGC_A_Ofdm18_Ofdm6_JAguar 0xc24
++#define rTxAGC_A_Ofdm54_Ofdm24_JAguar 0xc28
++#define rTxAGC_A_MCS3_MCS0_JAguar 0xc2c
++#define rTxAGC_A_MCS7_MCS4_JAguar 0xc30
++#define rTxAGC_A_MCS11_MCS8_JAguar 0xc34
++#define rTxAGC_A_MCS15_MCS12_JAguar 0xc38
++#define rTxAGC_A_Nss1Index3_Nss1Index0_JAguar 0xc3c
++#define rTxAGC_A_Nss1Index7_Nss1Index4_JAguar 0xc40
++#define rTxAGC_A_Nss2Index1_Nss1Index8_JAguar 0xc44
++#define rTxAGC_A_Nss2Index5_Nss2Index2_JAguar 0xc48
++#define rTxAGC_A_Nss2Index9_Nss2Index6_JAguar 0xc4c
++#define rTxAGC_B_CCK11_CCK1_JAguar 0xe20
++#define rTxAGC_B_Ofdm18_Ofdm6_JAguar 0xe24
++#define rTxAGC_B_Ofdm54_Ofdm24_JAguar 0xe28
++#define rTxAGC_B_MCS3_MCS0_JAguar 0xe2c
++#define rTxAGC_B_MCS7_MCS4_JAguar 0xe30
++#define rTxAGC_B_MCS11_MCS8_JAguar 0xe34
++#define rTxAGC_B_MCS15_MCS12_JAguar 0xe38
++#define rTxAGC_B_Nss1Index3_Nss1Index0_JAguar 0xe3c
++#define rTxAGC_B_Nss1Index7_Nss1Index4_JAguar 0xe40
++#define rTxAGC_B_Nss2Index1_Nss1Index8_JAguar 0xe44
++#define rTxAGC_B_Nss2Index5_Nss2Index2_JAguar 0xe48
++#define rTxAGC_B_Nss2Index9_Nss2Index6_JAguar 0xe4c
++#define bTxAGC_byte0_Jaguar 0xff
++#define bTxAGC_byte1_Jaguar 0xff00
++#define bTxAGC_byte2_Jaguar 0xff0000
++#define bTxAGC_byte3_Jaguar 0xff000000
++
++/* IQK YN: temporaily mask this part
++ * #define rFPGA0_IQK 0xe28
++ * #define rTx_IQK_Tone_A 0xe30
++ * #define rRx_IQK_Tone_A 0xe34
++ * #define rTx_IQK_PI_A 0xe38
++ * #define rRx_IQK_PI_A 0xe3c */
++
++/* #define rTx_IQK 0xe40 */
++/* #define rRx_IQK 0xe44 */
++/* #define rIQK_AGC_Pts 0xe48 */
++/* #define rIQK_AGC_Rsp 0xe4c */
++/* #define rTx_IQK_Tone_B 0xe50 */
++/* #define rRx_IQK_Tone_B 0xe54 */
++/* #define rTx_IQK_PI_B 0xe58 */
++/* #define rRx_IQK_PI_B 0xe5c */
++/* #define rIQK_AGC_Cont 0xe60 */
++
++
++/* AFE-related */
++#define rA_AFEPwr1_Jaguar 0xc60 /* dynamic AFE power control */
++#define rA_AFEPwr2_Jaguar 0xc64 /* dynamic AFE power control */
++#define rA_Rx_WaitCCA_Tx_CCKRFON_Jaguar 0xc68
++#define rA_Tx_CCKBBON_OFDMRFON_Jaguar 0xc6c
++#define rA_Tx_OFDMBBON_Tx2Rx_Jaguar 0xc70
++#define rA_Tx2Tx_RXCCK_Jaguar 0xc74
++#define rA_Rx_OFDM_WaitRIFS_Jaguar 0xc78
++#define rA_Rx2Rx_BT_Jaguar 0xc7c
++#define rA_sleep_nav_Jaguar 0xc80
++#define rA_pmpd_Jaguar 0xc84
++#define rB_AFEPwr1_Jaguar 0xe60 /* dynamic AFE power control */
++#define rB_AFEPwr2_Jaguar 0xe64 /* dynamic AFE power control */
++#define rB_Rx_WaitCCA_Tx_CCKRFON_Jaguar 0xe68
++#define rB_Tx_CCKBBON_OFDMRFON_Jaguar 0xe6c
++#define rB_Tx_OFDMBBON_Tx2Rx_Jaguar 0xe70
++#define rB_Tx2Tx_RXCCK_Jaguar 0xe74
++#define rB_Rx_OFDM_WaitRIFS_Jaguar 0xe78
++#define rB_Rx2Rx_BT_Jaguar 0xe7c
++#define rB_sleep_nav_Jaguar 0xe80
++#define rB_pmpd_Jaguar 0xe84
++
++
++/* YN: mask these registers temporaily
++ * #define rTx_Power_Before_IQK_A 0xe94
++ * #define rTx_Power_After_IQK_A 0xe9c */
++
++/* #define rRx_Power_Before_IQK_A 0xea0 */
++/* #define rRx_Power_Before_IQK_A_2 0xea4 */
++/* #define rRx_Power_After_IQK_A 0xea8 */
++/* #define rRx_Power_After_IQK_A_2 0xeac */
++
++/* #define rTx_Power_Before_IQK_B 0xeb4 */
++/* #define rTx_Power_After_IQK_B 0xebc */
++
++/* #define rRx_Power_Before_IQK_B 0xec0 */
++/* #define rRx_Power_Before_IQK_B_2 0xec4 */
++/* #define rRx_Power_After_IQK_B 0xec8 */
++/* #define rRx_Power_After_IQK_B_2 0xecc */
++
++
++/* RSSI Dump */
++#define rA_RSSIDump_Jaguar 0xBF0
++#define rB_RSSIDump_Jaguar 0xBF1
++#define rS1_RXevmDump_Jaguar 0xBF4
++#define rS2_RXevmDump_Jaguar 0xBF5
++#define rA_RXsnrDump_Jaguar 0xBF6
++#define rB_RXsnrDump_Jaguar 0xBF7
++#define rA_CfoShortDump_Jaguar 0xBF8
++#define rB_CfoShortDump_Jaguar 0xBFA
++#define rA_CfoLongDump_Jaguar 0xBEC
++#define rB_CfoLongDump_Jaguar 0xBEE
++
++
++/* RF Register
++ * */
++#define RF_AC_Jaguar 0x00 /* */
++#define RF_RF_Top_Jaguar 0x07 /* */
++#define RF_TXLOK_Jaguar 0x08 /* */
++#define RF_TXAPK_Jaguar 0x0B
++#define RF_CHNLBW_Jaguar 0x18 /* RF channel and BW switch */
++#define RF_RCK1_Jaguar 0x1c /* */
++#define RF_RCK2_Jaguar 0x1d
++#define RF_RCK3_Jaguar 0x1e
++#define RF_ModeTableAddr 0x30
++#define RF_ModeTableData0 0x31
++#define RF_ModeTableData1 0x32
++#define RF_TxLCTank_Jaguar 0x54
++#define RF_APK_Jaguar 0x63
++#define RF_LCK 0xB4
++#define RF_WeLut_Jaguar 0xEF
++
++#define bRF_CHNLBW_MOD_AG_Jaguar 0x70300
++#define bRF_CHNLBW_BW 0xc00
++
++
++/*
++ * RL6052 Register definition
++ * */
++#define RF_AC 0x00 /* */
++#define RF_IPA_A 0x0C /* */
++#define RF_TXBIAS_A 0x0D
++#define RF_BS_PA_APSET_G9_G11 0x0E
++#define RF_MODE1 0x10 /* */
++#define RF_MODE2 0x11 /* */
++#define RF_CHNLBW 0x18 /* RF channel and BW switch */
++#define RF_RCK_OS 0x30 /* RF TX PA control */
++#define RF_TXPA_G1 0x31 /* RF TX PA control */
++#define RF_TXPA_G2 0x32 /* RF TX PA control */
++#define RF_TXPA_G3 0x33 /* RF TX PA control */
++#define RF_0x52 0x52
++#define RF_WE_LUT 0xEF
++
++#define RF_TX_GAIN_OFFSET_8812A(_val) ((abs((_val)) << 1) | (((_val) > 0) ? BIT0 : 0))
++#define RF_TX_GAIN_OFFSET_8821A(_val) ((abs((_val)) << 1) | (((_val) > 0) ? BIT0 : 0))
++
++/*
++ * Bit Mask
++ *
++ * 1. Page1(0x100) */
++#define bBBResetB 0x100 /* Useless now? */
++#define bGlobalResetB 0x200
++#define bOFDMTxStart 0x4
++#define bCCKTxStart 0x8
++#define bCRC32Debug 0x100
++#define bPMACLoopback 0x10
++#define bTxLSIG 0xffffff
++#define bOFDMTxRate 0xf
++#define bOFDMTxReserved 0x10
++#define bOFDMTxLength 0x1ffe0
++#define bOFDMTxParity 0x20000
++#define bTxHTSIG1 0xffffff
++#define bTxHTMCSRate 0x7f
++#define bTxHTBW 0x80
++#define bTxHTLength 0xffff00
++#define bTxHTSIG2 0xffffff
++#define bTxHTSmoothing 0x1
++#define bTxHTSounding 0x2
++#define bTxHTReserved 0x4
++#define bTxHTAggreation 0x8
++#define bTxHTSTBC 0x30
++#define bTxHTAdvanceCoding 0x40
++#define bTxHTShortGI 0x80
++#define bTxHTNumberHT_LTF 0x300
++#define bTxHTCRC8 0x3fc00
++#define bCounterReset 0x10000
++#define bNumOfOFDMTx 0xffff
++#define bNumOfCCKTx 0xffff0000
++#define bTxIdleInterval 0xffff
++#define bOFDMService 0xffff0000
++#define bTxMACHeader 0xffffffff
++#define bTxDataInit 0xff
++#define bTxHTMode 0x100
++#define bTxDataType 0x30000
++#define bTxRandomSeed 0xffffffff
++#define bCCKTxPreamble 0x1
++#define bCCKTxSFD 0xffff0000
++#define bCCKTxSIG 0xff
++#define bCCKTxService 0xff00
++#define bCCKLengthExt 0x8000
++#define bCCKTxLength 0xffff0000
++#define bCCKTxCRC16 0xffff
++#define bCCKTxStatus 0x1
++#define bOFDMTxStatus 0x2
++
++
++/*
++ * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF
++ * 1. Page1(0x100)
++ * */
++#define rPMAC_Reset 0x100
++#define rPMAC_TxStart 0x104
++#define rPMAC_TxLegacySIG 0x108
++#define rPMAC_TxHTSIG1 0x10c
++#define rPMAC_TxHTSIG2 0x110
++#define rPMAC_PHYDebug 0x114
++#define rPMAC_TxPacketNum 0x118
++#define rPMAC_TxIdle 0x11c
++#define rPMAC_TxMACHeader0 0x120
++#define rPMAC_TxMACHeader1 0x124
++#define rPMAC_TxMACHeader2 0x128
++#define rPMAC_TxMACHeader3 0x12c
++#define rPMAC_TxMACHeader4 0x130
++#define rPMAC_TxMACHeader5 0x134
++#define rPMAC_TxDataType 0x138
++#define rPMAC_TxRandomSeed 0x13c
++#define rPMAC_CCKPLCPPreamble 0x140
++#define rPMAC_CCKPLCPHeader 0x144
++#define rPMAC_CCKCRC16 0x148
++#define rPMAC_OFDMRxCRC32OK 0x170
++#define rPMAC_OFDMRxCRC32Er 0x174
++#define rPMAC_OFDMRxParityEr 0x178
++#define rPMAC_OFDMRxCRC8Er 0x17c
++#define rPMAC_CCKCRxRC16Er 0x180
++#define rPMAC_CCKCRxRC32Er 0x184
++#define rPMAC_CCKCRxRC32OK 0x188
++#define rPMAC_TxStatus 0x18c
++
++/*
++ * 3. Page8(0x800)
++ * */
++#define rFPGA0_RFMOD 0x800 /* RF mode & CCK TxSC */ /* RF BW Setting?? */
++
++#define rFPGA0_TxInfo 0x804 /* Status report?? */
++#define rFPGA0_PSDFunction 0x808
++#define rFPGA0_TxGainStage 0x80c /* Set TX PWR init gain? */
++
++#define rFPGA0_XA_HSSIParameter1 0x820 /* RF 3 wire register */
++#define rFPGA0_XA_HSSIParameter2 0x824
++#define rFPGA0_XB_HSSIParameter1 0x828
++#define rFPGA0_XB_HSSIParameter2 0x82c
++
++#define rFPGA0_XAB_SwitchControl 0x858 /* RF Channel switch */
++#define rFPGA0_XCD_SwitchControl 0x85c
++
++#define rFPGA0_XAB_RFParameter 0x878 /* RF Parameter */
++#define rFPGA0_XCD_RFParameter 0x87c
++
++#define rFPGA0_AnalogParameter1 0x880 /* Crystal cap setting RF-R/W protection for parameter4?? */
++#define rFPGA0_AnalogParameter2 0x884
++#define rFPGA0_AnalogParameter3 0x888
++#define rFPGA0_AdDaClockEn 0x888 /* enable ad/da clock1 for dual-phy */
++#define rFPGA0_AnalogParameter4 0x88c
++#define rFPGA0_XB_LSSIReadBack 0x8a4
++#define rFPGA0_XCD_RFPara 0x8b4
++
++/*
++ * 4. Page9(0x900)
++ * */
++#define rFPGA1_RFMOD 0x900 /* RF mode & OFDM TxSC */ /* RF BW Setting?? */
++
++#define rFPGA1_TxBlock 0x904 /* Useless now */
++#define rFPGA1_DebugSelect 0x908 /* Useless now */
++#define rFPGA1_TxInfo 0x90c /* Useless now */ /* Status report?? */
++
++/*
++ * PageA(0xA00)
++ * */
++#define rCCK0_System 0xa00
++#define rCCK0_AFESetting 0xa04 /* Disable init gain now */ /* Select RX path by RSSI */
++#define rCCK0_DSPParameter2 0xa1c /* SQ threshold */
++#define rCCK0_TxFilter1 0xa20
++#define rCCK0_TxFilter2 0xa24
++#define rCCK0_DebugPort 0xa28 /* debug port and Tx filter3 */
++#define rCCK0_FalseAlarmReport 0xa2c /* 0xa2d useless now 0xa30-a4f channel report */
++
++/*
++ * PageB(0xB00)
++ * */
++#define rPdp_AntA 0xb00
++#define rPdp_AntA_4 0xb04
++#define rConfig_Pmpd_AntA 0xb28
++#define rConfig_AntA 0xb68
++#define rConfig_AntB 0xb6c
++#define rPdp_AntB 0xb70
++#define rPdp_AntB_4 0xb74
++#define rConfig_Pmpd_AntB 0xb98
++#define rAPK 0xbd8
++
++/*
++ * 6. PageC(0xC00)
++ * */
++#define rOFDM0_LSTF 0xc00
++
++#define rOFDM0_TRxPathEnable 0xc04
++#define rOFDM0_TRMuxPar 0xc08
++#define rOFDM0_TRSWIsolation 0xc0c
++
++#define rOFDM0_XARxAFE 0xc10 /* RxIQ DC offset, Rx digital filter, DC notch filter */
++#define rOFDM0_XARxIQImbalance 0xc14 /* RxIQ imblance matrix */
++#define rOFDM0_XBRxAFE 0xc18
++#define rOFDM0_XBRxIQImbalance 0xc1c
++#define rOFDM0_XCRxAFE 0xc20
++#define rOFDM0_XCRxIQImbalance 0xc24
++#define rOFDM0_XDRxAFE 0xc28
++#define rOFDM0_XDRxIQImbalance 0xc2c
++
++#define rOFDM0_RxDetector1 0xc30 /* PD, BW & SBD */ /* DM tune init gain */
++#define rOFDM0_RxDetector2 0xc34 /* SBD & Fame Sync. */
++#define rOFDM0_RxDetector3 0xc38 /* Frame Sync. */
++#define rOFDM0_RxDetector4 0xc3c /* PD, SBD, Frame Sync & Short-GI */
++
++#define rOFDM0_RxDSP 0xc40 /* Rx Sync Path */
++#define rOFDM0_CFOandDAGC 0xc44 /* CFO & DAGC */
++#define rOFDM0_CCADropThreshold 0xc48 /* CCA Drop threshold */
++#define rOFDM0_ECCAThreshold 0xc4c /* energy CCA */
++
++#define rOFDM0_XAAGCCore1 0xc50 /* DIG */
++#define rOFDM0_XAAGCCore2 0xc54
++#define rOFDM0_XBAGCCore1 0xc58
++#define rOFDM0_XBAGCCore2 0xc5c
++#define rOFDM0_XCAGCCore1 0xc60
++#define rOFDM0_XCAGCCore2 0xc64
++#define rOFDM0_XDAGCCore1 0xc68
++#define rOFDM0_XDAGCCore2 0xc6c
++
++#define rOFDM0_AGCParameter1 0xc70
++#define rOFDM0_AGCParameter2 0xc74
++#define rOFDM0_AGCRSSITable 0xc78
++#define rOFDM0_HTSTFAGC 0xc7c
++
++#define rOFDM0_XATxIQImbalance 0xc80 /* TX PWR TRACK and DIG */
++#define rOFDM0_XATxAFE 0xc84
++#define rOFDM0_XBTxIQImbalance 0xc88
++#define rOFDM0_XBTxAFE 0xc8c
++#define rOFDM0_XCTxIQImbalance 0xc90
++#define rOFDM0_XCTxAFE 0xc94
++#define rOFDM0_XDTxIQImbalance 0xc98
++#define rOFDM0_XDTxAFE 0xc9c
++
++#define rOFDM0_RxIQExtAnta 0xca0
++#define rOFDM0_TxCoeff1 0xca4
++#define rOFDM0_TxCoeff2 0xca8
++#define rOFDM0_TxCoeff3 0xcac
++#define rOFDM0_TxCoeff4 0xcb0
++#define rOFDM0_TxCoeff5 0xcb4
++#define rOFDM0_TxCoeff6 0xcb8
++#define rOFDM0_RxHPParameter 0xce0
++#define rOFDM0_TxPseudoNoiseWgt 0xce4
++#define rOFDM0_FrameSync 0xcf0
++#define rOFDM0_DFSReport 0xcf4
++
++/*
++ * 7. PageD(0xD00)
++ * */
++#define rOFDM1_LSTF 0xd00
++#define rOFDM1_TRxPathEnable 0xd04
++
++/*
++ * 8. PageE(0xE00)
++ * */
++#define rTxAGC_A_Rate18_06 0xe00
++#define rTxAGC_A_Rate54_24 0xe04
++#define rTxAGC_A_CCK1_Mcs32 0xe08
++#define rTxAGC_A_Mcs03_Mcs00 0xe10
++#define rTxAGC_A_Mcs07_Mcs04 0xe14
++#define rTxAGC_A_Mcs11_Mcs08 0xe18
++#define rTxAGC_A_Mcs15_Mcs12 0xe1c
++
++#define rTxAGC_B_Rate18_06 0x830
++#define rTxAGC_B_Rate54_24 0x834
++#define rTxAGC_B_CCK1_55_Mcs32 0x838
++#define rTxAGC_B_Mcs03_Mcs00 0x83c
++#define rTxAGC_B_Mcs07_Mcs04 0x848
++#define rTxAGC_B_Mcs11_Mcs08 0x84c
++#define rTxAGC_B_Mcs15_Mcs12 0x868
++#define rTxAGC_B_CCK11_A_CCK2_11 0x86c
++
++#define rFPGA0_IQK 0xe28
++#define rTx_IQK_Tone_A 0xe30
++#define rRx_IQK_Tone_A 0xe34
++#define rTx_IQK_PI_A 0xe38
++#define rRx_IQK_PI_A 0xe3c
++
++#define rTx_IQK 0xe40
++#define rRx_IQK 0xe44
++#define rIQK_AGC_Pts 0xe48
++#define rIQK_AGC_Rsp 0xe4c
++#define rTx_IQK_Tone_B 0xe50
++#define rRx_IQK_Tone_B 0xe54
++#define rTx_IQK_PI_B 0xe58
++#define rRx_IQK_PI_B 0xe5c
++#define rIQK_AGC_Cont 0xe60
++
++#define rBlue_Tooth 0xe6c
++#define rRx_Wait_CCA 0xe70
++#define rTx_CCK_RFON 0xe74
++#define rTx_CCK_BBON 0xe78
++#define rTx_OFDM_RFON 0xe7c
++#define rTx_OFDM_BBON 0xe80
++#define rTx_To_Rx 0xe84
++#define rTx_To_Tx 0xe88
++#define rRx_CCK 0xe8c
++
++#define rTx_Power_Before_IQK_A 0xe94
++#define rTx_Power_After_IQK_A 0xe9c
++
++#define rRx_Power_Before_IQK_A 0xea0
++#define rRx_Power_Before_IQK_A_2 0xea4
++#define rRx_Power_After_IQK_A 0xea8
++#define rRx_Power_After_IQK_A_2 0xeac
++
++#define rTx_Power_Before_IQK_B 0xeb4
++#define rTx_Power_After_IQK_B 0xebc
++
++#define rRx_Power_Before_IQK_B 0xec0
++#define rRx_Power_Before_IQK_B_2 0xec4
++#define rRx_Power_After_IQK_B 0xec8
++#define rRx_Power_After_IQK_B_2 0xecc
++
++#define rRx_OFDM 0xed0
++#define rRx_Wait_RIFS 0xed4
++#define rRx_TO_Rx 0xed8
++#define rStandby 0xedc
++#define rSleep 0xee0
++#define rPMPD_ANAEN 0xeec
++
++
++/* 2. Page8(0x800) */
++#define bRFMOD 0x1 /* Reg 0x800 rFPGA0_RFMOD */
++#define bJapanMode 0x2
++#define bCCKTxSC 0x30
++#define bCCKEn 0x1000000
++#define bOFDMEn 0x2000000
++#define bXBTxAGC 0xf00 /* Reg 80c rFPGA0_TxGainStage */
++#define bXCTxAGC 0xf000
++#define bXDTxAGC 0xf0000
++
++/* 4. PageA(0xA00) */
++#define bCCKBBMode 0x3 /* Useless */
++#define bCCKTxPowerSaving 0x80
++#define bCCKRxPowerSaving 0x40
++
++#define bCCKSideBand 0x10 /* Reg 0xa00 rCCK0_System 20/40 switch */
++
++#define bCCKScramble 0x8 /* Useless */
++#define bCCKAntDiversity 0x8000
++#define bCCKCarrierRecovery 0x4000
++#define bCCKTxRate 0x3000
++#define bCCKDCCancel 0x0800
++#define bCCKISICancel 0x0400
++#define bCCKMatchFilter 0x0200
++#define bCCKEqualizer 0x0100
++#define bCCKPreambleDetect 0x800000
++#define bCCKFastFalseCCA 0x400000
++#define bCCKChEstStart 0x300000
++#define bCCKCCACount 0x080000
++#define bCCKcs_lim 0x070000
++#define bCCKBistMode 0x80000000
++#define bCCKCCAMask 0x40000000
++#define bCCKTxDACPhase 0x4
++#define bCCKRxADCPhase 0x20000000 /* r_rx_clk */
++#define bCCKr_cp_mode0 0x0100
++#define bCCKTxDCOffset 0xf0
++#define bCCKRxDCOffset 0xf
++#define bCCKCCAMode 0xc000
++#define bCCKFalseCS_lim 0x3f00
++#define bCCKCS_ratio 0xc00000
++#define bCCKCorgBit_sel 0x300000
++#define bCCKPD_lim 0x0f0000
++#define bCCKNewCCA 0x80000000
++#define bCCKRxHPofIG 0x8000
++#define bCCKRxIG 0x7f00
++#define bCCKLNAPolarity 0x800000
++#define bCCKRx1stGain 0x7f0000
++#define bCCKRFExtend 0x20000000 /* CCK Rx Iinital gain polarity */
++#define bCCKRxAGCSatLevel 0x1f000000
++#define bCCKRxAGCSatCount 0xe0
++#define bCCKRxRFSettle 0x1f /* AGCsamp_dly */
++#define bCCKFixedRxAGC 0x8000
++/* #define bCCKRxAGCFormat 0x4000 */ /* remove to HSSI register 0x824 */
++#define bCCKAntennaPolarity 0x2000
++#define bCCKTxFilterType 0x0c00
++#define bCCKRxAGCReportType 0x0300
++#define bCCKRxDAGCEn 0x80000000
++#define bCCKRxDAGCPeriod 0x20000000
++#define bCCKRxDAGCSatLevel 0x1f000000
++#define bCCKTimingRecovery 0x800000
++#define bCCKTxC0 0x3f0000
++#define bCCKTxC1 0x3f000000
++#define bCCKTxC2 0x3f
++#define bCCKTxC3 0x3f00
++#define bCCKTxC4 0x3f0000
++#define bCCKTxC5 0x3f000000
++#define bCCKTxC6 0x3f
++#define bCCKTxC7 0x3f00
++#define bCCKDebugPort 0xff0000
++#define bCCKDACDebug 0x0f000000
++#define bCCKFalseAlarmEnable 0x8000
++#define bCCKFalseAlarmRead 0x4000
++#define bCCKTRSSI 0x7f
++#define bCCKRxAGCReport 0xfe
++#define bCCKRxReport_AntSel 0x80000000
++#define bCCKRxReport_MFOff 0x40000000
++#define bCCKRxRxReport_SQLoss 0x20000000
++#define bCCKRxReport_Pktloss 0x10000000
++#define bCCKRxReport_Lockedbit 0x08000000
++#define bCCKRxReport_RateError 0x04000000
++#define bCCKRxReport_RxRate 0x03000000
++#define bCCKRxFACounterLower 0xff
++#define bCCKRxFACounterUpper 0xff000000
++#define bCCKRxHPAGCStart 0xe000
++#define bCCKRxHPAGCFinal 0x1c00
++#define bCCKRxFalseAlarmEnable 0x8000
++#define bCCKFACounterFreeze 0x4000
++#define bCCKTxPathSel 0x10000000
++#define bCCKDefaultRxPath 0xc000000
++#define bCCKOptionRxPath 0x3000000
++
++/* 6. PageE(0xE00) */
++#define bSTBCEn 0x4 /* Useless */
++#define bAntennaMapping 0x10
++#define bNss 0x20
++#define bCFOAntSumD 0x200
++#define bPHYCounterReset 0x8000000
++#define bCFOReportGet 0x4000000
++#define bOFDMContinueTx 0x10000000
++#define bOFDMSingleCarrier 0x20000000
++#define bOFDMSingleTone 0x40000000
++
++
++/*
++ * Other Definition
++ * */
++
++#define bEnable 0x1 /* Useless */
++#define bDisable 0x0
++
++/* byte endable for srwrite */
++#define bByte0 0x1 /* Useless */
++#define bByte1 0x2
++#define bByte2 0x4
++#define bByte3 0x8
++#define bWord0 0x3
++#define bWord1 0xc
++#define bDWord 0xf
++
++/* for PutRegsetting & GetRegSetting BitMask */
++#define bMaskByte0 0xff /* Reg 0xc50 rOFDM0_XAAGCCore~0xC6f */
++#define bMaskByte1 0xff00
++#define bMaskByte2 0xff0000
++#define bMaskByte3 0xff000000
++#define bMaskHWord 0xffff0000
++#define bMaskLWord 0x0000ffff
++#define bMaskDWord 0xffffffff
++#define bMaskH3Bytes 0xffffff00
++#define bMask12Bits 0xfff
++#define bMaskH4Bits 0xf0000000
++#define bMaskOFDM_D 0xffc00000
++#define bMaskCCK 0x3f3f3f3f
++
++
++/*--------------------------Define Parameters-------------------------------*/
++
++
++#endif
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/include/Hal8812PwrSeq.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/include/Hal8812PwrSeq.h
+--- linux-5.11.4/3rdparty/rtl8812au/include/Hal8812PwrSeq.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/include/Hal8812PwrSeq.h 2021-03-07 18:16:17.084957471 +0200
+@@ -0,0 +1,208 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++
++
++#ifndef __HAL8812PWRSEQ_H__
++#define __HAL8812PWRSEQ_H__
++
++#include "HalPwrSeqCmd.h"
++
++/*
++ Check document WB-110628-DZ-RTL8195 (Jaguar) Power Architecture-R04.pdf
++ There are 6 HW Power States:
++ 0: POFF--Power Off
++ 1: PDN--Power Down
++ 2: CARDEMU--Card Emulation
++ 3: ACT--Active Mode
++ 4: LPS--Low Power State
++ 5: SUS--Suspend
++
++ The transision from different states are defined below
++ TRANS_CARDEMU_TO_ACT
++ TRANS_ACT_TO_CARDEMU
++ TRANS_CARDEMU_TO_SUS
++ TRANS_SUS_TO_CARDEMU
++ TRANS_CARDEMU_TO_PDN
++ TRANS_ACT_TO_LPS
++ TRANS_LPS_TO_ACT
++
++ TRANS_END
++*/
++#define RTL8812_TRANS_CARDEMU_TO_ACT_STEPS 15
++#define RTL8812_TRANS_ACT_TO_CARDEMU_STEPS 15
++#define RTL8812_TRANS_CARDEMU_TO_SUS_STEPS 15
++#define RTL8812_TRANS_SUS_TO_CARDEMU_STEPS 15
++#define RTL8812_TRANS_CARDEMU_TO_PDN_STEPS 15
++#define RTL8812_TRANS_PDN_TO_CARDEMU_STEPS 15
++#define RTL8812_TRANS_ACT_TO_LPS_STEPS 15
++#define RTL8812_TRANS_LPS_TO_ACT_STEPS 15
++#define RTL8812_TRANS_END_STEPS 1
++
++
++#define RTL8812_TRANS_CARDEMU_TO_ACT \
++ /* format */ \
++ /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
++ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0},/* disable SW LPS 0x04[10]=0*/ \
++ {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, BIT1},/* wait till 0x04[17] = 1 power ready*/ \
++ /*{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0}, disable HWPDN 0x04[15]=0*/ \
++ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, 0},/* disable WL suspend*/ \
++ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* polling until return 0*/ \
++ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT0, 0},/**/ \
++ {0x0024, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0}, /* 0x24[1] Choose the type of buffer after xosc: nand*/ \
++ {0x0028, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3, 0}, /* 0x28[33] Choose the type of buffer after xosc: nand*/
++
++#define RTL8812_TRANS_ACT_TO_CARDEMU \
++ /* format */ \
++ /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
++ {0x0c00, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x04}, /* 0xc00[7:0] = 4 turn off 3-wire */ \
++ {0x0e00, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x04}, /* 0xe00[7:0] = 4 turn off 3-wire */ \
++ {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0}, /* 0x2[0] = 0 RESET BB, CLOSE RF */ \
++ {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/ \
++ {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0}, /* Whole BB is reset*/ \
++ /*{0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},//0x1F[7:0] = 0 turn off RF*/ \
++ /*{0x004E, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},//0x4C[23] = 0x4E[7] = 0, switch DPDT_SEL_P output from register 0x65[2] */ \
++ {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x2A}, /* 0x07[7:0] = 0x28 sps pwm mode 0x2a for BT coex*/ \
++ {0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x02, 0},/*0x8[1] = 0 ANA clk = 500k */ \
++ /*{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0 | BIT1, 0}, // 0x02[1:0] = 0 reset BB */ \
++ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*0x04[9] = 1 turn off MAC by HW state machine*/ \
++ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, 0}, /*wait till 0x04[9] = 0 polling until return 0 to disable*/
++
++#define RTL8812_TRANS_CARDEMU_TO_SUS \
++ /* format */ \
++ /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
++ {0x0042, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xF0, 0xcc},\
++ {0x0042, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xF0, 0xEC},\
++ {0x0043, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x07},/* gpio11 input mode, gpio10~8 output mode */ \
++ {0x0045, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/* gpio 0~7 output same value as input ?? */ \
++ {0x0046, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xff},/* gpio0~7 output mode */ \
++ {0x0047, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/* 0x47[7:0] = 00 gpio mode */ \
++ {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/* suspend option all off */ \
++ {0x0014, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x80, BIT7},/*0x14[7] = 1 turn on ZCD */ \
++ {0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x01, BIT0},/* 0x15[0] =1 trun on ZCD */ \
++ {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x10, BIT4},/*0x23[4] = 1 hpon LDO sleep mode */ \
++ {0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x02, 0},/*0x8[1] = 0 ANA clk = 500k */ \
++ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, BIT3}, /*0x04[11] = 2b'11 enable WL suspend for PCIe*/
++
++#define RTL8812_TRANS_SUS_TO_CARDEMU \
++ /* format */ \
++ /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
++ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, 0}, /*0x04[11] = 2b'01enable WL suspend*/ \
++ {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x10, 0},/*0x23[4] = 0 hpon LDO sleep mode leave */ \
++ {0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x01, 0},/* 0x15[0] =0 trun off ZCD */ \
++ {0x0014, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x80, 0},/*0x14[7] = 0 turn off ZCD */ \
++ {0x0046, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/* gpio0~7 input mode */ \
++ {0x0043, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/* gpio11 input mode, gpio10~8 input mode */
++
++#define RTL8812_TRANS_CARDEMU_TO_CARDDIS \
++ /* format */ \
++ /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
++ /**{0x0194, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0}, //0x194[0]=0 , disable 32K clock*/ \
++ /**{0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x94}, //0x93 = 0x94 , 90[30] =0 enable 500k ANA clock .switch clock from 12M to 500K , 90 [26] =0 disable EEprom loader clock*/ \
++ {0x0003, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0}, /*0x03[2] = 0, reset 8051*/ \
++ {0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x05}, /*0x80 = 05h if reload fw, fill the default value of host_CPU handshake field*/ \
++ {0x0042, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xF0, 0xcc},\
++ {0x0042, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xF0, 0xEC},\
++ {0x0043, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x07},/* gpio11 input mode, gpio10~8 output mode */ \
++ {0x0045, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/* gpio 0~7 output same value as input ?? */ \
++ {0x0046, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xff},/* gpio0~7 output mode */ \
++ {0x0047, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/* 0x47[7:0] = 00 gpio mode */ \
++ {0x0014, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x80, BIT7},/*0x14[7] = 1 turn on ZCD */ \
++ {0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x01, BIT0},/* 0x15[0] =1 trun on ZCD */ \
++ {0x0012, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x01, 0},/*0x12[0] = 0 force PFM mode */ \
++ {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x10, BIT4},/*0x23[4] = 1 hpon LDO sleep mode */ \
++ {0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x02, 0},/*0x8[1] = 0 ANA clk = 500k */ \
++ {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07 = 0x20 , SOP option to disable BG/MB*/ \
++ {0x001f, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0}, /*0x01f[1]=0 , disable RFC_0 control REG_RF_CTRL_8812 */ \
++ {0x0076, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0}, /*0x076[1]=0 , disable RFC_1 control REG_OPT_CTRL_8812 +2 */ \
++ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, BIT3}, /*0x04[11] = 2b'01 enable WL suspend*/
++
++#define RTL8812_TRANS_CARDDIS_TO_CARDEMU \
++ /* format */ \
++ /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
++ {0x0012, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/*0x12[0] = 1 force PWM mode */ \
++ {0x0014, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x80, 0},/*0x14[7] = 0 turn off ZCD */ \
++ {0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x01, 0},/* 0x15[0] =0 trun off ZCD */ \
++ {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x10, 0},/*0x23[4] = 0 hpon LDO leave sleep mode */ \
++ {0x0046, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/* gpio0~7 input mode */ \
++ {0x0043, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/* gpio11 input mode, gpio10~8 input mode */ \
++ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0}, /*0x04[10] = 0, enable SW LPS PCIE only*/ \
++ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, 0}, /*0x04[11] = 2b'01enable WL suspend*/ \
++ {0x0003, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, BIT2}, /*0x03[2] = 1, enable 8051*/ \
++ {0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/*PCIe DMA start*/ \
++ {0x0024, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1}, /* 0x24[1] Choose the type of buffer after xosc: schmitt trigger*/ \
++ {0x0028, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3, BIT3}, /* 0x28[33] Choose the type of buffer after xosc: schmitt trigger*/
++
++
++#define RTL8812_TRANS_CARDEMU_TO_PDN \
++ /* format */ \
++ /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
++ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7},/* 0x04[15] = 1*/
++
++#define RTL8812_TRANS_PDN_TO_CARDEMU \
++ /* format */ \
++ /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
++ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/* 0x04[15] = 0*/
++
++#define RTL8812_TRANS_ACT_TO_LPS \
++ /* format */ \
++ /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
++ {0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF},/*PCIe DMA stop*/ \
++ {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x7F},/*Tx Pause*/ \
++ {0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
++ {0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
++ {0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
++ {0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
++ {0x0c00, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x04}, /* 0xc00[7:0] = 4 turn off 3-wire */ \
++ {0x0e00, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x04}, /* 0xe00[7:0] = 4 turn off 3-wire */ \
++ {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled, and clock are gated, and RF closed*/ \
++ {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/ \
++ {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0}, /* Whole BB is reset*/ \
++ {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x03},/*Reset MAC TRX*/ \
++ {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*check if removed later*/ \
++ {0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5},/*Respond TxOK to scheduler*/
++
++
++#define RTL8812_TRANS_LPS_TO_ACT \
++ /* format */ \
++ /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
++ {0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM*/ \
++ {0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/ \
++ {0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/ \
++ {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /*Delay*/ \
++ {0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*. 0x08[4] = 0 switch TSF to 40M*/ \
++ {0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT7, 0}, /*Polling 0x109[7]=0 TSF in 40M*/ \
++ {0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6 | BIT7, 0}, /*. 0x29[7:6] = 2b'00 enable BB clock*/ \
++ {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*. 0x101[1] = 1*/ \
++ {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF}, /*. 0x100[7:0] = 0xFF enable WMAC TRX*/ \
++ {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1 | BIT0, BIT1 | BIT0}, /*. 0x02[1:0] = 2b'11 enable BB macro*/ \
++ {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, /*. 0x522 = 0*/
++
++#define RTL8812_TRANS_END \
++ /* format */ \
++ /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
++ {0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, 0, PWR_CMD_END, 0, 0},
++
++
++extern WLAN_PWR_CFG rtl8812_power_on_flow[RTL8812_TRANS_CARDEMU_TO_ACT_STEPS + RTL8812_TRANS_END_STEPS];
++extern WLAN_PWR_CFG rtl8812_radio_off_flow[RTL8812_TRANS_ACT_TO_CARDEMU_STEPS + RTL8812_TRANS_END_STEPS];
++extern WLAN_PWR_CFG rtl8812_card_disable_flow[RTL8812_TRANS_ACT_TO_CARDEMU_STEPS + RTL8812_TRANS_CARDEMU_TO_PDN_STEPS + RTL8812_TRANS_END_STEPS];
++extern WLAN_PWR_CFG rtl8812_card_enable_flow[RTL8812_TRANS_ACT_TO_CARDEMU_STEPS + RTL8812_TRANS_CARDEMU_TO_PDN_STEPS + RTL8812_TRANS_END_STEPS];
++extern WLAN_PWR_CFG rtl8812_suspend_flow[RTL8812_TRANS_ACT_TO_CARDEMU_STEPS + RTL8812_TRANS_CARDEMU_TO_SUS_STEPS + RTL8812_TRANS_END_STEPS];
++extern WLAN_PWR_CFG rtl8812_resume_flow[RTL8812_TRANS_ACT_TO_CARDEMU_STEPS + RTL8812_TRANS_CARDEMU_TO_SUS_STEPS + RTL8812_TRANS_END_STEPS];
++extern WLAN_PWR_CFG rtl8812_hwpdn_flow[RTL8812_TRANS_ACT_TO_CARDEMU_STEPS + RTL8812_TRANS_CARDEMU_TO_PDN_STEPS + RTL8812_TRANS_END_STEPS];
++extern WLAN_PWR_CFG rtl8812_enter_lps_flow[RTL8812_TRANS_ACT_TO_LPS_STEPS + RTL8812_TRANS_END_STEPS];
++extern WLAN_PWR_CFG rtl8812_leave_lps_flow[RTL8812_TRANS_LPS_TO_ACT_STEPS + RTL8812_TRANS_END_STEPS];
++
++#endif /* __HAL8812PWRSEQ_H__ */
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/include/Hal8814PhyCfg.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/include/Hal8814PhyCfg.h
+--- linux-5.11.4/3rdparty/rtl8812au/include/Hal8814PhyCfg.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/include/Hal8814PhyCfg.h 2021-03-07 18:16:17.084957471 +0200
+@@ -0,0 +1,264 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __INC_HAL8814PHYCFG_H__
++#define __INC_HAL8814PHYCFG_H__
++
++
++/*--------------------------Define Parameters-------------------------------*/
++#define LOOP_LIMIT 5
++#define MAX_STALL_TIME 50 /* us */
++#define AntennaDiversityValue 0x80 /* (Adapter->bSoftwareAntennaDiversity ? 0x00 : 0x80) */
++#define MAX_TXPWR_IDX_NMODE_92S 63
++#define Reset_Cnt_Limit 3
++
++
++#ifdef CONFIG_PCI_HCI
++ #define MAX_AGGR_NUM 0x0B
++#else
++ #define MAX_AGGR_NUM 0x07
++#endif /* CONFIG_PCI_HCI */
++
++
++/*--------------------------Define Parameters-------------------------------*/
++
++/*------------------------------Define structure----------------------------*/
++
++
++/* BB/RF related */
++
++#define SIC_ENABLE 0
++
++/*------------------------------Define structure----------------------------*/
++
++
++/*------------------------Export global variable----------------------------*/
++/*------------------------Export global variable----------------------------*/
++
++
++/*------------------------Export Marco Definition---------------------------*/
++/*------------------------Export Marco Definition---------------------------*/
++
++
++/*--------------------------Exported Function prototype---------------------*/
++/* 1. BB register R/W API */
++
++extern u32
++PHY_QueryBBReg8814A(IN PADAPTER Adapter,
++ IN u32 RegAddr,
++ IN u32 BitMask);
++
++
++VOID
++PHY_SetBBReg8814A(IN PADAPTER Adapter,
++ IN u32 RegAddr,
++ IN u32 BitMask,
++ IN u32 Data);
++
++
++extern u32
++PHY_QueryRFReg8814A(IN PADAPTER Adapter,
++ IN enum rf_path eRFPath,
++ IN u32 RegAddr,
++ IN u32 BitMask);
++
++
++void
++PHY_SetRFReg8814A(IN PADAPTER Adapter,
++ IN enum rf_path eRFPath,
++ IN u32 RegAddr,
++ IN u32 BitMask,
++ IN u32 Data);
++
++/* 1 3. Initial BB/RF config by reading MAC/BB/RF txt. */
++s32
++phy_BB8814A_Config_ParaFile(
++ IN PADAPTER Adapter
++);
++
++VOID
++PHY_ConfigBB_8814A(
++ IN PADAPTER Adapter
++);
++
++
++VOID
++phy_ADC_CLK_8814A(
++ IN PADAPTER Adapter
++);
++
++s32
++PHY_RFConfig8814A(
++ IN PADAPTER Adapter
++);
++
++/*
++ * RF Power setting
++ *
++ * BOOLEAN PHY_SetRFPowerState8814A(PADAPTER Adapter, rt_rf_power_state eRFPowerState); */
++
++/* 1 5. Tx Power setting API */
++
++VOID
++PHY_GetTxPowerLevel8814(
++ IN PADAPTER Adapter,
++ OUT ps4Byte powerlevel
++);
++
++VOID
++PHY_SetTxPowerLevel8814(
++ IN PADAPTER Adapter,
++ IN u8 Channel
++);
++
++u8
++phy_get_tx_power_index_8814a(
++ IN PADAPTER Adapter,
++ IN enum rf_path RFPath,
++ IN u8 Rate,
++ IN enum channel_width BandWidth,
++ IN u8 Channel
++);
++
++u8
++PHY_GetTxPowerIndex8814A(
++ IN PADAPTER Adapter,
++ IN enum rf_path RFPath,
++ IN u8 Rate,
++ IN u8 BandWidth,
++ IN u8 Channel,
++ struct txpwr_idx_comp *tic
++);
++
++VOID
++PHY_SetTxPowerIndex_8814A(
++ IN PADAPTER Adapter,
++ IN u32 PowerIndex,
++ IN enum rf_path RFPath,
++ IN u8 Rate
++);
++
++
++BOOLEAN
++PHY_UpdateTxPowerDbm8814A(
++ IN PADAPTER Adapter,
++ IN s4Byte powerInDbm
++);
++
++
++u32
++PHY_GetTxBBSwing_8814A(
++ IN PADAPTER Adapter,
++ IN BAND_TYPE Band,
++ IN enum rf_path RFPath
++);
++
++
++
++/* 1 6. Channel setting API */
++#if 0
++VOID
++PHY_SwChnlTimerCallback8814A(
++ IN struct timer_list *p_timer
++);
++#endif
++VOID
++PHY_SwChnlWorkItemCallback8814A(
++ IN PVOID pContext
++);
++
++
++VOID
++HAL_HandleSwChnl8814A(
++ IN PADAPTER pAdapter,
++ IN u8 channel
++);
++
++VOID
++PHY_SwChnlSynchronously8814A(IN PADAPTER pAdapter,
++ IN u8 channel);
++
++VOID
++PHY_SwChnlAndSetBWModeCallback8814A(IN PVOID pContext);
++
++
++VOID
++PHY_HandleSwChnlAndSetBW8814A(
++ IN PADAPTER Adapter,
++ IN BOOLEAN bSwitchChannel,
++ IN BOOLEAN bSetBandWidth,
++ IN u8 ChannelNum,
++ IN enum channel_width ChnlWidth,
++ IN u8 ChnlOffsetOf40MHz,
++ IN u8 ChnlOffsetOf80MHz,
++ IN u8 CenterFrequencyIndex1
++);
++
++
++BOOLEAN
++PHY_QueryRFPathSwitch_8814A(IN PADAPTER pAdapter);
++
++
++
++#if (USE_WORKITEM)
++VOID
++RtCheckForHangWorkItemCallback8814A(
++ IN PVOID pContext
++);
++#endif
++
++BOOLEAN
++SetAntennaConfig8814A(
++ IN PADAPTER Adapter,
++ IN u8 DefaultAnt
++);
++
++VOID
++PHY_SetRFEReg8814A(
++ IN PADAPTER Adapter,
++ IN BOOLEAN bInit,
++ IN u8 Band
++);
++
++
++s32
++PHY_SwitchWirelessBand8814A(
++ IN PADAPTER Adapter,
++ IN u8 Band
++);
++
++VOID
++PHY_SetIO_8814A(
++ PADAPTER pAdapter
++);
++
++VOID
++PHY_SetSwChnlBWMode8814(
++ IN PADAPTER Adapter,
++ IN u8 channel,
++ IN enum channel_width Bandwidth,
++ IN u8 Offset40,
++ IN u8 Offset80
++);
++
++s32 PHY_MACConfig8814(PADAPTER Adapter);
++int PHY_BBConfig8814(PADAPTER Adapter);
++VOID PHY_Set_SecCCATH_by_RXANT_8814A(PADAPTER pAdapter, u4Byte ulAntennaRx);
++
++
++
++/*--------------------------Exported Function prototype---------------------*/
++
++/*--------------------------Exported Function prototype---------------------*/
++#endif /* __INC_HAL8192CPHYCFG_H */
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/include/Hal8814PhyReg.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/include/Hal8814PhyReg.h
+--- linux-5.11.4/3rdparty/rtl8812au/include/Hal8814PhyReg.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/include/Hal8814PhyReg.h 2021-03-07 18:16:17.084957471 +0200
+@@ -0,0 +1,863 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __INC_HAL8814PHYREG_H__
++#define __INC_HAL8814PHYREG_H__
++/*--------------------------Define Parameters-------------------------------*/
++/*
++ * BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF
++ * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF
++ * 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00
++ * 3. RF register 0x00-2E
++ * 4. Bit Mask for BB/RF register
++ * 5. Other defintion for BB/RF R/W
++ * */
++
++
++/* BB Register Definition */
++
++#define rCCAonSec_Jaguar 0x838
++#define rPwed_TH_Jaguar 0x830
++#define rL1_Weight_Jaguar 0x840
++#define r_L1_SBD_start_time 0x844
++
++/* BW and sideband setting */
++#define rBWIndication_Jaguar 0x834
++#define rL1PeakTH_Jaguar 0x848
++#define rRFMOD_Jaguar 0x8ac /* RF mode */
++#define rADC_Buf_Clk_Jaguar 0x8c4
++#define rADC_Buf_40_Clk_Jaguar2 0x8c8
++#define rRFECTRL_Jaguar 0x900
++#define bRFMOD_Jaguar 0xc3
++#define rCCK_System_Jaguar 0xa00 /* for cck sideband */
++#define bCCK_System_Jaguar 0x10
++
++/* Block & Path enable */
++#define rOFDMCCKEN_Jaguar 0x808 /* OFDM/CCK block enable */
++#define bOFDMEN_Jaguar 0x20000000
++#define bCCKEN_Jaguar 0x10000000
++#define rRxPath_Jaguar 0x808 /* Rx antenna */
++#define bRxPath_Jaguar 0xff
++#define rTxPath_Jaguar 0x80c /* Tx antenna */
++#define bTxPath_Jaguar 0x0fffffff
++#define rCCK_RX_Jaguar 0xa04 /* for cck rx path selection */
++#define bCCK_RX_Jaguar 0x0c000000
++#define rVhtlen_Use_Lsig_Jaguar 0x8c3 /* Use LSIG for VHT length */
++
++#define rRxPath_Jaguar2 0xa04 /* Rx antenna */
++#define rTxAnt_1Nsts_Jaguar2 0x93c /* Tx antenna for 1Nsts */
++#define rTxAnt_23Nsts_Jaguar2 0x940 /* Tx antenna for 2Nsts and 3Nsts */
++
++
++/* RF read/write-related */
++#define rHSSIRead_Jaguar 0x8b0 /* RF read addr */
++#define bHSSIRead_addr_Jaguar 0xff
++#define bHSSIRead_trigger_Jaguar 0x100
++#define rA_PIRead_Jaguar 0xd04 /* RF readback with PI */
++#define rB_PIRead_Jaguar 0xd44 /* RF readback with PI */
++#define rA_SIRead_Jaguar 0xd08 /* RF readback with SI */
++#define rB_SIRead_Jaguar 0xd48 /* RF readback with SI */
++#define rRead_data_Jaguar 0xfffff
++#define rA_LSSIWrite_Jaguar 0xc90 /* RF write addr */
++#define rB_LSSIWrite_Jaguar 0xe90 /* RF write addr */
++#define bLSSIWrite_data_Jaguar 0x000fffff
++#define bLSSIWrite_addr_Jaguar 0x0ff00000
++
++#define rC_PIRead_Jaguar2 0xd84 /* RF readback with PI */
++#define rD_PIRead_Jaguar2 0xdC4 /* RF readback with PI */
++#define rC_SIRead_Jaguar2 0xd88 /* RF readback with SI */
++#define rD_SIRead_Jaguar2 0xdC8 /* RF readback with SI */
++#define rC_LSSIWrite_Jaguar2 0x1890 /* RF write addr */
++#define rD_LSSIWrite_Jaguar2 0x1A90 /* RF write addr */
++
++
++/* YN: mask the following register definition temporarily */
++#define rFPGA0_XA_RFInterfaceOE 0x860 /* RF Channel switch */
++#define rFPGA0_XB_RFInterfaceOE 0x864
++
++#define rFPGA0_XAB_RFInterfaceSW 0x870 /* RF Interface Software Control */
++#define rFPGA0_XCD_RFInterfaceSW 0x874
++
++/* #define rFPGA0_XAB_RFParameter 0x878 */ /* RF Parameter
++ * #define rFPGA0_XCD_RFParameter 0x87c */
++
++/* #define rFPGA0_AnalogParameter1 0x880 */ /* Crystal cap setting RF-R/W protection for parameter4??
++ * #define rFPGA0_AnalogParameter2 0x884
++ * #define rFPGA0_AnalogParameter3 0x888
++ * #define rFPGA0_AdDaClockEn 0x888 */ /* enable ad/da clock1 for dual-phy
++ * #define rFPGA0_AnalogParameter4 0x88c */
++
++
++/* CCK TX scaling */
++#define rCCK_TxFilter1_Jaguar 0xa20
++#define bCCK_TxFilter1_C0_Jaguar 0x00ff0000
++#define bCCK_TxFilter1_C1_Jaguar 0xff000000
++#define rCCK_TxFilter2_Jaguar 0xa24
++#define bCCK_TxFilter2_C2_Jaguar 0x000000ff
++#define bCCK_TxFilter2_C3_Jaguar 0x0000ff00
++#define bCCK_TxFilter2_C4_Jaguar 0x00ff0000
++#define bCCK_TxFilter2_C5_Jaguar 0xff000000
++#define rCCK_TxFilter3_Jaguar 0xa28
++#define bCCK_TxFilter3_C6_Jaguar 0x000000ff
++#define bCCK_TxFilter3_C7_Jaguar 0x0000ff00
++/* NBI & CSI Mask setting */
++#define rCSI_Mask_Setting1_Jaguar 0x874
++#define rCSI_Fix_Mask0_Jaguar 0x880
++#define rCSI_Fix_Mask1_Jaguar 0x884
++#define rCSI_Fix_Mask2_Jaguar 0x888
++#define rCSI_Fix_Mask3_Jaguar 0x88c
++#define rCSI_Fix_Mask4_Jaguar 0x890
++#define rCSI_Fix_Mask5_Jaguar 0x894
++#define rCSI_Fix_Mask6_Jaguar 0x898
++#define rCSI_Fix_Mask7_Jaguar 0x89c
++#define rNBI_Setting_Jaguar 0x87c
++
++
++/* YN: mask the following register definition temporarily
++ * #define rPdp_AntA 0xb00
++ * #define rPdp_AntA_4 0xb04
++ * #define rConfig_Pmpd_AntA 0xb28
++ * #define rConfig_AntA 0xb68
++ * #define rConfig_AntB 0xb6c
++ * #define rPdp_AntB 0xb70
++ * #define rPdp_AntB_4 0xb74
++ * #define rConfig_Pmpd_AntB 0xb98
++ * #define rAPK 0xbd8 */
++
++/* RXIQC */
++#define rA_RxIQC_AB_Jaguar 0xc10 /* RxIQ imblance matrix coeff. A & B */
++#define rA_RxIQC_CD_Jaguar 0xc14 /* RxIQ imblance matrix coeff. C & D */
++#define rA_TxScale_Jaguar 0xc1c /* Pah_A TX scaling factor */
++#define rB_TxScale_Jaguar 0xe1c /* Path_B TX scaling factor */
++#define rB_RxIQC_AB_Jaguar 0xe10 /* RxIQ imblance matrix coeff. A & B */
++#define rB_RxIQC_CD_Jaguar 0xe14 /* RxIQ imblance matrix coeff. C & D */
++#define b_RxIQC_AC_Jaguar 0x02ff /* bit mask for IQC matrix element A & C */
++#define b_RxIQC_BD_Jaguar 0x02ff0000 /* bit mask for IQC matrix element A & C */
++
++#define rC_TxScale_Jaguar2 0x181c /* Pah_C TX scaling factor */
++#define rD_TxScale_Jaguar2 0x1A1c /* Path_D TX scaling factor */
++#define rRF_TxGainOffset 0x55
++
++/* DIG-related */
++#define rA_IGI_Jaguar 0xc50 /* Initial Gain for path-A */
++#define rB_IGI_Jaguar 0xe50 /* Initial Gain for path-B */
++#define rC_IGI_Jaguar2 0x1850 /* Initial Gain for path-C */
++#define rD_IGI_Jaguar2 0x1A50 /* Initial Gain for path-D */
++
++#define rOFDM_FalseAlarm1_Jaguar 0xf48 /* counter for break */
++#define rOFDM_FalseAlarm2_Jaguar 0xf4c /* counter for spoofing */
++#define rCCK_FalseAlarm_Jaguar 0xa5c /* counter for cck false alarm */
++#define b_FalseAlarm_Jaguar 0xffff
++#define rCCK_CCA_Jaguar 0xa08 /* cca threshold */
++#define bCCK_CCA_Jaguar 0x00ff0000
++
++/* Tx Power Ttraining-related */
++#define rA_TxPwrTraing_Jaguar 0xc54
++#define rB_TxPwrTraing_Jaguar 0xe54
++
++/* Report-related */
++#define rOFDM_ShortCFOAB_Jaguar 0xf60
++#define rOFDM_LongCFOAB_Jaguar 0xf64
++#define rOFDM_EndCFOAB_Jaguar 0xf70
++#define rOFDM_AGCReport_Jaguar 0xf84
++#define rOFDM_RxSNR_Jaguar 0xf88
++#define rOFDM_RxEVMCSI_Jaguar 0xf8c
++#define rOFDM_SIGReport_Jaguar 0xf90
++
++/* Misc functions */
++#define rEDCCA_Jaguar 0x8a4 /* EDCCA */
++#define bEDCCA_Jaguar 0xffff
++#define rAGC_table_Jaguar 0x82c /* AGC tabel select */
++#define bAGC_table_Jaguar 0x3
++#define b_sel5g_Jaguar 0x1000 /* sel5g */
++#define b_LNA_sw_Jaguar 0x8000 /* HW/WS control for LNA */
++#define rFc_area_Jaguar 0x860 /* fc_area */
++#define bFc_area_Jaguar 0x1ffe000
++#define rSingleTone_ContTx_Jaguar 0x914
++
++#define rAGC_table_Jaguar2 0x958 /* AGC tabel select */
++#define rDMA_trigger_Jaguar2 0x95C /* ADC sample mode */
++
++
++/* RFE */
++#define rA_RFE_Pinmux_Jaguar 0xcb0 /* Path_A RFE cotrol pinmux */
++#define rB_RFE_Pinmux_Jaguar 0xeb0 /* Path_B RFE control pinmux */
++#define rA_RFE_Inv_Jaguar 0xcb4 /* Path_A RFE cotrol */
++#define rB_RFE_Inv_Jaguar 0xeb4 /* Path_B RFE control */
++#define rA_RFE_Jaguar 0xcb8 /* Path_A RFE cotrol */
++#define rB_RFE_Jaguar 0xeb8 /* Path_B RFE control */
++#define rA_RFE_Inverse_Jaguar 0xCBC /* Path_A RFE control inverse */
++#define rB_RFE_Inverse_Jaguar 0xEBC /* Path_B RFE control inverse */
++#define r_ANTSEL_SW_Jaguar 0x900 /* ANTSEL SW Control */
++#define bMask_RFEInv_Jaguar 0x3ff00000
++#define bMask_AntselPathFollow_Jaguar 0x00030000
++
++#define rC_RFE_Pinmux_Jaguar 0x18B4 /* Path_C RFE cotrol pinmux */
++#define rD_RFE_Pinmux_Jaguar 0x1AB4 /* Path_D RFE cotrol pinmux */
++#define rA_RFE_Sel_Jaguar2 0x1990
++
++
++
++/* TX AGC */
++#define rTxAGC_A_CCK11_CCK1_JAguar 0xc20
++#define rTxAGC_A_Ofdm18_Ofdm6_JAguar 0xc24
++#define rTxAGC_A_Ofdm54_Ofdm24_JAguar 0xc28
++#define rTxAGC_A_MCS3_MCS0_JAguar 0xc2c
++#define rTxAGC_A_MCS7_MCS4_JAguar 0xc30
++#define rTxAGC_A_MCS11_MCS8_JAguar 0xc34
++#define rTxAGC_A_MCS15_MCS12_JAguar 0xc38
++#define rTxAGC_A_Nss1Index3_Nss1Index0_JAguar 0xc3c
++#define rTxAGC_A_Nss1Index7_Nss1Index4_JAguar 0xc40
++#define rTxAGC_A_Nss2Index1_Nss1Index8_JAguar 0xc44
++#define rTxAGC_A_Nss2Index5_Nss2Index2_JAguar 0xc48
++#define rTxAGC_A_Nss2Index9_Nss2Index6_JAguar 0xc4c
++#define rTxAGC_B_CCK11_CCK1_JAguar 0xe20
++#define rTxAGC_B_Ofdm18_Ofdm6_JAguar 0xe24
++#define rTxAGC_B_Ofdm54_Ofdm24_JAguar 0xe28
++#define rTxAGC_B_MCS3_MCS0_JAguar 0xe2c
++#define rTxAGC_B_MCS7_MCS4_JAguar 0xe30
++#define rTxAGC_B_MCS11_MCS8_JAguar 0xe34
++#define rTxAGC_B_MCS15_MCS12_JAguar 0xe38
++#define rTxAGC_B_Nss1Index3_Nss1Index0_JAguar 0xe3c
++#define rTxAGC_B_Nss1Index7_Nss1Index4_JAguar 0xe40
++#define rTxAGC_B_Nss2Index1_Nss1Index8_JAguar 0xe44
++#define rTxAGC_B_Nss2Index5_Nss2Index2_JAguar 0xe48
++#define rTxAGC_B_Nss2Index9_Nss2Index6_JAguar 0xe4c
++#define bTxAGC_byte0_Jaguar 0xff
++#define bTxAGC_byte1_Jaguar 0xff00
++#define bTxAGC_byte2_Jaguar 0xff0000
++#define bTxAGC_byte3_Jaguar 0xff000000
++
++
++/* TX AGC */
++#define rTxAGC_A_CCK11_CCK1_Jaguar2 0xc20
++#define rTxAGC_A_Ofdm18_Ofdm6_Jaguar2 0xc24
++#define rTxAGC_A_Ofdm54_Ofdm24_Jaguar2 0xc28
++#define rTxAGC_A_MCS3_MCS0_Jaguar2 0xc2c
++#define rTxAGC_A_MCS7_MCS4_Jaguar2 0xc30
++#define rTxAGC_A_MCS11_MCS8_Jaguar2 0xc34
++#define rTxAGC_A_MCS15_MCS12_Jaguar2 0xc38
++#define rTxAGC_A_MCS19_MCS16_Jaguar2 0xcd8
++#define rTxAGC_A_MCS23_MCS20_Jaguar2 0xcdc
++#define rTxAGC_A_Nss1Index3_Nss1Index0_Jaguar2 0xc3c
++#define rTxAGC_A_Nss1Index7_Nss1Index4_Jaguar2 0xc40
++#define rTxAGC_A_Nss2Index1_Nss1Index8_Jaguar2 0xc44
++#define rTxAGC_A_Nss2Index5_Nss2Index2_Jaguar2 0xc48
++#define rTxAGC_A_Nss2Index9_Nss2Index6_Jaguar2 0xc4c
++#define rTxAGC_A_Nss3Index3_Nss3Index0_Jaguar2 0xce0
++#define rTxAGC_A_Nss3Index7_Nss3Index4_Jaguar2 0xce4
++#define rTxAGC_A_Nss3Index9_Nss3Index8_Jaguar2 0xce8
++#define rTxAGC_B_CCK11_CCK1_Jaguar2 0xe20
++#define rTxAGC_B_Ofdm18_Ofdm6_Jaguar2 0xe24
++#define rTxAGC_B_Ofdm54_Ofdm24_Jaguar2 0xe28
++#define rTxAGC_B_MCS3_MCS0_Jaguar2 0xe2c
++#define rTxAGC_B_MCS7_MCS4_Jaguar2 0xe30
++#define rTxAGC_B_MCS11_MCS8_Jaguar2 0xe34
++#define rTxAGC_B_MCS15_MCS12_Jaguar2 0xe38
++#define rTxAGC_B_MCS19_MCS16_Jaguar2 0xed8
++#define rTxAGC_B_MCS23_MCS20_Jaguar2 0xedc
++#define rTxAGC_B_Nss1Index3_Nss1Index0_Jaguar2 0xe3c
++#define rTxAGC_B_Nss1Index7_Nss1Index4_Jaguar2 0xe40
++#define rTxAGC_B_Nss2Index1_Nss1Index8_Jaguar2 0xe44
++#define rTxAGC_B_Nss2Index5_Nss2Index2_Jaguar2 0xe48
++#define rTxAGC_B_Nss2Index9_Nss2Index6_Jaguar2 0xe4c
++#define rTxAGC_B_Nss3Index3_Nss3Index0_Jaguar2 0xee0
++#define rTxAGC_B_Nss3Index7_Nss3Index4_Jaguar2 0xee4
++#define rTxAGC_B_Nss3Index9_Nss3Index8_Jaguar2 0xee8
++#define rTxAGC_C_CCK11_CCK1_Jaguar2 0x1820
++#define rTxAGC_C_Ofdm18_Ofdm6_Jaguar2 0x1824
++#define rTxAGC_C_Ofdm54_Ofdm24_Jaguar2 0x1828
++#define rTxAGC_C_MCS3_MCS0_Jaguar2 0x182c
++#define rTxAGC_C_MCS7_MCS4_Jaguar2 0x1830
++#define rTxAGC_C_MCS11_MCS8_Jaguar2 0x1834
++#define rTxAGC_C_MCS15_MCS12_Jaguar2 0x1838
++#define rTxAGC_C_MCS19_MCS16_Jaguar2 0x18d8
++#define rTxAGC_C_MCS23_MCS20_Jaguar2 0x18dc
++#define rTxAGC_C_Nss1Index3_Nss1Index0_Jaguar2 0x183c
++#define rTxAGC_C_Nss1Index7_Nss1Index4_Jaguar2 0x1840
++#define rTxAGC_C_Nss2Index1_Nss1Index8_Jaguar2 0x1844
++#define rTxAGC_C_Nss2Index5_Nss2Index2_Jaguar2 0x1848
++#define rTxAGC_C_Nss2Index9_Nss2Index6_Jaguar2 0x184c
++#define rTxAGC_C_Nss3Index3_Nss3Index0_Jaguar2 0x18e0
++#define rTxAGC_C_Nss3Index7_Nss3Index4_Jaguar2 0x18e4
++#define rTxAGC_C_Nss3Index9_Nss3Index8_Jaguar2 0x18e8
++#define rTxAGC_D_CCK11_CCK1_Jaguar2 0x1a20
++#define rTxAGC_D_Ofdm18_Ofdm6_Jaguar2 0x1a24
++#define rTxAGC_D_Ofdm54_Ofdm24_Jaguar2 0x1a28
++#define rTxAGC_D_MCS3_MCS0_Jaguar2 0x1a2c
++#define rTxAGC_D_MCS7_MCS4_Jaguar2 0x1a30
++#define rTxAGC_D_MCS11_MCS8_Jaguar2 0x1a34
++#define rTxAGC_D_MCS15_MCS12_Jaguar2 0x1a38
++#define rTxAGC_D_MCS19_MCS16_Jaguar2 0x1ad8
++#define rTxAGC_D_MCS23_MCS20_Jaguar2 0x1adc
++#define rTxAGC_D_Nss1Index3_Nss1Index0_Jaguar2 0x1a3c
++#define rTxAGC_D_Nss1Index7_Nss1Index4_Jaguar2 0x1a40
++#define rTxAGC_D_Nss2Index1_Nss1Index8_Jaguar2 0x1a44
++#define rTxAGC_D_Nss2Index5_Nss2Index2_Jaguar2 0x1a48
++#define rTxAGC_D_Nss2Index9_Nss2Index6_Jaguar2 0x1a4c
++#define rTxAGC_D_Nss3Index3_Nss3Index0_Jaguar2 0x1ae0
++#define rTxAGC_D_Nss3Index7_Nss3Index4_Jaguar2 0x1ae4
++#define rTxAGC_D_Nss3Index9_Nss3Index8_Jaguar2 0x1ae8
++/* IQK YN: temporaily mask this part
++ * #define rFPGA0_IQK 0xe28
++ * #define rTx_IQK_Tone_A 0xe30
++ * #define rRx_IQK_Tone_A 0xe34
++ * #define rTx_IQK_PI_A 0xe38
++ * #define rRx_IQK_PI_A 0xe3c */
++
++/* #define rTx_IQK 0xe40 */
++/* #define rRx_IQK 0xe44 */
++/* #define rIQK_AGC_Pts 0xe48 */
++/* #define rIQK_AGC_Rsp 0xe4c */
++/* #define rTx_IQK_Tone_B 0xe50 */
++/* #define rRx_IQK_Tone_B 0xe54 */
++/* #define rTx_IQK_PI_B 0xe58 */
++/* #define rRx_IQK_PI_B 0xe5c */
++/* #define rIQK_AGC_Cont 0xe60 */
++
++
++/* AFE-related */
++#define rA_AFEPwr1_Jaguar 0xc60 /* dynamic AFE power control */
++#define rA_AFEPwr2_Jaguar 0xc64 /* dynamic AFE power control */
++#define rA_Rx_WaitCCA_Tx_CCKRFON_Jaguar 0xc68
++#define rA_Tx_CCKBBON_OFDMRFON_Jaguar 0xc6c
++#define rA_Tx_OFDMBBON_Tx2Rx_Jaguar 0xc70
++#define rA_Tx2Tx_RXCCK_Jaguar 0xc74
++#define rA_Rx_OFDM_WaitRIFS_Jaguar 0xc78
++#define rA_Rx2Rx_BT_Jaguar 0xc7c
++#define rA_sleep_nav_Jaguar 0xc80
++#define rA_pmpd_Jaguar 0xc84
++#define rB_AFEPwr1_Jaguar 0xe60 /* dynamic AFE power control */
++#define rB_AFEPwr2_Jaguar 0xe64 /* dynamic AFE power control */
++#define rB_Rx_WaitCCA_Tx_CCKRFON_Jaguar 0xe68
++#define rB_Tx_CCKBBON_OFDMRFON_Jaguar 0xe6c
++#define rB_Tx_OFDMBBON_Tx2Rx_Jaguar 0xe70
++#define rB_Tx2Tx_RXCCK_Jaguar 0xe74
++#define rB_Rx_OFDM_WaitRIFS_Jaguar 0xe78
++#define rB_Rx2Rx_BT_Jaguar 0xe7c
++#define rB_sleep_nav_Jaguar 0xe80
++#define rB_pmpd_Jaguar 0xe84
++
++
++/* YN: mask these registers temporaily
++ * #define rTx_Power_Before_IQK_A 0xe94
++ * #define rTx_Power_After_IQK_A 0xe9c */
++
++/* #define rRx_Power_Before_IQK_A 0xea0 */
++/* #define rRx_Power_Before_IQK_A_2 0xea4 */
++/* #define rRx_Power_After_IQK_A 0xea8 */
++/* #define rRx_Power_After_IQK_A_2 0xeac */
++
++/* #define rTx_Power_Before_IQK_B 0xeb4 */
++/* #define rTx_Power_After_IQK_B 0xebc */
++
++/* #define rRx_Power_Before_IQK_B 0xec0 */
++/* #define rRx_Power_Before_IQK_B_2 0xec4 */
++/* #define rRx_Power_After_IQK_B 0xec8 */
++/* #define rRx_Power_After_IQK_B_2 0xecc */
++
++
++/* RSSI Dump */
++#define rA_RSSIDump_Jaguar 0xBF0
++#define rB_RSSIDump_Jaguar 0xBF1
++#define rS1_RXevmDump_Jaguar 0xBF4
++#define rS2_RXevmDump_Jaguar 0xBF5
++#define rA_RXsnrDump_Jaguar 0xBF6
++#define rB_RXsnrDump_Jaguar 0xBF7
++#define rA_CfoShortDump_Jaguar 0xBF8
++#define rB_CfoShortDump_Jaguar 0xBFA
++#define rA_CfoLongDump_Jaguar 0xBEC
++#define rB_CfoLongDump_Jaguar 0xBEE
++
++
++/* RF Register
++ * */
++#define RF_AC_Jaguar 0x00 /* */
++#define RF_RF_Top_Jaguar 0x07 /* */
++#define RF_TXLOK_Jaguar 0x08 /* */
++#define RF_TXAPK_Jaguar 0x0B
++#define RF_CHNLBW_Jaguar 0x18 /* RF channel and BW switch */
++#define RF_RCK1_Jaguar 0x1c /* */
++#define RF_RCK2_Jaguar 0x1d
++#define RF_RCK3_Jaguar 0x1e
++#define RF_ModeTableAddr 0x30
++#define RF_ModeTableData0 0x31
++#define RF_ModeTableData1 0x32
++#define RF_TxLCTank_Jaguar 0x54
++#define RF_APK_Jaguar 0x63
++#define RF_LCK 0xB4
++#define RF_WeLut_Jaguar 0xEF
++
++#define bRF_CHNLBW_MOD_AG_Jaguar 0x70300
++#define bRF_CHNLBW_BW 0xc00
++
++
++/*
++ * RL6052 Register definition
++ * */
++#define RF_AC 0x00 /* */
++#define RF_IPA_A 0x0C /* */
++#define RF_TXBIAS_A 0x0D
++#define RF_BS_PA_APSET_G9_G11 0x0E
++#define RF_MODE1 0x10 /* */
++#define RF_MODE2 0x11 /* */
++#define RF_CHNLBW 0x18 /* RF channel and BW switch */
++#define RF_RCK_OS 0x30 /* RF TX PA control */
++#define RF_TXPA_G1 0x31 /* RF TX PA control */
++#define RF_TXPA_G2 0x32 /* RF TX PA control */
++#define RF_TXPA_G3 0x33 /* RF TX PA control */
++#define RF_0x52 0x52
++#define RF_WE_LUT 0xEF
++
++/*
++ * Bit Mask
++ *
++ * 1. Page1(0x100) */
++#define bBBResetB 0x100 /* Useless now? */
++#define bGlobalResetB 0x200
++#define bOFDMTxStart 0x4
++#define bCCKTxStart 0x8
++#define bCRC32Debug 0x100
++#define bPMACLoopback 0x10
++#define bTxLSIG 0xffffff
++#define bOFDMTxRate 0xf
++#define bOFDMTxReserved 0x10
++#define bOFDMTxLength 0x1ffe0
++#define bOFDMTxParity 0x20000
++#define bTxHTSIG1 0xffffff
++#define bTxHTMCSRate 0x7f
++#define bTxHTBW 0x80
++#define bTxHTLength 0xffff00
++#define bTxHTSIG2 0xffffff
++#define bTxHTSmoothing 0x1
++#define bTxHTSounding 0x2
++#define bTxHTReserved 0x4
++#define bTxHTAggreation 0x8
++#define bTxHTSTBC 0x30
++#define bTxHTAdvanceCoding 0x40
++#define bTxHTShortGI 0x80
++#define bTxHTNumberHT_LTF 0x300
++#define bTxHTCRC8 0x3fc00
++#define bCounterReset 0x10000
++#define bNumOfOFDMTx 0xffff
++#define bNumOfCCKTx 0xffff0000
++#define bTxIdleInterval 0xffff
++#define bOFDMService 0xffff0000
++#define bTxMACHeader 0xffffffff
++#define bTxDataInit 0xff
++#define bTxHTMode 0x100
++#define bTxDataType 0x30000
++#define bTxRandomSeed 0xffffffff
++#define bCCKTxPreamble 0x1
++#define bCCKTxSFD 0xffff0000
++#define bCCKTxSIG 0xff
++#define bCCKTxService 0xff00
++#define bCCKLengthExt 0x8000
++#define bCCKTxLength 0xffff0000
++#define bCCKTxCRC16 0xffff
++#define bCCKTxStatus 0x1
++#define bOFDMTxStatus 0x2
++
++
++/*
++ * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF
++ * 1. Page1(0x100)
++ * */
++#define rPMAC_Reset 0x100
++#define rPMAC_TxStart 0x104
++#define rPMAC_TxLegacySIG 0x108
++#define rPMAC_TxHTSIG1 0x10c
++#define rPMAC_TxHTSIG2 0x110
++#define rPMAC_PHYDebug 0x114
++#define rPMAC_TxPacketNum 0x118
++#define rPMAC_TxIdle 0x11c
++#define rPMAC_TxMACHeader0 0x120
++#define rPMAC_TxMACHeader1 0x124
++#define rPMAC_TxMACHeader2 0x128
++#define rPMAC_TxMACHeader3 0x12c
++#define rPMAC_TxMACHeader4 0x130
++#define rPMAC_TxMACHeader5 0x134
++#define rPMAC_TxDataType 0x138
++#define rPMAC_TxRandomSeed 0x13c
++#define rPMAC_CCKPLCPPreamble 0x140
++#define rPMAC_CCKPLCPHeader 0x144
++#define rPMAC_CCKCRC16 0x148
++#define rPMAC_OFDMRxCRC32OK 0x170
++#define rPMAC_OFDMRxCRC32Er 0x174
++#define rPMAC_OFDMRxParityEr 0x178
++#define rPMAC_OFDMRxCRC8Er 0x17c
++#define rPMAC_CCKCRxRC16Er 0x180
++#define rPMAC_CCKCRxRC32Er 0x184
++#define rPMAC_CCKCRxRC32OK 0x188
++#define rPMAC_TxStatus 0x18c
++
++/*
++ * 3. Page8(0x800)
++ * */
++#define rFPGA0_RFMOD 0x800 /* RF mode & CCK TxSC */ /* RF BW Setting?? */
++
++#define rFPGA0_TxInfo 0x804 /* Status report?? */
++#define rFPGA0_PSDFunction 0x808
++#define rFPGA0_TxGainStage 0x80c /* Set TX PWR init gain? */
++
++#define rFPGA0_XA_HSSIParameter1 0x820 /* RF 3 wire register */
++#define rFPGA0_XA_HSSIParameter2 0x824
++#define rFPGA0_XB_HSSIParameter1 0x828
++#define rFPGA0_XB_HSSIParameter2 0x82c
++
++#define rFPGA0_XA_LSSIParameter 0x840
++#define rFPGA0_XB_LSSIParameter 0x844
++
++#define rFPGA0_XAB_SwitchControl 0x858 /* RF Channel switch */
++#define rFPGA0_XCD_SwitchControl 0x85c
++
++#define rFPGA0_XAB_RFParameter 0x878 /* RF Parameter */
++#define rFPGA0_XCD_RFParameter 0x87c
++
++#define rFPGA0_AnalogParameter1 0x880 /* Crystal cap setting RF-R/W protection for parameter4?? */
++#define rFPGA0_AnalogParameter2 0x884
++#define rFPGA0_AnalogParameter3 0x888
++#define rFPGA0_AdDaClockEn 0x888 /* enable ad/da clock1 for dual-phy */
++#define rFPGA0_AnalogParameter4 0x88c
++
++#define rFPGA0_XA_LSSIReadBack 0x8a0 /* Tranceiver LSSI Readback */
++#define rFPGA0_XB_LSSIReadBack 0x8a4
++#define rFPGA0_XC_LSSIReadBack 0x8a8
++#define rFPGA0_XD_LSSIReadBack 0x8ac
++
++#define rFPGA0_XCD_RFPara 0x8b4
++#define rFPGA0_PSDReport 0x8b4 /* Useless now */
++#define TransceiverA_HSPI_Readback 0x8b8 /* Transceiver A HSPI Readback */
++#define TransceiverB_HSPI_Readback 0x8bc /* Transceiver B HSPI Readback */
++#define rFPGA0_XAB_RFInterfaceRB 0x8e0 /* Useless now */ /* RF Interface Readback Value */
++#define rFPGA0_XCD_RFInterfaceRB 0x8e4 /* Useless now */
++
++/*
++ * 4. Page9(0x900)
++ * */
++#define rFPGA1_RFMOD 0x900 /* RF mode & OFDM TxSC */ /* RF BW Setting?? */
++#define REG_BB_TX_PATH_SEL_1_8814A 0x93c
++#define REG_BB_TX_PATH_SEL_2_8814A 0x940
++#define rFPGA1_TxBlock 0x904 /* Useless now */
++#define rFPGA1_DebugSelect 0x908 /* Useless now */
++#define rFPGA1_TxInfo 0x90c /* Useless now */ /* Status report?? */
++/*Page 19 for TxBF*/
++#define REG_BB_TXBF_ANT_SET_BF1_8814A 0x19ac
++#define REG_BB_TXBF_ANT_SET_BF0_8814A 0x19b4
++/*
++ * PageA(0xA00)
++ * */
++#define rCCK0_System 0xa00
++#define rCCK0_AFESetting 0xa04 /* Disable init gain now */ /* Select RX path by RSSI */
++#define rCCK0_DSPParameter2 0xa1c /* SQ threshold */
++#define rCCK0_TxFilter1 0xa20
++#define rCCK0_TxFilter2 0xa24
++#define rCCK0_DebugPort 0xa28 /* debug port and Tx filter3 */
++#define rCCK0_FalseAlarmReport 0xa2c /* 0xa2d useless now 0xa30-a4f channel report */
++
++/*
++ * PageB(0xB00)
++ * */
++#define rPdp_AntA 0xb00
++#define rPdp_AntA_4 0xb04
++#define rConfig_Pmpd_AntA 0xb28
++#define rConfig_AntA 0xb68
++#define rConfig_AntB 0xb6c
++#define rPdp_AntB 0xb70
++#define rPdp_AntB_4 0xb74
++#define rConfig_Pmpd_AntB 0xb98
++#define rAPK 0xbd8
++
++/*
++ * 6. PageC(0xC00)
++ * */
++#define rOFDM0_LSTF 0xc00
++
++#define rOFDM0_TRxPathEnable 0xc04
++#define rOFDM0_TRMuxPar 0xc08
++#define rOFDM0_TRSWIsolation 0xc0c
++
++#define rOFDM0_XARxAFE 0xc10 /* RxIQ DC offset, Rx digital filter, DC notch filter */
++#define rOFDM0_XARxIQImbalance 0xc14 /* RxIQ imblance matrix */
++#define rOFDM0_XBRxAFE 0xc18
++#define rOFDM0_XBRxIQImbalance 0xc1c
++#define rOFDM0_XCRxAFE 0xc20
++#define rOFDM0_XCRxIQImbalance 0xc24
++#define rOFDM0_XDRxAFE 0xc28
++#define rOFDM0_XDRxIQImbalance 0xc2c
++
++#define rOFDM0_RxDetector1 0xc30 /* PD, BW & SBD */ /* DM tune init gain */
++#define rOFDM0_RxDetector2 0xc34 /* SBD & Fame Sync. */
++#define rOFDM0_RxDetector3 0xc38 /* Frame Sync. */
++#define rOFDM0_RxDetector4 0xc3c /* PD, SBD, Frame Sync & Short-GI */
++
++#define rOFDM0_RxDSP 0xc40 /* Rx Sync Path */
++#define rOFDM0_CFOandDAGC 0xc44 /* CFO & DAGC */
++#define rOFDM0_CCADropThreshold 0xc48 /* CCA Drop threshold */
++#define rOFDM0_ECCAThreshold 0xc4c /* energy CCA */
++
++#define rOFDM0_XAAGCCore1 0xc50 /* DIG */
++#define rOFDM0_XAAGCCore2 0xc54
++#define rOFDM0_XBAGCCore1 0xc58
++#define rOFDM0_XBAGCCore2 0xc5c
++#define rOFDM0_XCAGCCore1 0xc60
++#define rOFDM0_XCAGCCore2 0xc64
++#define rOFDM0_XDAGCCore1 0xc68
++#define rOFDM0_XDAGCCore2 0xc6c
++
++#define rOFDM0_AGCParameter1 0xc70
++#define rOFDM0_AGCParameter2 0xc74
++#define rOFDM0_AGCRSSITable 0xc78
++#define rOFDM0_HTSTFAGC 0xc7c
++
++#define rOFDM0_XATxIQImbalance 0xc80 /* TX PWR TRACK and DIG */
++#define rOFDM0_XATxAFE 0xc84
++#define rOFDM0_XBTxIQImbalance 0xc88
++#define rOFDM0_XBTxAFE 0xc8c
++#define rOFDM0_XCTxIQImbalance 0xc90
++#define rOFDM0_XCTxAFE 0xc94
++#define rOFDM0_XDTxIQImbalance 0xc98
++#define rOFDM0_XDTxAFE 0xc9c
++
++#define rOFDM0_RxIQExtAnta 0xca0
++#define rOFDM0_TxCoeff1 0xca4
++#define rOFDM0_TxCoeff2 0xca8
++#define rOFDM0_TxCoeff3 0xcac
++#define rOFDM0_TxCoeff4 0xcb0
++#define rOFDM0_TxCoeff5 0xcb4
++#define rOFDM0_TxCoeff6 0xcb8
++#define rOFDM0_RxHPParameter 0xce0
++#define rOFDM0_TxPseudoNoiseWgt 0xce4
++#define rOFDM0_FrameSync 0xcf0
++#define rOFDM0_DFSReport 0xcf4
++
++/*
++ * 7. PageD(0xD00)
++ * */
++#define rOFDM1_LSTF 0xd00
++#define rOFDM1_TRxPathEnable 0xd04
++
++/*
++ * 8. PageE(0xE00)
++ * */
++#define rTxAGC_A_Rate18_06 0xe00
++#define rTxAGC_A_Rate54_24 0xe04
++#define rTxAGC_A_CCK1_Mcs32 0xe08
++#define rTxAGC_A_Mcs03_Mcs00 0xe10
++#define rTxAGC_A_Mcs07_Mcs04 0xe14
++#define rTxAGC_A_Mcs11_Mcs08 0xe18
++#define rTxAGC_A_Mcs15_Mcs12 0xe1c
++
++#define rTxAGC_B_Rate18_06 0x830
++#define rTxAGC_B_Rate54_24 0x834
++#define rTxAGC_B_CCK1_55_Mcs32 0x838
++#define rTxAGC_B_Mcs03_Mcs00 0x83c
++#define rTxAGC_B_Mcs07_Mcs04 0x848
++#define rTxAGC_B_Mcs11_Mcs08 0x84c
++#define rTxAGC_B_Mcs15_Mcs12 0x868
++#define rTxAGC_B_CCK11_A_CCK2_11 0x86c
++
++#define rFPGA0_IQK 0xe28
++#define rTx_IQK_Tone_A 0xe30
++#define rRx_IQK_Tone_A 0xe34
++#define rTx_IQK_PI_A 0xe38
++#define rRx_IQK_PI_A 0xe3c
++
++#define rTx_IQK 0xe40
++#define rRx_IQK 0xe44
++#define rIQK_AGC_Pts 0xe48
++#define rIQK_AGC_Rsp 0xe4c
++#define rTx_IQK_Tone_B 0xe50
++#define rRx_IQK_Tone_B 0xe54
++#define rTx_IQK_PI_B 0xe58
++#define rRx_IQK_PI_B 0xe5c
++#define rIQK_AGC_Cont 0xe60
++
++#define rBlue_Tooth 0xe6c
++#define rRx_Wait_CCA 0xe70
++#define rTx_CCK_RFON 0xe74
++#define rTx_CCK_BBON 0xe78
++#define rTx_OFDM_RFON 0xe7c
++#define rTx_OFDM_BBON 0xe80
++#define rTx_To_Rx 0xe84
++#define rTx_To_Tx 0xe88
++#define rRx_CCK 0xe8c
++
++#define rTx_Power_Before_IQK_A 0xe94
++#define rTx_Power_After_IQK_A 0xe9c
++
++#define rRx_Power_Before_IQK_A 0xea0
++#define rRx_Power_Before_IQK_A_2 0xea4
++#define rRx_Power_After_IQK_A 0xea8
++#define rRx_Power_After_IQK_A_2 0xeac
++
++#define rTx_Power_Before_IQK_B 0xeb4
++#define rTx_Power_After_IQK_B 0xebc
++
++#define rRx_Power_Before_IQK_B 0xec0
++#define rRx_Power_Before_IQK_B_2 0xec4
++#define rRx_Power_After_IQK_B 0xec8
++#define rRx_Power_After_IQK_B_2 0xecc
++
++#define rRx_OFDM 0xed0
++#define rRx_Wait_RIFS 0xed4
++#define rRx_TO_Rx 0xed8
++#define rStandby 0xedc
++#define rSleep 0xee0
++#define rPMPD_ANAEN 0xeec
++
++
++/* 2. Page8(0x800) */
++#define bRFMOD 0x1 /* Reg 0x800 rFPGA0_RFMOD */
++#define bJapanMode 0x2
++#define bCCKTxSC 0x30
++#define bCCKEn 0x1000000
++#define bOFDMEn 0x2000000
++#define bXBTxAGC 0xf00 /* Reg 80c rFPGA0_TxGainStage */
++#define bXCTxAGC 0xf000
++#define bXDTxAGC 0xf0000
++
++/* 4. PageA(0xA00) */
++#define bCCKBBMode 0x3 /* Useless */
++#define bCCKTxPowerSaving 0x80
++#define bCCKRxPowerSaving 0x40
++
++#define bCCKSideBand 0x10 /* Reg 0xa00 rCCK0_System 20/40 switch */
++
++#define bCCKScramble 0x8 /* Useless */
++#define bCCKAntDiversity 0x8000
++#define bCCKCarrierRecovery 0x4000
++#define bCCKTxRate 0x3000
++#define bCCKDCCancel 0x0800
++#define bCCKISICancel 0x0400
++#define bCCKMatchFilter 0x0200
++#define bCCKEqualizer 0x0100
++#define bCCKPreambleDetect 0x800000
++#define bCCKFastFalseCCA 0x400000
++#define bCCKChEstStart 0x300000
++#define bCCKCCACount 0x080000
++#define bCCKcs_lim 0x070000
++#define bCCKBistMode 0x80000000
++#define bCCKCCAMask 0x40000000
++#define bCCKTxDACPhase 0x4
++#define bCCKRxADCPhase 0x20000000 /* r_rx_clk */
++#define bCCKr_cp_mode0 0x0100
++#define bCCKTxDCOffset 0xf0
++#define bCCKRxDCOffset 0xf
++#define bCCKCCAMode 0xc000
++#define bCCKFalseCS_lim 0x3f00
++#define bCCKCS_ratio 0xc00000
++#define bCCKCorgBit_sel 0x300000
++#define bCCKPD_lim 0x0f0000
++#define bCCKNewCCA 0x80000000
++#define bCCKRxHPofIG 0x8000
++#define bCCKRxIG 0x7f00
++#define bCCKLNAPolarity 0x800000
++#define bCCKRx1stGain 0x7f0000
++#define bCCKRFExtend 0x20000000 /* CCK Rx Iinital gain polarity */
++#define bCCKRxAGCSatLevel 0x1f000000
++#define bCCKRxAGCSatCount 0xe0
++#define bCCKRxRFSettle 0x1f /* AGCsamp_dly */
++#define bCCKFixedRxAGC 0x8000
++/* #define bCCKRxAGCFormat 0x4000 */ /* remove to HSSI register 0x824 */
++#define bCCKAntennaPolarity 0x2000
++#define bCCKTxFilterType 0x0c00
++#define bCCKRxAGCReportType 0x0300
++#define bCCKRxDAGCEn 0x80000000
++#define bCCKRxDAGCPeriod 0x20000000
++#define bCCKRxDAGCSatLevel 0x1f000000
++#define bCCKTimingRecovery 0x800000
++#define bCCKTxC0 0x3f0000
++#define bCCKTxC1 0x3f000000
++#define bCCKTxC2 0x3f
++#define bCCKTxC3 0x3f00
++#define bCCKTxC4 0x3f0000
++#define bCCKTxC5 0x3f000000
++#define bCCKTxC6 0x3f
++#define bCCKTxC7 0x3f00
++#define bCCKDebugPort 0xff0000
++#define bCCKDACDebug 0x0f000000
++#define bCCKFalseAlarmEnable 0x8000
++#define bCCKFalseAlarmRead 0x4000
++#define bCCKTRSSI 0x7f
++#define bCCKRxAGCReport 0xfe
++#define bCCKRxReport_AntSel 0x80000000
++#define bCCKRxReport_MFOff 0x40000000
++#define bCCKRxRxReport_SQLoss 0x20000000
++#define bCCKRxReport_Pktloss 0x10000000
++#define bCCKRxReport_Lockedbit 0x08000000
++#define bCCKRxReport_RateError 0x04000000
++#define bCCKRxReport_RxRate 0x03000000
++#define bCCKRxFACounterLower 0xff
++#define bCCKRxFACounterUpper 0xff000000
++#define bCCKRxHPAGCStart 0xe000
++#define bCCKRxHPAGCFinal 0x1c00
++#define bCCKRxFalseAlarmEnable 0x8000
++#define bCCKFACounterFreeze 0x4000
++#define bCCKTxPathSel 0x10000000
++#define bCCKDefaultRxPath 0xc000000
++#define bCCKOptionRxPath 0x3000000
++
++#define RF_T_METER_88E 0x42
++
++/* 6. PageE(0xE00) */
++#define bSTBCEn 0x4 /* Useless */
++#define bAntennaMapping 0x10
++#define bNss 0x20
++#define bCFOAntSumD 0x200
++#define bPHYCounterReset 0x8000000
++#define bCFOReportGet 0x4000000
++#define bOFDMContinueTx 0x10000000
++#define bOFDMSingleCarrier 0x20000000
++#define bOFDMSingleTone 0x40000000
++
++
++/*
++ * Other Definition
++ * */
++
++#define bEnable 0x1 /* Useless */
++#define bDisable 0x0
++
++/* byte endable for srwrite */
++#define bByte0 0x1 /* Useless */
++#define bByte1 0x2
++#define bByte2 0x4
++#define bByte3 0x8
++#define bWord0 0x3
++#define bWord1 0xc
++#define bDWord 0xf
++
++/* for PutRegsetting & GetRegSetting BitMask */
++#define bMaskByte0 0xff /* Reg 0xc50 rOFDM0_XAAGCCore~0xC6f */
++#define bMaskByte1 0xff00
++#define bMaskByte2 0xff0000
++#define bMaskByte3 0xff000000
++#define bMaskHWord 0xffff0000
++#define bMaskLWord 0x0000ffff
++#define bMaskDWord 0xffffffff
++#define bMaskH3Bytes 0xffffff00
++#define bMask12Bits 0xfff
++#define bMaskH4Bits 0xf0000000
++#define bMaskOFDM_D 0xffc00000
++#define bMaskCCK 0x3f3f3f3f
++#define bMask7bits 0x7f
++#define bMaskByte2HighNibble 0x00f00000
++#define bMaskByte3LowNibble 0x0f000000
++#define bMaskL3Bytes 0x00ffffff
++
++/*--------------------------Define Parameters-------------------------------*/
++
++
++#endif
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/include/Hal8814PwrSeq.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/include/Hal8814PwrSeq.h
+--- linux-5.11.4/3rdparty/rtl8812au/include/Hal8814PwrSeq.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/include/Hal8814PwrSeq.h 2021-03-07 18:16:17.084957471 +0200
+@@ -0,0 +1,231 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++
++
++#ifndef __HAL8814PWRSEQ_H__
++#define __HAL8814PWRSEQ_H__
++
++#include "HalPwrSeqCmd.h"
++
++/*
++ Check document WB-110628-DZ-RTL8195 (Jaguar) Power Architecture-R04.pdf
++ There are 6 HW Power States:
++ 0: POFF--Power Off
++ 1: PDN--Power Down
++ 2: CARDEMU--Card Emulation
++ 3: ACT--Active Mode
++ 4: LPS--Low Power State
++ 5: SUS--Suspend
++
++ The transision from different states are defined below
++ TRANS_CARDEMU_TO_ACT
++ TRANS_ACT_TO_CARDEMU
++ TRANS_CARDEMU_TO_SUS
++ TRANS_SUS_TO_CARDEMU
++ TRANS_CARDEMU_TO_PDN
++ TRANS_ACT_TO_LPS
++ TRANS_LPS_TO_ACT
++
++ TRANS_END
++*/
++#define RTL8814A_TRANS_CARDEMU_TO_ACT_STEPS 16
++#define RTL8814A_TRANS_ACT_TO_CARDEMU_STEPS 20
++#define RTL8814A_TRANS_CARDEMU_TO_SUS_STEPS 17
++#define RTL8814A_TRANS_SUS_TO_CARDEMU_STEPS 15
++#define RTL8814A_TRANS_CARDEMU_TO_PDN_STEPS 17
++#define RTL8814A_TRANS_PDN_TO_CARDEMU_STEPS 16
++#define RTL8814A_TRANS_ACT_TO_LPS_STEPS 20
++#define RTL8814A_TRANS_LPS_TO_ACT_STEPS 15
++#define RTL8814A_TRANS_END_STEPS 1
++
++
++#define RTL8814A_TRANS_CARDEMU_TO_ACT \
++ /* format */ \
++ /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
++ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0},/* disable SW LPS 0x04[10]=0*/ \
++ {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, BIT1},/* wait till 0x04[17] = 1 power ready*/ \
++ {0x002B, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0}, /* ??0x28[24]=1, enable pll phase select*/ \
++ {0x0015, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT3 | BIT2 | BIT1), (BIT3 | BIT2 | BIT1)},/* 0x14[11:9]=3'b111, OCP current threshold = 1.5A */ \
++ {0x002D, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x0E, 0x08},/* 0x2C[11:9]=3'b100, select lpf R3 */ \
++ {0x002D, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x70, 0x50},/* 0x2C[14:12]=3'b101, select lpf Rs*/ \
++ {0x007B, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6, BIT6},/* 0x78[30]=1'b1, SDM order select*/ \
++ /*{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0}, */ /* disable HWPDN 0x04[15]=0*/ \
++ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, 0},/* disable WL suspend*/ \
++ {0x00F0, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/* */ \
++ {0x0081, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x30, 0x20},/* */ \
++ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* polling until return 0*/ \
++ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT0, 0},/**/
++
++#define RTL8814A_TRANS_ACT_TO_CARDEMU \
++ /* format */ \
++ /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
++ {0x0c00, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x04}, /* 0xc00[7:0] = 4 turn off 3-wire */ \
++ {0x0e00, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x04}, /* 0xe00[7:0] = 4 turn off 3-wire */ \
++ {0x0002, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0}, /* 0x2[0] = 0 RESET BB, CLOSE RF */ \
++ {0x0002, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US}, /*Delay 1us*/ \
++ {0x0002, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0}, /* Whole BB is reset*/ \
++ {0x1002, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0}, /* 0x2[0] = 0 RESET BB, CLOSE RF */ \
++ {0x0002, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US}, /*Delay 1us*/ \
++ {0x1002, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0}, /* Whole BB is reset*/ \
++ {0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, /*0x1F[7:0] = 0 turn off RF*/ \
++ /*{0x004E, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},*/ /*0x4C[23] = 0x4E[7] = 0, switch DPDT_SEL_P output from register 0x65[2] */ \
++ {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x28}, /* 0x07[7:0] = 0x28 sps pwm mode 0x2a for BT coex*/ \
++ {0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x02, 0}, /*0x8[1] = 0 ANA clk = 500k */ \
++ /*{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0 | BIT1, 0},*/ /* 0x02[1:0] = 0 reset BB */ \
++ {0x0066, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0}, /*0x66[7]=0, disable ckreq for gpio7 output SUS */ \
++ {0x0041, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*0x41[4]=0, disable sic for gpio7 output SUS */ \
++ {0x0042, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0}, /*0x42[1]=0, disable ckout for gpio7 output SUS */ \
++ {0x004e, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5}, /*0x4E[5]=1, disable LED2 for gpio7 output SUS */ \
++ {0x0041, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0}, /*0x41[0]=0, disable uart for gpio7 output SUS */ \
++ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*0x04[9] = 1 turn off MAC by HW state machine*/ \
++ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, 0}, /*wait till 0x04[9] = 0 polling until return 0 to disable*/
++
++#define RTL8814A_TRANS_CARDEMU_TO_SUS \
++ /* format */ \
++ /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
++ {0x0061, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x0F, 0x0c},\
++ {0x0061, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x0F, 0x0E},\
++ {0x0062, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x0F, 0x07},/* gpio11 input mode, gpio10~8 output mode */ \
++ {0x0045, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/* gpio 0~7 output same value as input ?? */ \
++ {0x0046, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xff},/* gpio0~7 output mode */ \
++ {0x0047, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/* 0x47[7:0] = 00 gpio mode */ \
++ {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/* suspend option all off */ \
++ {0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5},/*0x14[13] = 1 turn on ZCD */ \
++ {0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6, BIT6},/* 0x14[14] =1 trun on ZCD */ \
++ {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4},/*0x23[4] = 1 hpon LDO sleep mode */ \
++ {0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*0x8[1] = 0 ANA clk = 500k */ \
++ {0x0091, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xA0, 0xA0}, /* 0x91[7]=1 0x91[5]=1 , disable sps, ldo sleep mode */ \
++ {0x0070, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, BIT3}, /* 0x70[3]=1 enable mainbias polling */ \
++ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, BIT3}, /*0x04[11] = 1 enable WL suspend */
++
++#define RTL8814A_TRANS_SUS_TO_CARDEMU \
++ /* format */ \
++ /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
++ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, 0}, /*0x04[11] = 0 enable WL suspend*/ \
++ {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x10, 0},/*0x23[4] = 0 hpon LDO sleep mode leave */ \
++ {0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6, 0},/* 0x14[14] =0 trun off ZCD */ \
++ {0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, 0},/*0x14[13] = 0 turn off ZCD */ \
++ {0x0046, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/* gpio0~7 input mode */ \
++ {0x0062, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/* gpio11 input mode, gpio10~8 input mode */
++
++#define RTL8814A_TRANS_CARDEMU_TO_CARDDIS \
++ /* format */ \
++ /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
++ /**{0x0194, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0}, //0x194[0]=0 , disable 32K clock*/ \
++ /**{0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x94}, //0x93 = 0x94 , 90[30] =0 enable 500k ANA clock .switch clock from 12M to 500K , 90 [26] =0 disable EEprom loader clock*/ \
++ {0x0003, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0}, /*0x03[2] = 0, reset 3081*/ \
++ {0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x01}, /*0x80 = 05h if reload fw, fill the default value of host_CPU handshake field*/ \
++ {0x0081, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x30}, /*0x80 = 05h if reload fw, fill the default value of host_CPU handshake field*/ \
++ /*{0x0042, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xF0, 0xcc},*/ \
++ /*{0x0042, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xF0, 0xEC},*/ \
++ /*{0x0043, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x07},*/ /* gpio11 input mode, gpio10~8 output mode */ \
++ {0x0045, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/* gpio 0~7 output same value as input ?? */ \
++ {0x0046, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xff},/* gpio0~7 output mode */ \
++ {0x0047, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/* 0x47[7:0] = 00 gpio mode */ \
++ {0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6, BIT6},/* 0x15[6] =1 trun on ZCD output */ \
++ {0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5},/*0x15[5] = 1 turn on ZCD */ \
++ {0x0012, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6, 0},/*0x12[6] = 0 force PFM mode */ \
++ {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4},/*0x23[4] = 1 hpon LDO sleep mode */ \
++ {0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*0x8[1] = 0 ANA clk = 500k */ \
++ {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07 = 0x20 , SOP option to disable BG/MB*/ \
++ {0x001f, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0}, /* 0x01f[1]=0 , disable RFC_0 control REG_RF_CTRL_8814A */ \
++ {0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0}, /* 0x020[1]=0 , disable RFC_1 control REG_RF_CTRL_8814A */ \
++ {0x0021, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0}, /* 0x021[1]=0 , disable RFC_2 control REG_RF_CTRL_8814A */ \
++ {0x0076, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0}, /* 0x076[1]=0 , disable RFC_3 control REG_OPT_CTRL_8814A +2 */ \
++ {0x0091, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xA0, 0xA0}, /* 0x91[7]=1 0x91[5]=1 , disable sps, ldo sleep mode */ \
++ {0x0070, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, BIT3}, /* 0x70[3]=1 enable mainbias polling */ \
++ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, BIT3}, /*0x04[11] = 1 enable WL suspend*/
++
++#define RTL8814A_TRANS_CARDDIS_TO_CARDEMU \
++ /* format */ \
++ /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
++ {0x0012, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6, BIT6},/*0x12[6] = 1 force PWM mode */ \
++ {0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, 0},/*0x15[5] = 0 turn off ZCD */ \
++ {0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6, 0},/* 0x15[6] =0 trun off ZCD output */ \
++ {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0},/*0x23[4] = 0 hpon LDO leave sleep mode */ \
++ {0x0046, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/* gpio0~7 input mode */ \
++ {0x0062, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00}, /* gpio11 input mode, gpio10~8 input mode */ \
++ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0}, /*0x04[10] = 0, enable SW LPS PCIE only*/ \
++ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, 0}, /*0x04[11] = 0, enable WL suspend*/ \
++ /*{0x0003, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, BIT2},*/ /*0x03[2] = 1, enable 3081*/ \
++ {0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/*PCIe DMA start*/ \
++ {0x0071, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0},/*0x70[10] = 0, CPHY_MBIAS_EN disable*/
++
++
++#define RTL8814A_TRANS_CARDEMU_TO_PDN \
++ /* format */ \
++ /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
++ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7},/* 0x04[15] = 1*/
++
++#define RTL8814A_TRANS_PDN_TO_CARDEMU \
++ /* format */ \
++ /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
++ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/* 0x04[15] = 0*/
++
++#define RTL8814A_TRANS_ACT_TO_LPS \
++ /* format */ \
++ /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
++ {0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF},/*PCIe DMA stop*/ \
++ {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x7F},/*Tx Pause*/ \
++ {0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
++ {0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
++ {0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
++ {0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
++ {0x0c00, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x04}, /* 0xc00[7:0] = 4 turn off 3-wire */ \
++ {0x0e00, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x04}, /* 0xe00[7:0] = 4 turn off 3-wire */ \
++ {0x0002, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled, and clock are gated, and RF closed*/ \
++ {0x0002, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/ \
++ {0x0002, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0}, /* Whole BB is reset*/ \
++ {0x1002, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled, and clock are gated, and RF closed*/ \
++ {0x0002, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/ \
++ {0x1002, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0}, /* Whole BB is reset*/ \
++ {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x03},/*Reset MAC TRX*/ \
++ {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*check if removed later*/ \
++ {0x05F1, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/*Respond TxOK to scheduler*/
++
++
++#define RTL8814A_TRANS_LPS_TO_ACT \
++ /* format */ \
++ /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
++ {0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM*/ \
++ {0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/ \
++ {0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/ \
++ {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /* Delay*/ \
++ {0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*. 0x08[4] = 0 switch TSF to 40M*/ \
++ {0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT7, 0}, /* Polling 0x109[7]=0 TSF in 40M*/ \
++ /*{0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6 | BIT7, 0}, */ /*. ??0x29[7:6] = 2b'00 enable BB clock*/ \
++ {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*. 0x101[1] = 1*/ \
++ {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF}, /*. 0x100[7:0] = 0xFF enable WMAC TRX*/ \
++ {0x0002, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1 | BIT0, BIT1 | BIT0}, /*. 0x02[1:0] = 2b'11 enable BB macro*/ \
++ {0x1002, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1 | BIT0, BIT1 | BIT0}, /*. 0x1002[1:0] = 2b'11 enable BB macro*/ \
++ {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, /*. 0x522 = 0*/
++
++#define RTL8814A_TRANS_END \
++ /* format */ \
++ /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
++ {0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, 0, PWR_CMD_END, 0, 0},
++
++
++extern WLAN_PWR_CFG rtl8814A_power_on_flow[RTL8814A_TRANS_CARDEMU_TO_ACT_STEPS + RTL8814A_TRANS_END_STEPS];
++extern WLAN_PWR_CFG rtl8814A_radio_off_flow[RTL8814A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8814A_TRANS_END_STEPS];
++extern WLAN_PWR_CFG rtl8814A_card_disable_flow[RTL8814A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8814A_TRANS_CARDEMU_TO_PDN_STEPS + RTL8814A_TRANS_END_STEPS];
++extern WLAN_PWR_CFG rtl8814A_card_enable_flow[RTL8814A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8814A_TRANS_CARDEMU_TO_PDN_STEPS + RTL8814A_TRANS_END_STEPS];
++extern WLAN_PWR_CFG rtl8814A_suspend_flow[RTL8814A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8814A_TRANS_CARDEMU_TO_SUS_STEPS + RTL8814A_TRANS_END_STEPS];
++extern WLAN_PWR_CFG rtl8814A_resume_flow[RTL8814A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8814A_TRANS_CARDEMU_TO_SUS_STEPS + RTL8814A_TRANS_END_STEPS];
++extern WLAN_PWR_CFG rtl8814A_hwpdn_flow[RTL8814A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8814A_TRANS_CARDEMU_TO_PDN_STEPS + RTL8814A_TRANS_END_STEPS];
++extern WLAN_PWR_CFG rtl8814A_enter_lps_flow[RTL8814A_TRANS_ACT_TO_LPS_STEPS + RTL8814A_TRANS_END_STEPS];
++extern WLAN_PWR_CFG rtl8814A_leave_lps_flow[RTL8814A_TRANS_LPS_TO_ACT_STEPS + RTL8814A_TRANS_END_STEPS];
++
++#endif /* __HAL8814PWRSEQ_H__ */
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/include/Hal8821APwrSeq.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/include/Hal8821APwrSeq.h
+--- linux-5.11.4/3rdparty/rtl8812au/include/Hal8821APwrSeq.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/include/Hal8821APwrSeq.h 2021-03-07 18:16:17.084957471 +0200
+@@ -0,0 +1,200 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2016 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef REALTEK_POWER_SEQUENCE_8821
++#define REALTEK_POWER_SEQUENCE_8821
++
++#include "HalPwrSeqCmd.h"
++
++/*
++ Check document WM-20130516-JackieLau-RTL8821A_Power_Architecture-R10.vsd
++ There are 6 HW Power States:
++ 0: POFF--Power Off
++ 1: PDN--Power Down
++ 2: CARDEMU--Card Emulation
++ 3: ACT--Active Mode
++ 4: LPS--Low Power State
++ 5: SUS--Suspend
++
++ The transision from different states are defined below
++ TRANS_CARDEMU_TO_ACT
++ TRANS_ACT_TO_CARDEMU
++ TRANS_CARDEMU_TO_SUS
++ TRANS_SUS_TO_CARDEMU
++ TRANS_CARDEMU_TO_PDN
++ TRANS_ACT_TO_LPS
++ TRANS_LPS_TO_ACT
++
++ TRANS_END
++*/
++#define RTL8821A_TRANS_CARDEMU_TO_ACT_STEPS 25
++#define RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS 15
++#define RTL8821A_TRANS_CARDEMU_TO_SUS_STEPS 15
++#define RTL8821A_TRANS_SUS_TO_CARDEMU_STEPS 15
++#define RTL8821A_TRANS_CARDDIS_TO_CARDEMU_STEPS 15
++#define RTL8821A_TRANS_CARDEMU_TO_PDN_STEPS 15
++#define RTL8821A_TRANS_PDN_TO_CARDEMU_STEPS 15
++#define RTL8821A_TRANS_ACT_TO_LPS_STEPS 15
++#define RTL8821A_TRANS_LPS_TO_ACT_STEPS 15
++#define RTL8821A_TRANS_END_STEPS 1
++
++
++#define RTL8821A_TRANS_CARDEMU_TO_ACT \
++ /* format */ \
++ /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
++ {0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0}, /*0x20[0] = 1b'1 enable LDOA12 MACRO block for all interface*/ \
++ {0x0067, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*0x67[0] = 0 to disable BT_GPS_SEL pins*/ \
++ {0x0001, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 1, PWRSEQ_DELAY_MS},/*Delay 1ms*/ \
++ {0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, 0}, /*0x00[5] = 1b'0 release analog Ips to digital ,1:isolation*/ \
++ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT4 | BIT3 | BIT2), 0},/* disable SW LPS 0x04[10]=0 and WLSUS_EN 0x04[12:11]=0*/ \
++ {0x0075, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0 , BIT0},/* Disable USB suspend */ \
++ {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, BIT1},/* wait till 0x04[17] = 1 power ready*/ \
++ {0x0075, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0 , 0},/* Enable USB suspend */ \
++ {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* release WLON reset 0x04[16]=1*/ \
++ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/* disable HWPDN 0x04[15]=0*/ \
++ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT4 | BIT3), 0},/* disable WL suspend*/ \
++ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* polling until return 0*/ \
++ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT0, 0},/**/ \
++ {0x004F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/*0x4C[24] = 0x4F[0] = 1, switch DPDT_SEL_P output from WL BB */\
++ {0x0067, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT5 | BIT4), (BIT5 | BIT4)},/*0x66[13] = 0x67[5] = 1, switch for PAPE_G/PAPE_A from WL BB ; 0x66[12] = 0x67[4] = 1, switch LNAON from WL BB */\
++ {0x0025, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6, 0},/*anapar_mac<118> , 0x25[6]=0 by wlan single function*/\
++ {0x0049, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1},/*Enable falling edge triggering interrupt*/\
++ {0x0063, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1},/*Enable GPIO9 interrupt mode*/\
++ {0x0062, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*Enable GPIO9 input mode*/\
++ {0x0058, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/*Enable HSISR GPIO[C:0] interrupt*/\
++ {0x005A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1},/*Enable HSISR GPIO9 interrupt*/\
++ {0x007A, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x3A},/*0x7A = 0x3A start BT*/\
++ {0x002E, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF , 0x82 },/* 0x2C[23:12]=0x820 ; XTAL trim */ \
++ {0x0010, PWR_CUT_A_MSK , PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6 , BIT6 },/* 0x10[6]=1 ; MP·s¼W¹ï©ó0x2Cªº±±¨îÅv¡A¶·§â0x10[6]³]¬°1¤~¯àÅýWLAN±±¨î */ \
++
++
++#define RTL8821A_TRANS_ACT_TO_CARDEMU \
++ /* format */ \
++ /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
++ {0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/*0x1F[7:0] = 0 turn off RF*/ \
++ {0x004F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*0x4C[24] = 0x4F[0] = 0, switch DPDT_SEL_P output from register 0x65[2] */\
++ {0x0049, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*Enable rising edge triggering interrupt*/ \
++ {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* release WLON reset 0x04[16]=1*/ \
++ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*0x04[9] = 1 turn off MAC by HW state machine*/ \
++ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, 0}, /*wait till 0x04[9] = 0 polling until return 0 to disable*/ \
++ {0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5}, /*0x00[5] = 1b'1 analog Ips to digital ,1:isolation*/ \
++ {0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0}, /*0x20[0] = 1b'0 disable LDOA12 MACRO block*/ \
++
++
++#define RTL8821A_TRANS_CARDEMU_TO_SUS \
++ /* format */ \
++ /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
++ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4 | BIT3, (BIT4 | BIT3)}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \
++ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/ \
++ {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/ \
++ {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SDIO SOP option to disable BG/MB/ACK/SWR*/ \
++ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, BIT3 | BIT4}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \
++ {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/ \
++ {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/
++
++#define RTL8821A_TRANS_SUS_TO_CARDEMU \
++ /* format */ \
++ /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
++ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT7, 0}, /*clear suspend enable and power down enable*/ \
++ {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/ \
++ {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\
++ {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*0x23[4] = 1b'0 12H LDO enter normal mode*/ \
++ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/
++
++#define RTL8821A_TRANS_CARDEMU_TO_CARDDIS \
++ /* format */ \
++ /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
++ {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07 = 0x20 , SOP option to disable BG/MB*/ \
++ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/ \
++ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, BIT2}, /*0x04[10] = 1, enable SW LPS*/ \
++ {0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 1}, /*0x48[16] = 1 to enable GPIO9 as EXT WAKEUP*/ \
++ {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/ \
++ {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/ \
++ {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/
++
++#define RTL8821A_TRANS_CARDDIS_TO_CARDEMU \
++ /* format */ \
++ /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
++ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT7, 0}, /*clear suspend enable and power down enable*/ \
++ {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/ \
++ {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\
++ {0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0}, /*0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/ \
++ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/\
++ {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*0x23[4] = 1b'0 12H LDO enter normal mode*/ \
++ {0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/*PCIe DMA start*/
++
++
++#define RTL8821A_TRANS_CARDEMU_TO_PDN \
++ /* format */ \
++ /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
++ {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/ \
++ {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK | PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SOP option to disable BG/MB/ACK/SWR*/ \
++ {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/* 0x04[16] = 0*/\
++ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7},/* 0x04[15] = 1*/
++
++#define RTL8821A_TRANS_PDN_TO_CARDEMU \
++ /* format */ \
++ /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
++ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/* 0x04[15] = 0*/
++
++#define RTL8821A_TRANS_ACT_TO_LPS \
++ /* format */ \
++ /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
++ {0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF},/*PCIe DMA stop*/ \
++ {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF},/*Tx Pause*/ \
++ {0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
++ {0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
++ {0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
++ {0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
++ {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled, and clock are gated*/ \
++ {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/ \
++ {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*Whole BB is reset*/ \
++ {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x03},/*Reset MAC TRX*/ \
++ {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*check if removed later*/ \
++ {0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/*When driver enter Sus/ Disable, enable LOP for BT*/ \
++ {0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5},/*Respond TxOK to scheduler*/ \
++
++
++#define RTL8821A_TRANS_LPS_TO_ACT \
++ /* format */ \
++ /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
++ {0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM*/\
++ {0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/\
++ {0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/\
++ {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /*Delay*/\
++ {0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*. 0x08[4] = 0 switch TSF to 40M*/\
++ {0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT7, 0}, /*Polling 0x109[7]=0 TSF in 40M*/\
++ {0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6 | BIT7, 0}, /*. 0x29[7:6] = 2b'00 enable BB clock*/\
++ {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*. 0x101[1] = 1*/\
++ {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF}, /*. 0x100[7:0] = 0xFF enable WMAC TRX*/\
++ {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1 | BIT0, BIT1 | BIT0}, /*. 0x02[1:0] = 2b'11 enable BB macro*/\
++ {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, /*. 0x522 = 0*/
++
++#define RTL8821A_TRANS_END \
++ /* format */ \
++ /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
++ {0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, 0, PWR_CMD_END, 0, 0},
++
++
++ extern WLAN_PWR_CFG rtl8821A_power_on_flow[RTL8821A_TRANS_CARDEMU_TO_ACT_STEPS + RTL8821A_TRANS_END_STEPS];
++ extern WLAN_PWR_CFG rtl8821A_radio_off_flow[RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8821A_TRANS_END_STEPS];
++ extern WLAN_PWR_CFG rtl8821A_card_disable_flow[RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8821A_TRANS_CARDEMU_TO_PDN_STEPS + RTL8821A_TRANS_END_STEPS];
++ extern WLAN_PWR_CFG rtl8821A_card_enable_flow[RTL8821A_TRANS_CARDDIS_TO_CARDEMU_STEPS + RTL8821A_TRANS_CARDEMU_TO_ACT_STEPS + RTL8821A_TRANS_END_STEPS];
++ extern WLAN_PWR_CFG rtl8821A_suspend_flow[RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8821A_TRANS_CARDEMU_TO_SUS_STEPS + RTL8821A_TRANS_END_STEPS];
++ extern WLAN_PWR_CFG rtl8821A_resume_flow[RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8821A_TRANS_CARDEMU_TO_SUS_STEPS + RTL8821A_TRANS_END_STEPS];
++ extern WLAN_PWR_CFG rtl8821A_hwpdn_flow[RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8821A_TRANS_CARDEMU_TO_PDN_STEPS + RTL8821A_TRANS_END_STEPS];
++ extern WLAN_PWR_CFG rtl8821A_enter_lps_flow[RTL8821A_TRANS_ACT_TO_LPS_STEPS + RTL8821A_TRANS_END_STEPS];
++ extern WLAN_PWR_CFG rtl8821A_leave_lps_flow[RTL8821A_TRANS_LPS_TO_ACT_STEPS + RTL8821A_TRANS_END_STEPS];
++
++#endif
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/include/hal_btcoex.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/include/hal_btcoex.h
+--- linux-5.11.4/3rdparty/rtl8812au/include/hal_btcoex.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/include/hal_btcoex.h 2021-03-07 18:16:17.085957519 +0200
@@ -0,0 +1,97 @@
+/******************************************************************************
+ *
@@ -377414,11 +373637,9 @@ index 000000000..03021fee3
+u8 hal_btcoex_get_rf4ce_link_state(void);
+#endif
+#endif /* !__HAL_BTCOEX_H__ */
-diff --git linux-5.8/3rdparty/rtl8812au/include/hal_btcoex_wifionly.h linux-5.8/3rdparty/rtl8812au/include/hal_btcoex_wifionly.h
-new file mode 100644
-index 000000000..c18d20e7c
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/include/hal_btcoex_wifionly.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/include/hal_btcoex_wifionly.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/include/hal_btcoex_wifionly.h
+--- linux-5.11.4/3rdparty/rtl8812au/include/hal_btcoex_wifionly.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/include/hal_btcoex_wifionly.h 2021-03-07 18:16:17.085957519 +0200
@@ -0,0 +1,81 @@
+/******************************************************************************
+ *
@@ -377501,11 +373722,9 @@ index 000000000..c18d20e7c
+#endif
+
+#endif
-diff --git linux-5.8/3rdparty/rtl8812au/include/hal_com.h linux-5.8/3rdparty/rtl8812au/include/hal_com.h
-new file mode 100644
-index 000000000..a9fb90cc5
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/include/hal_com.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/include/hal_com.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/include/hal_com.h
+--- linux-5.11.4/3rdparty/rtl8812au/include/hal_com.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/include/hal_com.h 2021-03-07 18:16:17.085957519 +0200
@@ -0,0 +1,719 @@
+/******************************************************************************
+ *
@@ -378226,11 +374445,9 @@ index 000000000..a9fb90cc5
+#endif
+
+#endif /* __HAL_COMMON_H__ */
-diff --git linux-5.8/3rdparty/rtl8812au/include/hal_com_h2c.h linux-5.8/3rdparty/rtl8812au/include/hal_com_h2c.h
-new file mode 100644
-index 000000000..13158bcb6
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/include/hal_com_h2c.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/include/hal_com_h2c.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/include/hal_com_h2c.h
+--- linux-5.11.4/3rdparty/rtl8812au/include/hal_com_h2c.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/include/hal_com_h2c.h 2021-03-07 18:16:17.085957519 +0200
@@ -0,0 +1,635 @@
+/******************************************************************************
+ *
@@ -378867,11 +375084,9 @@ index 000000000..13158bcb6
+u8 rtw_hal_set_req_per_rpt_cmd(_adapter *adapter, u8 group_macid,
+ u8 rpt_type, u32 macid_bitmap);
+#endif
-diff --git linux-5.8/3rdparty/rtl8812au/include/hal_com_led.h linux-5.8/3rdparty/rtl8812au/include/hal_com_led.h
-new file mode 100644
-index 000000000..d88556df7
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/include/hal_com_led.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/include/hal_com_led.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/include/hal_com_led.h
+--- linux-5.11.4/3rdparty/rtl8812au/include/hal_com_led.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/include/hal_com_led.h 2021-03-07 18:16:17.085957519 +0200
@@ -0,0 +1,437 @@
+/******************************************************************************
+ *
@@ -379310,11 +375525,9 @@ index 000000000..d88556df7
+
+#endif /*__HAL_COMMON_LED_H_*/
+
-diff --git linux-5.8/3rdparty/rtl8812au/include/hal_com_phycfg.h linux-5.8/3rdparty/rtl8812au/include/hal_com_phycfg.h
-new file mode 100644
-index 000000000..3c7073dcd
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/include/hal_com_phycfg.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/include/hal_com_phycfg.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/include/hal_com_phycfg.h
+--- linux-5.11.4/3rdparty/rtl8812au/include/hal_com_phycfg.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/include/hal_com_phycfg.h 2021-03-07 18:16:17.085957519 +0200
@@ -0,0 +1,299 @@
+/******************************************************************************
+ *
@@ -379615,11 +375828,9 @@ index 000000000..3c7073dcd
+#endif /* CONFIG_LOAD_PHY_PARA_FROM_FILE */
+u8 phy_check_under_survey_ch(_adapter *adapter);
+#endif /* __HAL_COMMON_H__ */
-diff --git linux-5.8/3rdparty/rtl8812au/include/hal_com_reg.h linux-5.8/3rdparty/rtl8812au/include/hal_com_reg.h
-new file mode 100644
-index 000000000..420367194
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/include/hal_com_reg.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/include/hal_com_reg.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/include/hal_com_reg.h
+--- linux-5.11.4/3rdparty/rtl8812au/include/hal_com_reg.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/include/hal_com_reg.h 2021-03-07 18:16:17.086957566 +0200
@@ -0,0 +1,1887 @@
+/******************************************************************************
+ *
@@ -381508,11 +377719,9 @@ index 000000000..420367194
+#define HAL_8188E_HW_GPIO_WPS_BIT BIT(7)
+
+#endif /* __HAL_COMMON_H__ */
-diff --git linux-5.8/3rdparty/rtl8812au/include/hal_data.h linux-5.8/3rdparty/rtl8812au/include/hal_data.h
-new file mode 100644
-index 000000000..3f28e1586
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/include/hal_data.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/include/hal_data.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/include/hal_data.h
+--- linux-5.11.4/3rdparty/rtl8812au/include/hal_data.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/include/hal_data.h 2021-03-07 18:16:17.086957566 +0200
@@ -0,0 +1,1105 @@
+/******************************************************************************
+ *
@@ -382619,11 +378828,9 @@ index 000000000..3f28e1586
+*/
+
+#endif /* __HAL_DATA_H__ */
-diff --git linux-5.8/3rdparty/rtl8812au/include/hal_gspi.h linux-5.8/3rdparty/rtl8812au/include/hal_gspi.h
-new file mode 100644
-index 000000000..51d491cdb
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/include/hal_gspi.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/include/hal_gspi.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/include/hal_gspi.h
+--- linux-5.11.4/3rdparty/rtl8812au/include/hal_gspi.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/include/hal_gspi.h 2021-03-07 18:16:17.086957566 +0200
@@ -0,0 +1,26 @@
+/******************************************************************************
+ *
@@ -382651,11 +378858,9 @@ index 000000000..51d491cdb
+u32 rtw_hal_get_gspi_tx_max_length(PADAPTER padapter, u8 queue_idx);
+
+#endif
-diff --git linux-5.8/3rdparty/rtl8812au/include/hal_ic_cfg.h linux-5.8/3rdparty/rtl8812au/include/hal_ic_cfg.h
-new file mode 100644
-index 000000000..cc3ab5cad
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/include/hal_ic_cfg.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/include/hal_ic_cfg.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/include/hal_ic_cfg.h
+--- linux-5.11.4/3rdparty/rtl8812au/include/hal_ic_cfg.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/include/hal_ic_cfg.h 2021-03-07 18:16:17.086957566 +0200
@@ -0,0 +1,313 @@
+/******************************************************************************
+ *
@@ -382970,11 +379175,9 @@ index 000000000..cc3ab5cad
+#endif
+
+#endif /*__HAL_IC_CFG_H__*/
-diff --git linux-5.8/3rdparty/rtl8812au/include/hal_intf.h linux-5.8/3rdparty/rtl8812au/include/hal_intf.h
-new file mode 100644
-index 000000000..f77fa441c
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/include/hal_intf.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/include/hal_intf.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/include/hal_intf.h
+--- linux-5.11.4/3rdparty/rtl8812au/include/hal_intf.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/include/hal_intf.h 2021-03-07 18:16:17.086957566 +0200
@@ -0,0 +1,849 @@
+/******************************************************************************
+ *
@@ -383825,11 +380028,9 @@ index 000000000..f77fa441c
+#endif
+
+#endif /* __HAL_INTF_H__ */
-diff --git linux-5.8/3rdparty/rtl8812au/include/hal_pg.h linux-5.8/3rdparty/rtl8812au/include/hal_pg.h
-new file mode 100644
-index 000000000..b807ca84a
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/include/hal_pg.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/include/hal_pg.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/include/hal_pg.h
+--- linux-5.11.4/3rdparty/rtl8812au/include/hal_pg.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/include/hal_pg.h 2021-03-07 18:16:17.086957566 +0200
@@ -0,0 +1,880 @@
+/******************************************************************************
+ *
@@ -384711,11 +380912,9 @@ index 000000000..b807ca84a
+
+
+#endif
-diff --git linux-5.8/3rdparty/rtl8812au/include/hal_phy.h linux-5.8/3rdparty/rtl8812au/include/hal_phy.h
-new file mode 100644
-index 000000000..342613be1
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/include/hal_phy.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/include/hal_phy.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/include/hal_phy.h
+--- linux-5.11.4/3rdparty/rtl8812au/include/hal_phy.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/include/hal_phy.h 2021-03-07 18:16:17.086957566 +0200
@@ -0,0 +1,234 @@
+/******************************************************************************
+ *
@@ -384951,11 +381150,9 @@ index 000000000..342613be1
+ IN PADAPTER Adapter);
+#endif /*#CONFIG_RF_SHADOW_RW*/
+#endif /* __HAL_COMMON_H__ */
-diff --git linux-5.8/3rdparty/rtl8812au/include/hal_phy_reg.h linux-5.8/3rdparty/rtl8812au/include/hal_phy_reg.h
-new file mode 100644
-index 000000000..6e6a99e61
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/include/hal_phy_reg.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/include/hal_phy_reg.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/include/hal_phy_reg.h
+--- linux-5.11.4/3rdparty/rtl8812au/include/hal_phy_reg.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/include/hal_phy_reg.h 2021-03-07 18:16:17.086957566 +0200
@@ -0,0 +1,25 @@
+/******************************************************************************
+ *
@@ -384982,11 +381179,143 @@ index 000000000..6e6a99e61
+/* #endif */
+
+#endif /* __HAL_PHY_REG_H__ */
-diff --git linux-5.8/3rdparty/rtl8812au/include/hal_sdio.h linux-5.8/3rdparty/rtl8812au/include/hal_sdio.h
-new file mode 100644
-index 000000000..c3578e2fc
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/include/hal_sdio.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/include/HalPwrSeqCmd.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/include/HalPwrSeqCmd.h
+--- linux-5.11.4/3rdparty/rtl8812au/include/HalPwrSeqCmd.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/include/HalPwrSeqCmd.h 2021-03-07 18:16:17.084957471 +0200
+@@ -0,0 +1,130 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __HALPWRSEQCMD_H__
++#define __HALPWRSEQCMD_H__
++
++#include
++
++/*---------------------------------------------*/
++/* 3 The value of cmd: 4 bits
++ *---------------------------------------------*/
++#define PWR_CMD_READ 0x00
++/* offset: the read register offset
++ * msk: the mask of the read value
++ * value: N/A, left by 0
++ * note: dirver shall implement this function by read & msk */
++
++#define PWR_CMD_WRITE 0x01
++/* offset: the read register offset
++ * msk: the mask of the write bits
++ * value: write value
++ * note: driver shall implement this cmd by read & msk after write */
++
++#define PWR_CMD_POLLING 0x02
++/* offset: the read register offset
++ * msk: the mask of the polled value
++ * value: the value to be polled, masked by the msd field.
++ * note: driver shall implement this cmd by
++ * do {
++ * if( (Read(offset) & msk) == (value & msk) )
++ * break;
++ * } while(not timeout); */
++
++#define PWR_CMD_DELAY 0x03
++/* offset: the value to delay
++ * msk: N/A
++ * value: the unit of delay, 0: us, 1: ms */
++
++#define PWR_CMD_END 0x04
++/* offset: N/A
++ * msk: N/A
++ * value: N/A */
++
++/*---------------------------------------------*/
++/* 3 The value of base: 4 bits
++ *---------------------------------------------
++ * define the base address of each block */
++#define PWR_BASEADDR_MAC 0x00
++#define PWR_BASEADDR_USB 0x01
++#define PWR_BASEADDR_PCIE 0x02
++#define PWR_BASEADDR_SDIO 0x03
++
++/*---------------------------------------------*/
++/* 3 The value of interface_msk: 4 bits
++ *---------------------------------------------*/
++#define PWR_INTF_SDIO_MSK BIT(0)
++#define PWR_INTF_USB_MSK BIT(1)
++#define PWR_INTF_PCI_MSK BIT(2)
++#define PWR_INTF_ALL_MSK (BIT(0) | BIT(1) | BIT(2) | BIT(3))
++
++/*---------------------------------------------*/
++/* 3 The value of fab_msk: 4 bits
++ *---------------------------------------------*/
++#define PWR_FAB_TSMC_MSK BIT(0)
++#define PWR_FAB_UMC_MSK BIT(1)
++#define PWR_FAB_ALL_MSK (BIT(0) | BIT(1) | BIT(2) | BIT(3))
++
++/*---------------------------------------------*/
++/* 3 The value of cut_msk: 8 bits
++ *---------------------------------------------*/
++#define PWR_CUT_TESTCHIP_MSK BIT(0)
++#define PWR_CUT_A_MSK BIT(1)
++#define PWR_CUT_B_MSK BIT(2)
++#define PWR_CUT_C_MSK BIT(3)
++#define PWR_CUT_D_MSK BIT(4)
++#define PWR_CUT_E_MSK BIT(5)
++#define PWR_CUT_F_MSK BIT(6)
++#define PWR_CUT_G_MSK BIT(7)
++#define PWR_CUT_ALL_MSK 0xFF
++
++
++typedef enum _PWRSEQ_CMD_DELAY_UNIT_ {
++ PWRSEQ_DELAY_US,
++ PWRSEQ_DELAY_MS,
++} PWRSEQ_DELAY_UNIT;
++
++typedef struct _WL_PWR_CFG_ {
++ u16 offset;
++ u8 cut_msk;
++ u8 fab_msk:4;
++ u8 interface_msk:4;
++ u8 base:4;
++ u8 cmd:4;
++ u8 msk;
++ u8 value;
++} WLAN_PWR_CFG, *PWLAN_PWR_CFG;
++
++
++#define GET_PWR_CFG_OFFSET(__PWR_CMD) ((__PWR_CMD).offset)
++#define GET_PWR_CFG_CUT_MASK(__PWR_CMD) ((__PWR_CMD).cut_msk)
++#define GET_PWR_CFG_FAB_MASK(__PWR_CMD) ((__PWR_CMD).fab_msk)
++#define GET_PWR_CFG_INTF_MASK(__PWR_CMD) ((__PWR_CMD).interface_msk)
++#define GET_PWR_CFG_BASE(__PWR_CMD) ((__PWR_CMD).base)
++#define GET_PWR_CFG_CMD(__PWR_CMD) ((__PWR_CMD).cmd)
++#define GET_PWR_CFG_MASK(__PWR_CMD) ((__PWR_CMD).msk)
++#define GET_PWR_CFG_VALUE(__PWR_CMD) ((__PWR_CMD).value)
++
++
++/* ********************************************************************************
++ * Prototype of protected function.
++ * ******************************************************************************** */
++u8 HalPwrSeqCmdParsing(
++ PADAPTER padapter,
++ u8 CutVersion,
++ u8 FabVersion,
++ u8 InterfaceType,
++ WLAN_PWR_CFG PwrCfgCmd[]);
++
++#endif
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/include/hal_sdio.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/include/hal_sdio.h
+--- linux-5.11.4/3rdparty/rtl8812au/include/hal_sdio.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/include/hal_sdio.h 2021-03-07 18:16:17.086957566 +0200
@@ -0,0 +1,56 @@
+/******************************************************************************
+ *
@@ -385044,11 +381373,689 @@ index 000000000..c3578e2fc
+u32 cmd53_4byte_alignment(struct intf_hdl *pintfhdl, u32 addr);
+
+#endif /* __HAL_SDIO_H_ */
-diff --git linux-5.8/3rdparty/rtl8812au/include/ieee80211.h linux-5.8/3rdparty/rtl8812au/include/ieee80211.h
-new file mode 100644
-index 000000000..92dd31732
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/include/ieee80211.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/include/HalVerDef.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/include/HalVerDef.h
+--- linux-5.11.4/3rdparty/rtl8812au/include/HalVerDef.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/include/HalVerDef.h 2021-03-07 18:16:17.084957471 +0200
+@@ -0,0 +1,201 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __HAL_VERSION_DEF_H__
++#define __HAL_VERSION_DEF_H__
++
++#define TRUE _TRUE
++#define FALSE _FALSE
++
++/* HAL_IC_TYPE_E */
++typedef enum tag_HAL_IC_Type_Definition {
++ CHIP_8192S = 0,
++ CHIP_8188C = 1,
++ CHIP_8192C = 2,
++ CHIP_8192D = 3,
++ CHIP_8723A = 4,
++ CHIP_8188E = 5,
++ CHIP_8812 = 6,
++ CHIP_8821 = 7,
++ CHIP_8723B = 8,
++ CHIP_8192E = 9,
++ CHIP_8814A = 10,
++ CHIP_8703B = 11,
++ CHIP_8188F = 12,
++ CHIP_8822B = 13,
++ CHIP_8723D = 14,
++ CHIP_8821C = 15,
++ CHIP_8710B = 16,
++ CHIP_8192F = 17,
++ CHIP_8188GTV = 18,
++} HAL_IC_TYPE_E;
++
++/* HAL_CHIP_TYPE_E */
++typedef enum tag_HAL_CHIP_Type_Definition {
++ TEST_CHIP = 0,
++ NORMAL_CHIP = 1,
++ FPGA = 2,
++} HAL_CHIP_TYPE_E;
++
++/* HAL_CUT_VERSION_E */
++typedef enum tag_HAL_Cut_Version_Definition {
++ A_CUT_VERSION = 0,
++ B_CUT_VERSION = 1,
++ C_CUT_VERSION = 2,
++ D_CUT_VERSION = 3,
++ E_CUT_VERSION = 4,
++ F_CUT_VERSION = 5,
++ G_CUT_VERSION = 6,
++ H_CUT_VERSION = 7,
++ I_CUT_VERSION = 8,
++ J_CUT_VERSION = 9,
++ K_CUT_VERSION = 10,
++} HAL_CUT_VERSION_E;
++
++/* HAL_Manufacturer */
++typedef enum tag_HAL_Manufacturer_Version_Definition {
++ CHIP_VENDOR_TSMC = 0,
++ CHIP_VENDOR_UMC = 1,
++ CHIP_VENDOR_SMIC = 2,
++} HAL_VENDOR_E;
++
++typedef enum tag_HAL_RF_Type_Definition {
++ RF_TYPE_1T1R = 0,
++ RF_TYPE_1T2R = 1,
++ RF_TYPE_2T2R = 2,
++ RF_TYPE_2T3R = 3,
++ RF_TYPE_2T4R = 4,
++ RF_TYPE_3T3R = 5,
++ RF_TYPE_3T4R = 6,
++ RF_TYPE_4T4R = 7,
++} HAL_RF_TYPE_E;
++
++typedef struct tag_HAL_VERSION {
++ HAL_IC_TYPE_E ICType;
++ HAL_CHIP_TYPE_E ChipType;
++ HAL_CUT_VERSION_E CUTVersion;
++ HAL_VENDOR_E VendorType;
++ HAL_RF_TYPE_E RFType;
++ u8 ROMVer;
++} HAL_VERSION, *PHAL_VERSION;
++
++/* VERSION_8192C VersionID;
++ * HAL_VERSION VersionID; */
++
++/* Get element */
++#define GET_CVID_IC_TYPE(version) ((HAL_IC_TYPE_E)(((HAL_VERSION)version).ICType))
++#define GET_CVID_CHIP_TYPE(version) ((HAL_CHIP_TYPE_E)(((HAL_VERSION)version).ChipType))
++#define GET_CVID_RF_TYPE(version) ((HAL_RF_TYPE_E)(((HAL_VERSION)version).RFType))
++#define GET_CVID_MANUFACTUER(version) ((HAL_VENDOR_E)(((HAL_VERSION)version).VendorType))
++#define GET_CVID_CUT_VERSION(version) ((HAL_CUT_VERSION_E)(((HAL_VERSION)version).CUTVersion))
++#define GET_CVID_ROM_VERSION(version) ((((HAL_VERSION)version).ROMVer) & ROM_VERSION_MASK)
++
++/* ----------------------------------------------------------------------------
++ * Common Macro. --
++ * ----------------------------------------------------------------------------
++ * HAL_VERSION VersionID */
++
++/* HAL_IC_TYPE_E */
++#if 0
++ #define IS_81XXC(version) (((GET_CVID_IC_TYPE(version) == CHIP_8192C) || (GET_CVID_IC_TYPE(version) == CHIP_8188C)) ? TRUE : FALSE)
++ #define IS_8723_SERIES(version) ((GET_CVID_IC_TYPE(version) == CHIP_8723A) ? TRUE : FALSE)
++ #define IS_92D(version) ((GET_CVID_IC_TYPE(version) == CHIP_8192D) ? TRUE : FALSE)
++#endif
++
++#define IS_8188E(version) ((GET_CVID_IC_TYPE(version) == CHIP_8188E) ? TRUE : FALSE)
++#define IS_8188F(version) ((GET_CVID_IC_TYPE(version) == CHIP_8188F) ? TRUE : FALSE)
++#define IS_8188GTV(version) ((GET_CVID_IC_TYPE(version) == CHIP_8188GTV) ? TRUE : FALSE)
++#define IS_8192E(version) ((GET_CVID_IC_TYPE(version) == CHIP_8192E) ? TRUE : FALSE)
++#define IS_8812_SERIES(version) ((GET_CVID_IC_TYPE(version) == CHIP_8812) ? TRUE : FALSE)
++#define IS_8821_SERIES(version) ((GET_CVID_IC_TYPE(version) == CHIP_8821) ? TRUE : FALSE)
++#define IS_8814A_SERIES(version) ((GET_CVID_IC_TYPE(version) == CHIP_8814A) ? TRUE : FALSE)
++#define IS_8723B_SERIES(version) ((GET_CVID_IC_TYPE(version) == CHIP_8723B) ? TRUE : FALSE)
++#define IS_8703B_SERIES(version) ((GET_CVID_IC_TYPE(version) == CHIP_8703B) ? TRUE : FALSE)
++#define IS_8822B_SERIES(version) ((GET_CVID_IC_TYPE(version) == CHIP_8822B) ? TRUE : FALSE)
++#define IS_8821C_SERIES(version) ((GET_CVID_IC_TYPE(version) == CHIP_8821C) ? TRUE : FALSE)
++#define IS_8723D_SERIES(version) ((GET_CVID_IC_TYPE(version) == CHIP_8723D) ? TRUE : FALSE)
++#define IS_8710B_SERIES(version) ((GET_CVID_IC_TYPE(version) == CHIP_8710B) ? TRUE : FALSE)
++
++#define IS_8192F_SERIES(version)\
++ ((GET_CVID_IC_TYPE(version) == CHIP_8192F) ? TRUE : FALSE)
++/* HAL_CHIP_TYPE_E */
++#define IS_TEST_CHIP(version) ((GET_CVID_CHIP_TYPE(version) == TEST_CHIP) ? TRUE : FALSE)
++#define IS_NORMAL_CHIP(version) ((GET_CVID_CHIP_TYPE(version) == NORMAL_CHIP) ? TRUE : FALSE)
++
++/* HAL_CUT_VERSION_E */
++#define IS_A_CUT(version) ((GET_CVID_CUT_VERSION(version) == A_CUT_VERSION) ? TRUE : FALSE)
++#define IS_B_CUT(version) ((GET_CVID_CUT_VERSION(version) == B_CUT_VERSION) ? TRUE : FALSE)
++#define IS_C_CUT(version) ((GET_CVID_CUT_VERSION(version) == C_CUT_VERSION) ? TRUE : FALSE)
++#define IS_D_CUT(version) ((GET_CVID_CUT_VERSION(version) == D_CUT_VERSION) ? TRUE : FALSE)
++#define IS_E_CUT(version) ((GET_CVID_CUT_VERSION(version) == E_CUT_VERSION) ? TRUE : FALSE)
++#define IS_F_CUT(version) ((GET_CVID_CUT_VERSION(version) == F_CUT_VERSION) ? TRUE : FALSE)
++#define IS_I_CUT(version) ((GET_CVID_CUT_VERSION(version) == I_CUT_VERSION) ? TRUE : FALSE)
++#define IS_J_CUT(version) ((GET_CVID_CUT_VERSION(version) == J_CUT_VERSION) ? TRUE : FALSE)
++#define IS_K_CUT(version) ((GET_CVID_CUT_VERSION(version) == K_CUT_VERSION) ? TRUE : FALSE)
++
++/* HAL_VENDOR_E */
++#define IS_CHIP_VENDOR_TSMC(version) ((GET_CVID_MANUFACTUER(version) == CHIP_VENDOR_TSMC) ? TRUE : FALSE)
++#define IS_CHIP_VENDOR_UMC(version) ((GET_CVID_MANUFACTUER(version) == CHIP_VENDOR_UMC) ? TRUE : FALSE)
++#define IS_CHIP_VENDOR_SMIC(version) ((GET_CVID_MANUFACTUER(version) == CHIP_VENDOR_SMIC) ? TRUE : FALSE)
++
++/* HAL_RF_TYPE_E */
++#define IS_1T1R(version) ((GET_CVID_RF_TYPE(version) == RF_TYPE_1T1R) ? TRUE : FALSE)
++#define IS_1T2R(version) ((GET_CVID_RF_TYPE(version) == RF_TYPE_1T2R) ? TRUE : FALSE)
++#define IS_2T2R(version) ((GET_CVID_RF_TYPE(version) == RF_TYPE_2T2R) ? TRUE : FALSE)
++#define IS_3T3R(version) ((GET_CVID_RF_TYPE(version) == RF_TYPE_3T3R) ? TRUE : FALSE)
++#define IS_3T4R(version) ((GET_CVID_RF_TYPE(version) == RF_TYPE_3T4R) ? TRUE : FALSE)
++#define IS_4T4R(version) ((GET_CVID_RF_TYPE(version) == RF_TYPE_4T4R) ? TRUE : FALSE)
++
++
++
++/* ----------------------------------------------------------------------------
++ * Chip version Macro. --
++ * ---------------------------------------------------------------------------- */
++#if 0
++ #define IS_81XXC_TEST_CHIP(version) ((IS_81XXC(version) && (!IS_NORMAL_CHIP(version))) ? TRUE : FALSE)
++
++ #define IS_92C_SERIAL(version) ((IS_81XXC(version) && IS_2T2R(version)) ? TRUE : FALSE)
++ #define IS_81xxC_VENDOR_UMC_A_CUT(version) (IS_81XXC(version) ? (IS_CHIP_VENDOR_UMC(version) ? (IS_A_CUT(version) ? TRUE : FALSE) : FALSE) : FALSE)
++ #define IS_81xxC_VENDOR_UMC_B_CUT(version) (IS_81XXC(version) ? (IS_CHIP_VENDOR_UMC(version) ? (IS_B_CUT(version) ? TRUE : FALSE) : FALSE) : FALSE)
++ #define IS_81xxC_VENDOR_UMC_C_CUT(version) (IS_81XXC(version) ? (IS_CHIP_VENDOR_UMC(version) ? (IS_C_CUT(version) ? TRUE : FALSE) : FALSE) : FALSE)
++
++ #define IS_NORMAL_CHIP92D(version) ((IS_92D(version)) ? ((GET_CVID_CHIP_TYPE(version) == NORMAL_CHIP) ? TRUE : FALSE) : FALSE)
++
++ #define IS_92D_SINGLEPHY(version) ((IS_92D(version)) ? (IS_2T2R(version) ? TRUE : FALSE) : FALSE)
++ #define IS_92D_C_CUT(version) ((IS_92D(version)) ? (IS_C_CUT(version) ? TRUE : FALSE) : FALSE)
++ #define IS_92D_D_CUT(version) ((IS_92D(version)) ? (IS_D_CUT(version) ? TRUE : FALSE) : FALSE)
++ #define IS_92D_E_CUT(version) ((IS_92D(version)) ? (IS_E_CUT(version) ? TRUE : FALSE) : FALSE)
++
++ #define IS_8723A_A_CUT(version) ((IS_8723_SERIES(version)) ? (IS_A_CUT(version) ? TRUE : FALSE) : FALSE)
++ #define IS_8723A_B_CUT(version) ((IS_8723_SERIES(version)) ? (IS_B_CUT(version) ? TRUE : FALSE) : FALSE)
++#endif
++#define IS_VENDOR_8188E_I_CUT_SERIES(_Adapter) ((IS_8188E(GET_HAL_DATA(_Adapter)->version_id)) ? ((GET_CVID_CUT_VERSION(GET_HAL_DATA(_Adapter)->version_id) >= I_CUT_VERSION) ? TRUE : FALSE) : FALSE)
++#define IS_VENDOR_8812A_TEST_CHIP(_Adapter) ((IS_8812_SERIES(GET_HAL_DATA(_Adapter)->version_id)) ? ((IS_NORMAL_CHIP(GET_HAL_DATA(_Adapter)->version_id)) ? FALSE : TRUE) : FALSE)
++#define IS_VENDOR_8812A_MP_CHIP(_Adapter) ((IS_8812_SERIES(GET_HAL_DATA(_Adapter)->version_id)) ? ((IS_NORMAL_CHIP(GET_HAL_DATA(_Adapter)->version_id)) ? TRUE : FALSE) : FALSE)
++#define IS_VENDOR_8812A_C_CUT(_Adapter) ((IS_8812_SERIES(GET_HAL_DATA(_Adapter)->version_id)) ? ((GET_CVID_CUT_VERSION(GET_HAL_DATA(_Adapter)->version_id) == C_CUT_VERSION) ? TRUE : FALSE) : FALSE)
++
++#define IS_VENDOR_8821A_TEST_CHIP(_Adapter) ((IS_8821_SERIES(GET_HAL_DATA(_Adapter)->version_id)) ? ((IS_NORMAL_CHIP(GET_HAL_DATA(_Adapter)->version_id)) ? FALSE : TRUE) : FALSE)
++#define IS_VENDOR_8821A_MP_CHIP(_Adapter) ((IS_8821_SERIES(GET_HAL_DATA(_Adapter)->version_id)) ? ((IS_NORMAL_CHIP(GET_HAL_DATA(_Adapter)->version_id)) ? TRUE : FALSE) : FALSE)
++
++#define IS_VENDOR_8192E_B_CUT(_Adapter) ((GET_CVID_CUT_VERSION(GET_HAL_DATA(_Adapter)->version_id) == B_CUT_VERSION) ? TRUE : FALSE)
++
++#define IS_VENDOR_8723B_TEST_CHIP(_Adapter) ((IS_8723B_SERIES(GET_HAL_DATA(_Adapter)->version_id)) ? ((IS_NORMAL_CHIP(GET_HAL_DATA(_Adapter)->version_id)) ? FALSE : TRUE) : FALSE)
++#define IS_VENDOR_8723B_MP_CHIP(_Adapter) ((IS_8723B_SERIES(GET_HAL_DATA(_Adapter)->version_id)) ? ((IS_NORMAL_CHIP(GET_HAL_DATA(_Adapter)->version_id)) ? TRUE : FALSE) : FALSE)
++
++#define IS_VENDOR_8703B_TEST_CHIP(_Adapter) ((IS_8703B_SERIES(GET_HAL_DATA(_Adapter)->version_id)) ? ((IS_NORMAL_CHIP(GET_HAL_DATA(_Adapter)->version_id)) ? FALSE : TRUE) : FALSE)
++#define IS_VENDOR_8703B_MP_CHIP(_Adapter) ((IS_8703B_SERIES(GET_HAL_DATA(_Adapter)->version_id)) ? ((IS_NORMAL_CHIP(GET_HAL_DATA(_Adapter)->version_id)) ? TRUE : FALSE) : FALSE)
++#define IS_VENDOR_8814A_TEST_CHIP(_Adapter) ((IS_8814A_SERIES(GET_HAL_DATA(_Adapter)->version_id)) ? ((IS_NORMAL_CHIP(GET_HAL_DATA(_Adapter)->version_id)) ? FALSE : TRUE) : FALSE)
++#define IS_VENDOR_8814A_MP_CHIP(_Adapter) ((IS_8814A_SERIES(GET_HAL_DATA(_Adapter)->version_id)) ? ((IS_NORMAL_CHIP(GET_HAL_DATA(_Adapter)->version_id)) ? TRUE : FALSE) : FALSE)
++
++#endif
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/include/ieee80211_ext.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/include/ieee80211_ext.h
+--- linux-5.11.4/3rdparty/rtl8812au/include/ieee80211_ext.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/include/ieee80211_ext.h 2021-03-07 18:16:17.087957613 +0200
+@@ -0,0 +1,471 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __IEEE80211_EXT_H
++#define __IEEE80211_EXT_H
++
++#include
++#include
++#include
++
++#define WMM_OUI_TYPE 2
++#define WMM_OUI_SUBTYPE_INFORMATION_ELEMENT 0
++#define WMM_OUI_SUBTYPE_PARAMETER_ELEMENT 1
++#define WMM_OUI_SUBTYPE_TSPEC_ELEMENT 2
++#define WMM_VERSION 1
++
++#define WPA_PROTO_WPA BIT(0)
++#define WPA_PROTO_RSN BIT(1)
++
++#define WPA_KEY_MGMT_IEEE8021X BIT(0)
++#define WPA_KEY_MGMT_PSK BIT(1)
++#define WPA_KEY_MGMT_NONE BIT(2)
++#define WPA_KEY_MGMT_IEEE8021X_NO_WPA BIT(3)
++#define WPA_KEY_MGMT_WPA_NONE BIT(4)
++
++
++#define WPA_CAPABILITY_PREAUTH BIT(0)
++#define WPA_CAPABILITY_MGMT_FRAME_PROTECTION BIT(6)
++#define WPA_CAPABILITY_PEERKEY_ENABLED BIT(9)
++
++
++#define PMKID_LEN 16
++
++
++#ifdef PLATFORM_LINUX
++struct wpa_ie_hdr {
++ u8 elem_id;
++ u8 len;
++ u8 oui[4]; /* 24-bit OUI followed by 8-bit OUI type */
++ u8 version[2]; /* little endian */
++} __attribute__((packed));
++
++struct rsn_ie_hdr {
++ u8 elem_id; /* WLAN_EID_RSN */
++ u8 len;
++ u8 version[2]; /* little endian */
++} __attribute__((packed));
++
++struct wme_ac_parameter {
++#if defined(CONFIG_LITTLE_ENDIAN)
++ /* byte 1 */
++ u8 aifsn:4,
++ acm:1,
++ aci:2,
++ reserved:1;
++
++ /* byte 2 */
++ u8 eCWmin:4,
++ eCWmax:4;
++#elif defined(CONFIG_BIG_ENDIAN)
++ /* byte 1 */
++ u8 reserved:1,
++ aci:2,
++ acm:1,
++ aifsn:4;
++
++ /* byte 2 */
++ u8 eCWmax:4,
++ eCWmin:4;
++#else
++#error "Please fix "
++#endif
++
++ /* bytes 3 & 4 */
++ u16 txopLimit;
++} __attribute__((packed));
++
++struct wme_parameter_element {
++ /* required fields for WME version 1 */
++ u8 oui[3];
++ u8 oui_type;
++ u8 oui_subtype;
++ u8 version;
++ u8 acInfo;
++ u8 reserved;
++ struct wme_ac_parameter ac[4];
++
++} __attribute__((packed));
++
++#endif
++
++#ifdef PLATFORM_WINDOWS
++
++#pragma pack(1)
++
++struct wpa_ie_hdr {
++ u8 elem_id;
++ u8 len;
++ u8 oui[4]; /* 24-bit OUI followed by 8-bit OUI type */
++ u8 version[2]; /* little endian */
++};
++
++struct rsn_ie_hdr {
++ u8 elem_id; /* WLAN_EID_RSN */
++ u8 len;
++ u8 version[2]; /* little endian */
++};
++
++#pragma pack()
++
++#endif
++
++#define WPA_PUT_LE16(a, val) \
++ do { \
++ (a)[1] = ((u16) (val)) >> 8; \
++ (a)[0] = ((u16) (val)) & 0xff; \
++ } while (0)
++
++#define WPA_PUT_BE32(a, val) \
++ do { \
++ (a)[0] = (u8) ((((u32) (val)) >> 24) & 0xff); \
++ (a)[1] = (u8) ((((u32) (val)) >> 16) & 0xff); \
++ (a)[2] = (u8) ((((u32) (val)) >> 8) & 0xff); \
++ (a)[3] = (u8) (((u32) (val)) & 0xff); \
++ } while (0)
++
++#define WPA_PUT_LE32(a, val) \
++ do { \
++ (a)[3] = (u8) ((((u32) (val)) >> 24) & 0xff); \
++ (a)[2] = (u8) ((((u32) (val)) >> 16) & 0xff); \
++ (a)[1] = (u8) ((((u32) (val)) >> 8) & 0xff); \
++ (a)[0] = (u8) (((u32) (val)) & 0xff); \
++ } while (0)
++
++#define RSN_SELECTOR_PUT(a, val) WPA_PUT_BE32((u8 *) (a), (val))
++/* #define RSN_SELECTOR_PUT(a, val) WPA_PUT_LE32((u8 *) (a), (val)) */
++
++
++
++/* Action category code */
++enum ieee80211_category {
++ WLAN_CATEGORY_SPECTRUM_MGMT = 0,
++ WLAN_CATEGORY_QOS = 1,
++ WLAN_CATEGORY_DLS = 2,
++ WLAN_CATEGORY_BACK = 3,
++ WLAN_CATEGORY_HT = 7,
++ WLAN_CATEGORY_WMM = 17,
++};
++
++/* SPECTRUM_MGMT action code */
++enum ieee80211_spectrum_mgmt_actioncode {
++ WLAN_ACTION_SPCT_MSR_REQ = 0,
++ WLAN_ACTION_SPCT_MSR_RPRT = 1,
++ WLAN_ACTION_SPCT_TPC_REQ = 2,
++ WLAN_ACTION_SPCT_TPC_RPRT = 3,
++ WLAN_ACTION_SPCT_CHL_SWITCH = 4,
++ WLAN_ACTION_SPCT_EXT_CHL_SWITCH = 5,
++};
++
++/* BACK action code */
++enum ieee80211_back_actioncode {
++ WLAN_ACTION_ADDBA_REQ = 0,
++ WLAN_ACTION_ADDBA_RESP = 1,
++ WLAN_ACTION_DELBA = 2,
++};
++
++/* HT features action code */
++enum ieee80211_ht_actioncode {
++ WLAN_ACTION_NOTIFY_CH_WIDTH = 0,
++ WLAN_ACTION_SM_PS = 1,
++ WLAN_ACTION_PSPM = 2,
++ WLAN_ACTION_PCO_PHASE = 3,
++ WLAN_ACTION_MIMO_CSI_MX = 4,
++ WLAN_ACTION_MIMO_NONCP_BF = 5,
++ WLAN_ACTION_MIMP_CP_BF = 6,
++ WLAN_ACTION_ASEL_INDICATES_FB = 7,
++ WLAN_ACTION_HI_INFO_EXCHG = 8,
++};
++
++/* BACK (block-ack) parties */
++enum ieee80211_back_parties {
++ WLAN_BACK_RECIPIENT = 0,
++ WLAN_BACK_INITIATOR = 1,
++ WLAN_BACK_TIMER = 2,
++};
++
++#ifdef PLATFORM_LINUX
++
++struct ieee80211_mgmt {
++ u16 frame_control;
++ u16 duration;
++ u8 da[6];
++ u8 sa[6];
++ u8 bssid[6];
++ u16 seq_ctrl;
++ union {
++ struct {
++ u16 auth_alg;
++ u16 auth_transaction;
++ u16 status_code;
++ /* possibly followed by Challenge text */
++ u8 variable[0];
++ } __attribute__((packed)) auth;
++ struct {
++ u16 reason_code;
++ } __attribute__((packed)) deauth;
++ struct {
++ u16 capab_info;
++ u16 listen_interval;
++ /* followed by SSID and Supported rates */
++ u8 variable[0];
++ } __attribute__((packed)) assoc_req;
++ struct {
++ u16 capab_info;
++ u16 status_code;
++ u16 aid;
++ /* followed by Supported rates */
++ u8 variable[0];
++ } __attribute__((packed)) assoc_resp, reassoc_resp;
++ struct {
++ u16 capab_info;
++ u16 listen_interval;
++ u8 current_ap[6];
++ /* followed by SSID and Supported rates */
++ u8 variable[0];
++ } __attribute__((packed)) reassoc_req;
++ struct {
++ u16 reason_code;
++ } __attribute__((packed)) disassoc;
++ struct {
++ __le64 timestamp;
++ u16 beacon_int;
++ u16 capab_info;
++ /* followed by some of SSID, Supported rates,
++ * FH Params, DS Params, CF Params, IBSS Params, TIM */
++ u8 variable[0];
++ } __attribute__((packed)) beacon;
++ struct {
++ /* only variable items: SSID, Supported rates */
++ u8 variable[0];
++ } __attribute__((packed)) probe_req;
++ struct {
++ __le64 timestamp;
++ u16 beacon_int;
++ u16 capab_info;
++ /* followed by some of SSID, Supported rates,
++ * FH Params, DS Params, CF Params, IBSS Params */
++ u8 variable[0];
++ } __attribute__((packed)) probe_resp;
++ struct {
++ u8 category;
++ union {
++ struct {
++ u8 action_code;
++ u8 dialog_token;
++ u8 status_code;
++ u8 variable[0];
++ } __attribute__((packed)) wme_action;
++#if 0
++ struct {
++ u8 action_code;
++ u8 element_id;
++ u8 length;
++ struct ieee80211_channel_sw_ie sw_elem;
++ } __attribute__((packed)) chan_switch;
++ struct {
++ u8 action_code;
++ u8 dialog_token;
++ u8 element_id;
++ u8 length;
++ struct ieee80211_msrment_ie msr_elem;
++ } __attribute__((packed)) measurement;
++#endif
++ struct {
++ u8 action_code;
++ u8 dialog_token;
++ u16 capab;
++ u16 timeout;
++ u16 start_seq_num;
++ } __attribute__((packed)) addba_req;
++ struct {
++ u8 action_code;
++ u8 dialog_token;
++ u16 status;
++ u16 capab;
++ u16 timeout;
++ } __attribute__((packed)) addba_resp;
++ struct {
++ u8 action_code;
++ u16 params;
++ u16 reason_code;
++ } __attribute__((packed)) delba;
++ struct {
++ u8 action_code;
++ /* capab_info for open and confirm,
++ * reason for close
++ */
++ u16 aux;
++ /* Followed in plink_confirm by status
++ * code, AID and supported rates,
++ * and directly by supported rates in
++ * plink_open and plink_close
++ */
++ u8 variable[0];
++ } __attribute__((packed)) plink_action;
++ struct {
++ u8 action_code;
++ u8 variable[0];
++ } __attribute__((packed)) mesh_action;
++ } __attribute__((packed)) u;
++ } __attribute__((packed)) action;
++ } __attribute__((packed)) u;
++} __attribute__((packed));
++
++#endif
++
++
++#ifdef PLATFORM_WINDOWS
++
++#pragma pack(1)
++
++struct ieee80211_mgmt {
++ u16 frame_control;
++ u16 duration;
++ u8 da[6];
++ u8 sa[6];
++ u8 bssid[6];
++ u16 seq_ctrl;
++ union {
++ struct {
++ u16 auth_alg;
++ u16 auth_transaction;
++ u16 status_code;
++ /* possibly followed by Challenge text */
++ u8 variable[0];
++ } auth;
++ struct {
++ u16 reason_code;
++ } deauth;
++ struct {
++ u16 capab_info;
++ u16 listen_interval;
++ /* followed by SSID and Supported rates */
++ u8 variable[0];
++ } assoc_req;
++ struct {
++ u16 capab_info;
++ u16 status_code;
++ u16 aid;
++ /* followed by Supported rates */
++ u8 variable[0];
++ } assoc_resp, reassoc_resp;
++ struct {
++ u16 capab_info;
++ u16 listen_interval;
++ u8 current_ap[6];
++ /* followed by SSID and Supported rates */
++ u8 variable[0];
++ } reassoc_req;
++ struct {
++ u16 reason_code;
++ } disassoc;
++#if 0
++ struct {
++ __le64 timestamp;
++ u16 beacon_int;
++ u16 capab_info;
++ /* followed by some of SSID, Supported rates,
++ * FH Params, DS Params, CF Params, IBSS Params, TIM */
++ u8 variable[0];
++ } beacon;
++ struct {
++ /* only variable items: SSID, Supported rates */
++ u8 variable[0];
++ } probe_req;
++
++ struct {
++ __le64 timestamp;
++ u16 beacon_int;
++ u16 capab_info;
++ /* followed by some of SSID, Supported rates,
++ * FH Params, DS Params, CF Params, IBSS Params */
++ u8 variable[0];
++ } probe_resp;
++#endif
++ struct {
++ u8 category;
++ union {
++ struct {
++ u8 action_code;
++ u8 dialog_token;
++ u8 status_code;
++ u8 variable[0];
++ } wme_action;
++ #if 0
++ struct{
++ u8 action_code;
++ u8 element_id;
++ u8 length;
++ struct ieee80211_channel_sw_ie sw_elem;
++ } chan_switch;
++ struct{
++ u8 action_code;
++ u8 dialog_token;
++ u8 element_id;
++ u8 length;
++ struct ieee80211_msrment_ie msr_elem;
++ } measurement;
++ #endif
++ struct {
++ u8 action_code;
++ u8 dialog_token;
++ u16 capab;
++ u16 timeout;
++ u16 start_seq_num;
++ } addba_req;
++ struct {
++ u8 action_code;
++ u8 dialog_token;
++ u16 status;
++ u16 capab;
++ u16 timeout;
++ } addba_resp;
++ struct {
++ u8 action_code;
++ u16 params;
++ u16 reason_code;
++ } delba;
++ struct {
++ u8 action_code;
++ /* capab_info for open and confirm,
++ * reason for close
++ */
++ u16 aux;
++ /* Followed in plink_confirm by status
++ * code, AID and supported rates,
++ * and directly by supported rates in
++ * plink_open and plink_close
++ */
++ u8 variable[0];
++ } plink_action;
++ struct {
++ u8 action_code;
++ u8 variable[0];
++ } mesh_action;
++ } u;
++ } action;
++ } u;
++} ;
++
++#pragma pack()
++
++#endif
++
++/* mgmt header + 1 byte category code */
++#define IEEE80211_MIN_ACTION_SIZE FIELD_OFFSET(struct ieee80211_mgmt, u.action.u)
++
++
++
++#endif
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/include/ieee80211.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/include/ieee80211.h
+--- linux-5.11.4/3rdparty/rtl8812au/include/ieee80211.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/include/ieee80211.h 2021-03-07 18:16:17.087957613 +0200
@@ -0,0 +1,2204 @@
+/******************************************************************************
+ *
@@ -387254,488 +384261,9 @@ index 000000000..92dd31732
+
+
+#endif /* IEEE80211_H */
-diff --git linux-5.8/3rdparty/rtl8812au/include/ieee80211_ext.h linux-5.8/3rdparty/rtl8812au/include/ieee80211_ext.h
-new file mode 100644
-index 000000000..94a8e582d
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/include/ieee80211_ext.h
-@@ -0,0 +1,471 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __IEEE80211_EXT_H
-+#define __IEEE80211_EXT_H
-+
-+#include
-+#include
-+#include
-+
-+#define WMM_OUI_TYPE 2
-+#define WMM_OUI_SUBTYPE_INFORMATION_ELEMENT 0
-+#define WMM_OUI_SUBTYPE_PARAMETER_ELEMENT 1
-+#define WMM_OUI_SUBTYPE_TSPEC_ELEMENT 2
-+#define WMM_VERSION 1
-+
-+#define WPA_PROTO_WPA BIT(0)
-+#define WPA_PROTO_RSN BIT(1)
-+
-+#define WPA_KEY_MGMT_IEEE8021X BIT(0)
-+#define WPA_KEY_MGMT_PSK BIT(1)
-+#define WPA_KEY_MGMT_NONE BIT(2)
-+#define WPA_KEY_MGMT_IEEE8021X_NO_WPA BIT(3)
-+#define WPA_KEY_MGMT_WPA_NONE BIT(4)
-+
-+
-+#define WPA_CAPABILITY_PREAUTH BIT(0)
-+#define WPA_CAPABILITY_MGMT_FRAME_PROTECTION BIT(6)
-+#define WPA_CAPABILITY_PEERKEY_ENABLED BIT(9)
-+
-+
-+#define PMKID_LEN 16
-+
-+
-+#ifdef PLATFORM_LINUX
-+struct wpa_ie_hdr {
-+ u8 elem_id;
-+ u8 len;
-+ u8 oui[4]; /* 24-bit OUI followed by 8-bit OUI type */
-+ u8 version[2]; /* little endian */
-+} __attribute__((packed));
-+
-+struct rsn_ie_hdr {
-+ u8 elem_id; /* WLAN_EID_RSN */
-+ u8 len;
-+ u8 version[2]; /* little endian */
-+} __attribute__((packed));
-+
-+struct wme_ac_parameter {
-+#if defined(CONFIG_LITTLE_ENDIAN)
-+ /* byte 1 */
-+ u8 aifsn:4,
-+ acm:1,
-+ aci:2,
-+ reserved:1;
-+
-+ /* byte 2 */
-+ u8 eCWmin:4,
-+ eCWmax:4;
-+#elif defined(CONFIG_BIG_ENDIAN)
-+ /* byte 1 */
-+ u8 reserved:1,
-+ aci:2,
-+ acm:1,
-+ aifsn:4;
-+
-+ /* byte 2 */
-+ u8 eCWmax:4,
-+ eCWmin:4;
-+#else
-+#error "Please fix "
-+#endif
-+
-+ /* bytes 3 & 4 */
-+ u16 txopLimit;
-+} __attribute__((packed));
-+
-+struct wme_parameter_element {
-+ /* required fields for WME version 1 */
-+ u8 oui[3];
-+ u8 oui_type;
-+ u8 oui_subtype;
-+ u8 version;
-+ u8 acInfo;
-+ u8 reserved;
-+ struct wme_ac_parameter ac[4];
-+
-+} __attribute__((packed));
-+
-+#endif
-+
-+#ifdef PLATFORM_WINDOWS
-+
-+#pragma pack(1)
-+
-+struct wpa_ie_hdr {
-+ u8 elem_id;
-+ u8 len;
-+ u8 oui[4]; /* 24-bit OUI followed by 8-bit OUI type */
-+ u8 version[2]; /* little endian */
-+};
-+
-+struct rsn_ie_hdr {
-+ u8 elem_id; /* WLAN_EID_RSN */
-+ u8 len;
-+ u8 version[2]; /* little endian */
-+};
-+
-+#pragma pack()
-+
-+#endif
-+
-+#define WPA_PUT_LE16(a, val) \
-+ do { \
-+ (a)[1] = ((u16) (val)) >> 8; \
-+ (a)[0] = ((u16) (val)) & 0xff; \
-+ } while (0)
-+
-+#define WPA_PUT_BE32(a, val) \
-+ do { \
-+ (a)[0] = (u8) ((((u32) (val)) >> 24) & 0xff); \
-+ (a)[1] = (u8) ((((u32) (val)) >> 16) & 0xff); \
-+ (a)[2] = (u8) ((((u32) (val)) >> 8) & 0xff); \
-+ (a)[3] = (u8) (((u32) (val)) & 0xff); \
-+ } while (0)
-+
-+#define WPA_PUT_LE32(a, val) \
-+ do { \
-+ (a)[3] = (u8) ((((u32) (val)) >> 24) & 0xff); \
-+ (a)[2] = (u8) ((((u32) (val)) >> 16) & 0xff); \
-+ (a)[1] = (u8) ((((u32) (val)) >> 8) & 0xff); \
-+ (a)[0] = (u8) (((u32) (val)) & 0xff); \
-+ } while (0)
-+
-+#define RSN_SELECTOR_PUT(a, val) WPA_PUT_BE32((u8 *) (a), (val))
-+/* #define RSN_SELECTOR_PUT(a, val) WPA_PUT_LE32((u8 *) (a), (val)) */
-+
-+
-+
-+/* Action category code */
-+enum ieee80211_category {
-+ WLAN_CATEGORY_SPECTRUM_MGMT = 0,
-+ WLAN_CATEGORY_QOS = 1,
-+ WLAN_CATEGORY_DLS = 2,
-+ WLAN_CATEGORY_BACK = 3,
-+ WLAN_CATEGORY_HT = 7,
-+ WLAN_CATEGORY_WMM = 17,
-+};
-+
-+/* SPECTRUM_MGMT action code */
-+enum ieee80211_spectrum_mgmt_actioncode {
-+ WLAN_ACTION_SPCT_MSR_REQ = 0,
-+ WLAN_ACTION_SPCT_MSR_RPRT = 1,
-+ WLAN_ACTION_SPCT_TPC_REQ = 2,
-+ WLAN_ACTION_SPCT_TPC_RPRT = 3,
-+ WLAN_ACTION_SPCT_CHL_SWITCH = 4,
-+ WLAN_ACTION_SPCT_EXT_CHL_SWITCH = 5,
-+};
-+
-+/* BACK action code */
-+enum ieee80211_back_actioncode {
-+ WLAN_ACTION_ADDBA_REQ = 0,
-+ WLAN_ACTION_ADDBA_RESP = 1,
-+ WLAN_ACTION_DELBA = 2,
-+};
-+
-+/* HT features action code */
-+enum ieee80211_ht_actioncode {
-+ WLAN_ACTION_NOTIFY_CH_WIDTH = 0,
-+ WLAN_ACTION_SM_PS = 1,
-+ WLAN_ACTION_PSPM = 2,
-+ WLAN_ACTION_PCO_PHASE = 3,
-+ WLAN_ACTION_MIMO_CSI_MX = 4,
-+ WLAN_ACTION_MIMO_NONCP_BF = 5,
-+ WLAN_ACTION_MIMP_CP_BF = 6,
-+ WLAN_ACTION_ASEL_INDICATES_FB = 7,
-+ WLAN_ACTION_HI_INFO_EXCHG = 8,
-+};
-+
-+/* BACK (block-ack) parties */
-+enum ieee80211_back_parties {
-+ WLAN_BACK_RECIPIENT = 0,
-+ WLAN_BACK_INITIATOR = 1,
-+ WLAN_BACK_TIMER = 2,
-+};
-+
-+#ifdef PLATFORM_LINUX
-+
-+struct ieee80211_mgmt {
-+ u16 frame_control;
-+ u16 duration;
-+ u8 da[6];
-+ u8 sa[6];
-+ u8 bssid[6];
-+ u16 seq_ctrl;
-+ union {
-+ struct {
-+ u16 auth_alg;
-+ u16 auth_transaction;
-+ u16 status_code;
-+ /* possibly followed by Challenge text */
-+ u8 variable[0];
-+ } __attribute__((packed)) auth;
-+ struct {
-+ u16 reason_code;
-+ } __attribute__((packed)) deauth;
-+ struct {
-+ u16 capab_info;
-+ u16 listen_interval;
-+ /* followed by SSID and Supported rates */
-+ u8 variable[0];
-+ } __attribute__((packed)) assoc_req;
-+ struct {
-+ u16 capab_info;
-+ u16 status_code;
-+ u16 aid;
-+ /* followed by Supported rates */
-+ u8 variable[0];
-+ } __attribute__((packed)) assoc_resp, reassoc_resp;
-+ struct {
-+ u16 capab_info;
-+ u16 listen_interval;
-+ u8 current_ap[6];
-+ /* followed by SSID and Supported rates */
-+ u8 variable[0];
-+ } __attribute__((packed)) reassoc_req;
-+ struct {
-+ u16 reason_code;
-+ } __attribute__((packed)) disassoc;
-+ struct {
-+ __le64 timestamp;
-+ u16 beacon_int;
-+ u16 capab_info;
-+ /* followed by some of SSID, Supported rates,
-+ * FH Params, DS Params, CF Params, IBSS Params, TIM */
-+ u8 variable[0];
-+ } __attribute__((packed)) beacon;
-+ struct {
-+ /* only variable items: SSID, Supported rates */
-+ u8 variable[0];
-+ } __attribute__((packed)) probe_req;
-+ struct {
-+ __le64 timestamp;
-+ u16 beacon_int;
-+ u16 capab_info;
-+ /* followed by some of SSID, Supported rates,
-+ * FH Params, DS Params, CF Params, IBSS Params */
-+ u8 variable[0];
-+ } __attribute__((packed)) probe_resp;
-+ struct {
-+ u8 category;
-+ union {
-+ struct {
-+ u8 action_code;
-+ u8 dialog_token;
-+ u8 status_code;
-+ u8 variable[0];
-+ } __attribute__((packed)) wme_action;
-+#if 0
-+ struct {
-+ u8 action_code;
-+ u8 element_id;
-+ u8 length;
-+ struct ieee80211_channel_sw_ie sw_elem;
-+ } __attribute__((packed)) chan_switch;
-+ struct {
-+ u8 action_code;
-+ u8 dialog_token;
-+ u8 element_id;
-+ u8 length;
-+ struct ieee80211_msrment_ie msr_elem;
-+ } __attribute__((packed)) measurement;
-+#endif
-+ struct {
-+ u8 action_code;
-+ u8 dialog_token;
-+ u16 capab;
-+ u16 timeout;
-+ u16 start_seq_num;
-+ } __attribute__((packed)) addba_req;
-+ struct {
-+ u8 action_code;
-+ u8 dialog_token;
-+ u16 status;
-+ u16 capab;
-+ u16 timeout;
-+ } __attribute__((packed)) addba_resp;
-+ struct {
-+ u8 action_code;
-+ u16 params;
-+ u16 reason_code;
-+ } __attribute__((packed)) delba;
-+ struct {
-+ u8 action_code;
-+ /* capab_info for open and confirm,
-+ * reason for close
-+ */
-+ u16 aux;
-+ /* Followed in plink_confirm by status
-+ * code, AID and supported rates,
-+ * and directly by supported rates in
-+ * plink_open and plink_close
-+ */
-+ u8 variable[0];
-+ } __attribute__((packed)) plink_action;
-+ struct {
-+ u8 action_code;
-+ u8 variable[0];
-+ } __attribute__((packed)) mesh_action;
-+ } __attribute__((packed)) u;
-+ } __attribute__((packed)) action;
-+ } __attribute__((packed)) u;
-+} __attribute__((packed));
-+
-+#endif
-+
-+
-+#ifdef PLATFORM_WINDOWS
-+
-+#pragma pack(1)
-+
-+struct ieee80211_mgmt {
-+ u16 frame_control;
-+ u16 duration;
-+ u8 da[6];
-+ u8 sa[6];
-+ u8 bssid[6];
-+ u16 seq_ctrl;
-+ union {
-+ struct {
-+ u16 auth_alg;
-+ u16 auth_transaction;
-+ u16 status_code;
-+ /* possibly followed by Challenge text */
-+ u8 variable[0];
-+ } auth;
-+ struct {
-+ u16 reason_code;
-+ } deauth;
-+ struct {
-+ u16 capab_info;
-+ u16 listen_interval;
-+ /* followed by SSID and Supported rates */
-+ u8 variable[0];
-+ } assoc_req;
-+ struct {
-+ u16 capab_info;
-+ u16 status_code;
-+ u16 aid;
-+ /* followed by Supported rates */
-+ u8 variable[0];
-+ } assoc_resp, reassoc_resp;
-+ struct {
-+ u16 capab_info;
-+ u16 listen_interval;
-+ u8 current_ap[6];
-+ /* followed by SSID and Supported rates */
-+ u8 variable[0];
-+ } reassoc_req;
-+ struct {
-+ u16 reason_code;
-+ } disassoc;
-+#if 0
-+ struct {
-+ __le64 timestamp;
-+ u16 beacon_int;
-+ u16 capab_info;
-+ /* followed by some of SSID, Supported rates,
-+ * FH Params, DS Params, CF Params, IBSS Params, TIM */
-+ u8 variable[0];
-+ } beacon;
-+ struct {
-+ /* only variable items: SSID, Supported rates */
-+ u8 variable[0];
-+ } probe_req;
-+
-+ struct {
-+ __le64 timestamp;
-+ u16 beacon_int;
-+ u16 capab_info;
-+ /* followed by some of SSID, Supported rates,
-+ * FH Params, DS Params, CF Params, IBSS Params */
-+ u8 variable[0];
-+ } probe_resp;
-+#endif
-+ struct {
-+ u8 category;
-+ union {
-+ struct {
-+ u8 action_code;
-+ u8 dialog_token;
-+ u8 status_code;
-+ u8 variable[0];
-+ } wme_action;
-+ #if 0
-+ struct{
-+ u8 action_code;
-+ u8 element_id;
-+ u8 length;
-+ struct ieee80211_channel_sw_ie sw_elem;
-+ } chan_switch;
-+ struct{
-+ u8 action_code;
-+ u8 dialog_token;
-+ u8 element_id;
-+ u8 length;
-+ struct ieee80211_msrment_ie msr_elem;
-+ } measurement;
-+ #endif
-+ struct {
-+ u8 action_code;
-+ u8 dialog_token;
-+ u16 capab;
-+ u16 timeout;
-+ u16 start_seq_num;
-+ } addba_req;
-+ struct {
-+ u8 action_code;
-+ u8 dialog_token;
-+ u16 status;
-+ u16 capab;
-+ u16 timeout;
-+ } addba_resp;
-+ struct {
-+ u8 action_code;
-+ u16 params;
-+ u16 reason_code;
-+ } delba;
-+ struct {
-+ u8 action_code;
-+ /* capab_info for open and confirm,
-+ * reason for close
-+ */
-+ u16 aux;
-+ /* Followed in plink_confirm by status
-+ * code, AID and supported rates,
-+ * and directly by supported rates in
-+ * plink_open and plink_close
-+ */
-+ u8 variable[0];
-+ } plink_action;
-+ struct {
-+ u8 action_code;
-+ u8 variable[0];
-+ } mesh_action;
-+ } u;
-+ } action;
-+ } u;
-+} ;
-+
-+#pragma pack()
-+
-+#endif
-+
-+/* mgmt header + 1 byte category code */
-+#define IEEE80211_MIN_ACTION_SIZE FIELD_OFFSET(struct ieee80211_mgmt, u.action.u)
-+
-+
-+
-+#endif
-diff --git linux-5.8/3rdparty/rtl8812au/include/if_ether.h linux-5.8/3rdparty/rtl8812au/include/if_ether.h
-new file mode 100644
-index 000000000..a3007c4ab
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/include/if_ether.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/include/if_ether.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/include/if_ether.h
+--- linux-5.11.4/3rdparty/rtl8812au/include/if_ether.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/include/if_ether.h 2021-03-07 18:16:17.087957613 +0200
@@ -0,0 +1,106 @@
+/******************************************************************************
+ *
@@ -387843,11 +384371,9 @@ index 000000000..a3007c4ab
+
+
+#endif /* _LINUX_IF_ETHER_H */
-diff --git linux-5.8/3rdparty/rtl8812au/include/ip.h linux-5.8/3rdparty/rtl8812au/include/ip.h
-new file mode 100644
-index 000000000..4feb98fb0
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/include/ip.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/include/ip.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/include/ip.h
+--- linux-5.11.4/3rdparty/rtl8812au/include/ip.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/include/ip.h 2021-03-07 18:16:17.087957613 +0200
@@ -0,0 +1,135 @@
+/******************************************************************************
+ *
@@ -387984,11 +384510,9 @@ index 000000000..4feb98fb0
+};
+
+#endif /* _LINUX_IP_H */
-diff --git linux-5.8/3rdparty/rtl8812au/include/linux/old_unused_rtl_wireless.h linux-5.8/3rdparty/rtl8812au/include/linux/old_unused_rtl_wireless.h
-new file mode 100644
-index 000000000..c7f4a6c9b
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/include/linux/old_unused_rtl_wireless.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/include/linux/old_unused_rtl_wireless.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/include/linux/old_unused_rtl_wireless.h
+--- linux-5.11.4/3rdparty/rtl8812au/include/linux/old_unused_rtl_wireless.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/include/linux/old_unused_rtl_wireless.h 2021-03-07 18:16:17.087957613 +0200
@@ -0,0 +1,87 @@
+/******************************************************************************
+ *
@@ -388077,11 +384601,9 @@ index 000000000..c7f4a6c9b
+};
+
+#endif /* _LINUX_WIRELESS_H */
-diff --git linux-5.8/3rdparty/rtl8812au/include/mlme_osdep.h linux-5.8/3rdparty/rtl8812au/include/mlme_osdep.h
-new file mode 100644
-index 000000000..131eb0925
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/include/mlme_osdep.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/include/mlme_osdep.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/include/mlme_osdep.h
+--- linux-5.11.4/3rdparty/rtl8812au/include/mlme_osdep.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/include/mlme_osdep.h 2021-03-07 18:16:17.087957613 +0200
@@ -0,0 +1,25 @@
+/******************************************************************************
+ *
@@ -388108,11 +384630,9 @@ index 000000000..131eb0925
+void rtw_reset_securitypriv(_adapter *adapter);
+
+#endif /* _MLME_OSDEP_H_ */
-diff --git linux-5.8/3rdparty/rtl8812au/include/mp_custom_oid.h linux-5.8/3rdparty/rtl8812au/include/mp_custom_oid.h
-new file mode 100644
-index 000000000..8ed14413c
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/include/mp_custom_oid.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/include/mp_custom_oid.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/include/mp_custom_oid.h
+--- linux-5.11.4/3rdparty/rtl8812au/include/mp_custom_oid.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/include/mp_custom_oid.h 2021-03-07 18:16:17.087957613 +0200
@@ -0,0 +1,348 @@
+/******************************************************************************
+ *
@@ -388462,11 +384982,9 @@ index 000000000..8ed14413c
+#define OID_RT_PRO_EFUSE_MAP 0xFF871217 /* Q, S */
+
+#endif /* #ifndef __CUSTOM_OID_H */
-diff --git linux-5.8/3rdparty/rtl8812au/include/nic_spec.h linux-5.8/3rdparty/rtl8812au/include/nic_spec.h
-new file mode 100644
-index 000000000..913ef9ba8
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/include/nic_spec.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/include/nic_spec.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/include/nic_spec.h
+--- linux-5.11.4/3rdparty/rtl8812au/include/nic_spec.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/include/nic_spec.h 2021-03-07 18:16:17.087957613 +0200
@@ -0,0 +1,41 @@
+/******************************************************************************
+ *
@@ -388509,11 +385027,9 @@ index 000000000..913ef9ba8
+
+
+#endif /* __RTL8711_SPEC_H__ */
-diff --git linux-5.8/3rdparty/rtl8812au/include/osdep_intf.h linux-5.8/3rdparty/rtl8812au/include/osdep_intf.h
-new file mode 100644
-index 000000000..7be08808d
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/include/osdep_intf.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/include/osdep_intf.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/include/osdep_intf.h
+--- linux-5.11.4/3rdparty/rtl8812au/include/osdep_intf.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/include/osdep_intf.h 2021-03-07 18:16:17.087957613 +0200
@@ -0,0 +1,167 @@
+/******************************************************************************
+ *
@@ -388682,11 +385198,973 @@ index 000000000..7be08808d
+int rtw_resume_common(_adapter *padapter);
+
+#endif /* _OSDEP_INTF_H_ */
-diff --git linux-5.8/3rdparty/rtl8812au/include/osdep_service.h linux-5.8/3rdparty/rtl8812au/include/osdep_service.h
-new file mode 100644
-index 000000000..d7e375329
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/include/osdep_service.h
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/include/osdep_service_bsd.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/include/osdep_service_bsd.h
+--- linux-5.11.4/3rdparty/rtl8812au/include/osdep_service_bsd.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/include/osdep_service_bsd.h 2021-03-07 18:16:17.087957613 +0200
+@@ -0,0 +1,756 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++#ifndef __OSDEP_BSD_SERVICE_H_
++#define __OSDEP_BSD_SERVICE_H_
++
++
++#include
++#include
++#include
++#include
++#include
++#include
++#include
++#include
++#include
++#include
++#include
++#include
++#include
++#include
++#include
++#include
++#include
++#include
++#include
++#include
++#include
++#include
++#include
++#include
++
++#include
++#include
++#include
++#include
++#include
++#include
++#include
++#include
++
++
++#include
++#include
++#include
++#include
++#include
++
++#include
++#include
++#include
++#include
++
++#include
++#include
++#include "usbdevs.h"
++
++#define USB_DEBUG_VAR rum_debug
++#include
++
++#if 1 //Baron porting from linux, it's all temp solution, needs to check again
++#include
++#include /* XXX for PCPU_GET */
++// typedef struct semaphore _sema;
++ typedef struct sema _sema;
++// typedef spinlock_t _lock;
++ typedef struct mtx _lock;
++ typedef struct mtx _mutex;
++ typedef struct rtw_timer_list _timer;
++ struct list_head {
++ struct list_head *next, *prev;
++ };
++ struct __queue {
++ struct list_head queue;
++ _lock lock;
++ };
++
++ typedef struct mbuf _pkt;
++ typedef struct mbuf _buffer;
++
++ typedef struct __queue _queue;
++ typedef struct list_head _list;
++ typedef int _OS_STATUS;
++ //typedef u32 _irqL;
++ typedef unsigned long _irqL;
++ typedef struct ifnet * _nic_hdl;
++
++ typedef pid_t _thread_hdl_;
++// typedef struct thread _thread_hdl_;
++ typedef void thread_return;
++ typedef void* thread_context;
++
++ typedef void timer_hdl_return;
++ typedef void* timer_hdl_context;
++ typedef struct work_struct _workitem;
++
++#define KERNEL_VERSION(a,b,c) (((a) << 16) + ((b) << 8) + (c))
++/* emulate a modern version */
++#define LINUX_VERSION_CODE KERNEL_VERSION(2, 6, 35)
++
++#define WIRELESS_EXT -1
++#define HZ hz
++#define spin_lock_irqsave mtx_lock_irqsave
++#define spin_lock_bh mtx_lock_irqsave
++#define mtx_lock_irqsave(lock, x) mtx_lock(lock)//{local_irq_save((x)); mtx_lock_spin((lock));}
++//#define IFT_RTW 0xf9 //ifnet allocate type for RTW
++#define free_netdev if_free
++#define LIST_CONTAINOR(ptr, type, member) \
++ ((type *)((char *)(ptr)-(SIZE_T)(&((type *)0)->member)))
++#define container_of(p,t,n) (t*)((p)-&(((t*)0)->n))
++/*
++ * Linux timers are emulated using FreeBSD callout functions
++ * (and taskqueue functionality).
++ *
++ * Currently no timer stats functionality.
++ *
++ * See (linux_compat) processes.c
++ *
++ */
++struct rtw_timer_list {
++ struct callout callout;
++ void (*function)(void *);
++ void *arg;
++};
++
++struct workqueue_struct;
++struct work_struct;
++typedef void (*work_func_t)(struct work_struct *work);
++/* Values for the state of an item of work (work_struct) */
++typedef enum work_state {
++ WORK_STATE_UNSET = 0,
++ WORK_STATE_CALLOUT_PENDING = 1,
++ WORK_STATE_TASK_PENDING = 2,
++ WORK_STATE_WORK_CANCELLED = 3
++} work_state_t;
++
++struct work_struct {
++ struct task task; /* FreeBSD task */
++ work_state_t state; /* the pending or otherwise state of work. */
++ work_func_t func;
++};
++#define spin_unlock_irqrestore mtx_unlock_irqrestore
++#define spin_unlock_bh mtx_unlock_irqrestore
++#define mtx_unlock_irqrestore(lock,x) mtx_unlock(lock);
++extern void _rtw_spinlock_init(_lock *plock);
++
++//modify private structure to match freebsd
++#define BITS_PER_LONG 32
++union ktime {
++ s64 tv64;
++#if BITS_PER_LONG != 64 && !defined(CONFIG_KTIME_SCALAR)
++ struct {
++#ifdef __BIG_ENDIAN
++ s32 sec, nsec;
++#else
++ s32 nsec, sec;
++#endif
++ } tv;
++#endif
++};
++#define kmemcheck_bitfield_begin(name)
++#define kmemcheck_bitfield_end(name)
++#define CHECKSUM_NONE 0
++typedef unsigned char *sk_buff_data_t;
++typedef union ktime ktime_t; /* Kill this */
++
++void rtw_mtx_lock(_lock *plock);
++
++void rtw_mtx_unlock(_lock *plock);
++
++/**
++ * struct sk_buff - socket buffer
++ * @next: Next buffer in list
++ * @prev: Previous buffer in list
++ * @sk: Socket we are owned by
++ * @tstamp: Time we arrived
++ * @dev: Device we arrived on/are leaving by
++ * @transport_header: Transport layer header
++ * @network_header: Network layer header
++ * @mac_header: Link layer header
++ * @_skb_refdst: destination entry (with norefcount bit)
++ * @sp: the security path, used for xfrm
++ * @cb: Control buffer. Free for use by every layer. Put private vars here
++ * @len: Length of actual data
++ * @data_len: Data length
++ * @mac_len: Length of link layer header
++ * @hdr_len: writable header length of cloned skb
++ * @csum: Checksum (must include start/offset pair)
++ * @csum_start: Offset from skb->head where checksumming should start
++ * @csum_offset: Offset from csum_start where checksum should be stored
++ * @local_df: allow local fragmentation
++ * @cloned: Head may be cloned (check refcnt to be sure)
++ * @nohdr: Payload reference only, must not modify header
++ * @pkt_type: Packet class
++ * @fclone: skbuff clone status
++ * @ip_summed: Driver fed us an IP checksum
++ * @priority: Packet queueing priority
++ * @users: User count - see {datagram,tcp}.c
++ * @protocol: Packet protocol from driver
++ * @truesize: Buffer size
++ * @head: Head of buffer
++ * @data: Data head pointer
++ * @tail: Tail pointer
++ * @end: End pointer
++ * @destructor: Destruct function
++ * @mark: Generic packet mark
++ * @nfct: Associated connection, if any
++ * @ipvs_property: skbuff is owned by ipvs
++ * @peeked: this packet has been seen already, so stats have been
++ * done for it, don't do them again
++ * @nf_trace: netfilter packet trace flag
++ * @nfctinfo: Relationship of this skb to the connection
++ * @nfct_reasm: netfilter conntrack re-assembly pointer
++ * @nf_bridge: Saved data about a bridged frame - see br_netfilter.c
++ * @skb_iif: ifindex of device we arrived on
++ * @rxhash: the packet hash computed on receive
++ * @queue_mapping: Queue mapping for multiqueue devices
++ * @tc_index: Traffic control index
++ * @tc_verd: traffic control verdict
++ * @ndisc_nodetype: router type (from link layer)
++ * @dma_cookie: a cookie to one of several possible DMA operations
++ * done by skb DMA functions
++ * @secmark: security marking
++ * @vlan_tci: vlan tag control information
++ */
++
++struct sk_buff {
++ /* These two members must be first. */
++ struct sk_buff *next;
++ struct sk_buff *prev;
++
++ ktime_t tstamp;
++
++ struct sock *sk;
++ //struct net_device *dev;
++ struct ifnet *dev;
++
++ /*
++ * This is the control buffer. It is free to use for every
++ * layer. Please put your private variables there. If you
++ * want to keep them across layers you have to do a skb_clone()
++ * first. This is owned by whoever has the skb queued ATM.
++ */
++ char cb[48] __aligned(8);
++
++ unsigned long _skb_refdst;
++#ifdef CONFIG_XFRM
++ struct sec_path *sp;
++#endif
++ unsigned int len,
++ data_len;
++ u16 mac_len,
++ hdr_len;
++ union {
++ u32 csum;
++ struct {
++ u16 csum_start;
++ u16 csum_offset;
++ }smbol2;
++ }smbol1;
++ u32 priority;
++ kmemcheck_bitfield_begin(flags1);
++ u8 local_df:1,
++ cloned:1,
++ ip_summed:2,
++ nohdr:1,
++ nfctinfo:3;
++ u8 pkt_type:3,
++ fclone:2,
++ ipvs_property:1,
++ peeked:1,
++ nf_trace:1;
++ kmemcheck_bitfield_end(flags1);
++ u16 protocol;
++
++ void (*destructor)(struct sk_buff *skb);
++#if defined(CONFIG_NF_CONNTRACK) || defined(CONFIG_NF_CONNTRACK_MODULE)
++ struct nf_conntrack *nfct;
++ struct sk_buff *nfct_reasm;
++#endif
++#ifdef CONFIG_BRIDGE_NETFILTER
++ struct nf_bridge_info *nf_bridge;
++#endif
++
++ int skb_iif;
++#ifdef CONFIG_NET_SCHED
++ u16 tc_index; /* traffic control index */
++#ifdef CONFIG_NET_CLS_ACT
++ u16 tc_verd; /* traffic control verdict */
++#endif
++#endif
++
++ u32 rxhash;
++
++ kmemcheck_bitfield_begin(flags2);
++ u16 queue_mapping:16;
++#ifdef CONFIG_IPV6_NDISC_NODETYPE
++ u8 ndisc_nodetype:2,
++ deliver_no_wcard:1;
++#else
++ u8 deliver_no_wcard:1;
++#endif
++ kmemcheck_bitfield_end(flags2);
++
++ /* 0/14 bit hole */
++
++#ifdef CONFIG_NET_DMA
++ dma_cookie_t dma_cookie;
++#endif
++#ifdef CONFIG_NETWORK_SECMARK
++ u32 secmark;
++#endif
++ union {
++ u32 mark;
++ u32 dropcount;
++ }symbol3;
++
++ u16 vlan_tci;
++
++ sk_buff_data_t transport_header;
++ sk_buff_data_t network_header;
++ sk_buff_data_t mac_header;
++ /* These elements must be at the end, see alloc_skb() for details. */
++ sk_buff_data_t tail;
++ sk_buff_data_t end;
++ unsigned char *head,
++ *data;
++ unsigned int truesize;
++ atomic_t users;
++};
++struct sk_buff_head {
++ /* These two members must be first. */
++ struct sk_buff *next;
++ struct sk_buff *prev;
++
++ u32 qlen;
++ _lock lock;
++};
++#define skb_tail_pointer(skb) skb->tail
++static inline unsigned char *skb_put(struct sk_buff *skb, unsigned int len)
++{
++ unsigned char *tmp = skb_tail_pointer(skb);
++ //SKB_LINEAR_ASSERT(skb);
++ skb->tail += len;
++ skb->len += len;
++ return tmp;
++}
++
++static inline unsigned char *__skb_pull(struct sk_buff *skb, unsigned int len)
++{
++ skb->len -= len;
++ if(skb->len < skb->data_len)
++ printf("%s(),%d,error!\n",__FUNCTION__,__LINE__);
++ return skb->data += len;
++}
++static inline unsigned char *skb_pull(struct sk_buff *skb, unsigned int len)
++{
++ #ifdef PLATFORM_FREEBSD
++ return __skb_pull(skb, len);
++ #else
++ return unlikely(len > skb->len) ? NULL : __skb_pull(skb, len);
++ #endif //PLATFORM_FREEBSD
++}
++static inline u32 skb_queue_len(const struct sk_buff_head *list_)
++{
++ return list_->qlen;
++}
++static inline void __skb_insert(struct sk_buff *newsk,
++ struct sk_buff *prev, struct sk_buff *next,
++ struct sk_buff_head *list)
++{
++ newsk->next = next;
++ newsk->prev = prev;
++ next->prev = prev->next = newsk;
++ list->qlen++;
++}
++static inline void __skb_queue_before(struct sk_buff_head *list,
++ struct sk_buff *next,
++ struct sk_buff *newsk)
++{
++ __skb_insert(newsk, next->prev, next, list);
++}
++static inline void skb_queue_tail(struct sk_buff_head *list,
++ struct sk_buff *newsk)
++{
++ mtx_lock(&list->lock);
++ __skb_queue_before(list, (struct sk_buff *)list, newsk);
++ mtx_unlock(&list->lock);
++}
++static inline struct sk_buff *skb_peek(struct sk_buff_head *list_)
++{
++ struct sk_buff *list = ((struct sk_buff *)list_)->next;
++ if (list == (struct sk_buff *)list_)
++ list = NULL;
++ return list;
++}
++static inline void __skb_unlink(struct sk_buff *skb, struct sk_buff_head *list)
++{
++ struct sk_buff *next, *prev;
++
++ list->qlen--;
++ next = skb->next;
++ prev = skb->prev;
++ skb->next = skb->prev = NULL;
++ next->prev = prev;
++ prev->next = next;
++}
++
++static inline struct sk_buff *skb_dequeue(struct sk_buff_head *list)
++{
++ mtx_lock(&list->lock);
++
++ struct sk_buff *skb = skb_peek(list);
++ if (skb)
++ __skb_unlink(skb, list);
++
++ mtx_unlock(&list->lock);
++
++ return skb;
++}
++static inline void skb_reserve(struct sk_buff *skb, int len)
++{
++ skb->data += len;
++ skb->tail += len;
++}
++static inline void __skb_queue_head_init(struct sk_buff_head *list)
++{
++ list->prev = list->next = (struct sk_buff *)list;
++ list->qlen = 0;
++}
++/*
++ * This function creates a split out lock class for each invocation;
++ * this is needed for now since a whole lot of users of the skb-queue
++ * infrastructure in drivers have different locking usage (in hardirq)
++ * than the networking core (in softirq only). In the long run either the
++ * network layer or drivers should need annotation to consolidate the
++ * main types of usage into 3 classes.
++ */
++static inline void skb_queue_head_init(struct sk_buff_head *list)
++{
++ _rtw_spinlock_init(&list->lock);
++ __skb_queue_head_init(list);
++}
++unsigned long copy_from_user(void *to, const void *from, unsigned long n);
++unsigned long copy_to_user(void *to, const void *from, unsigned long n);
++struct sk_buff * dev_alloc_skb(unsigned int size);
++struct sk_buff *skb_clone(const struct sk_buff *skb);
++void dev_kfree_skb_any(struct sk_buff *skb);
++#endif //Baron porting from linux, it's all temp solution, needs to check again
++
++
++#if 1 // kenny add Linux compatibility code for Linux USB driver
++#include
++
++#define __init // __attribute ((constructor))
++#define __exit // __attribute ((destructor))
++
++/*
++ * Definitions for module_init and module_exit macros.
++ *
++ * These macros will use the SYSINIT framework to call a specified
++ * function (with no arguments) on module loading or unloading.
++ *
++ */
++
++void module_init_exit_wrapper(void *arg);
++
++#define module_init(initfn) \
++ SYSINIT(mod_init_ ## initfn, \
++ SI_SUB_KLD, SI_ORDER_FIRST, \
++ module_init_exit_wrapper, initfn)
++
++#define module_exit(exitfn) \
++ SYSUNINIT(mod_exit_ ## exitfn, \
++ SI_SUB_KLD, SI_ORDER_ANY, \
++ module_init_exit_wrapper, exitfn)
++
++/*
++ * The usb_register and usb_deregister functions are used to register
++ * usb drivers with the usb subsystem.
++ */
++int usb_register(struct usb_driver *driver);
++int usb_deregister(struct usb_driver *driver);
++
++/*
++ * usb_get_dev and usb_put_dev - increment/decrement the reference count
++ * of the usb device structure.
++ *
++ * Original body of usb_get_dev:
++ *
++ * if (dev)
++ * get_device(&dev->dev);
++ * return dev;
++ *
++ * Reference counts are not currently used in this compatibility
++ * layer. So these functions will do nothing.
++ */
++static inline struct usb_device *
++usb_get_dev(struct usb_device *dev)
++{
++ return dev;
++}
++
++static inline void
++usb_put_dev(struct usb_device *dev)
++{
++ return;
++}
++
++
++// rtw_usb_compat_linux
++int rtw_usb_submit_urb(struct urb *urb, uint16_t mem_flags);
++int rtw_usb_unlink_urb(struct urb *urb);
++int rtw_usb_clear_halt(struct usb_device *dev, struct usb_host_endpoint *uhe);
++int rtw_usb_control_msg(struct usb_device *dev, struct usb_host_endpoint *uhe,
++ uint8_t request, uint8_t requesttype,
++ uint16_t value, uint16_t index, void *data,
++ uint16_t size, usb_timeout_t timeout);
++int rtw_usb_set_interface(struct usb_device *dev, uint8_t iface_no, uint8_t alt_index);
++int rtw_usb_setup_endpoint(struct usb_device *dev,
++ struct usb_host_endpoint *uhe, usb_size_t bufsize);
++struct urb *rtw_usb_alloc_urb(uint16_t iso_packets, uint16_t mem_flags);
++struct usb_host_endpoint *rtw_usb_find_host_endpoint(struct usb_device *dev, uint8_t type, uint8_t ep);
++struct usb_host_interface *rtw_usb_altnum_to_altsetting(const struct usb_interface *intf, uint8_t alt_index);
++struct usb_interface *rtw_usb_ifnum_to_if(struct usb_device *dev, uint8_t iface_no);
++void *rtw_usbd_get_intfdata(struct usb_interface *intf);
++void rtw_usb_linux_register(void *arg);
++void rtw_usb_linux_deregister(void *arg);
++void rtw_usb_linux_free_device(struct usb_device *dev);
++void rtw_usb_free_urb(struct urb *urb);
++void rtw_usb_init_urb(struct urb *urb);
++void rtw_usb_kill_urb(struct urb *urb);
++void rtw_usb_set_intfdata(struct usb_interface *intf, void *data);
++void rtw_usb_fill_bulk_urb(struct urb *urb, struct usb_device *udev,
++ struct usb_host_endpoint *uhe, void *buf,
++ int length, usb_complete_t callback, void *arg);
++int rtw_usb_bulk_msg(struct usb_device *udev, struct usb_host_endpoint *uhe,
++ void *data, int len, uint16_t *pactlen, usb_timeout_t timeout);
++void *usb_get_intfdata(struct usb_interface *intf);
++int usb_linux_init_endpoints(struct usb_device *udev);
++
++
++
++typedef struct urb * PURB;
++
++typedef unsigned gfp_t;
++#define __GFP_WAIT ((gfp_t)0x10u) /* Can wait and reschedule? */
++#define __GFP_HIGH ((gfp_t)0x20u) /* Should access emergency pools? */
++#define __GFP_IO ((gfp_t)0x40u) /* Can start physical IO? */
++#define __GFP_FS ((gfp_t)0x80u) /* Can call down to low-level FS? */
++#define __GFP_COLD ((gfp_t)0x100u) /* Cache-cold page required */
++#define __GFP_NOWARN ((gfp_t)0x200u) /* Suppress page allocation failure warning */
++#define __GFP_REPEAT ((gfp_t)0x400u) /* Retry the allocation. Might fail */
++#define __GFP_NOFAIL ((gfp_t)0x800u) /* Retry for ever. Cannot fail */
++#define __GFP_NORETRY ((gfp_t)0x1000u)/* Do not retry. Might fail */
++#define __GFP_NO_GROW ((gfp_t)0x2000u)/* Slab internal usage */
++#define __GFP_COMP ((gfp_t)0x4000u)/* Add compound page metadata */
++#define __GFP_ZERO ((gfp_t)0x8000u)/* Return zeroed page on success */
++#define __GFP_NOMEMALLOC ((gfp_t)0x10000u) /* Don't use emergency reserves */
++#define __GFP_HARDWALL ((gfp_t)0x20000u) /* Enforce hardwall cpuset memory allocs */
++
++/* This equals 0, but use constants in case they ever change */
++#define GFP_NOWAIT (GFP_ATOMIC & ~__GFP_HIGH)
++/* GFP_ATOMIC means both !wait (__GFP_WAIT not set) and use emergency pool */
++#define GFP_ATOMIC (__GFP_HIGH)
++#define GFP_NOIO (__GFP_WAIT)
++#define GFP_NOFS (__GFP_WAIT | __GFP_IO)
++#define GFP_KERNEL (__GFP_WAIT | __GFP_IO | __GFP_FS)
++#define GFP_USER (__GFP_WAIT | __GFP_IO | __GFP_FS | __GFP_HARDWALL)
++#define GFP_HIGHUSER (__GFP_WAIT | __GFP_IO | __GFP_FS | __GFP_HARDWALL | \
++ __GFP_HIGHMEM)
++
++
++#endif // kenny add Linux compatibility code for Linux USB
++
++__inline static _list *get_next(_list *list)
++{
++ return list->next;
++}
++
++__inline static _list *get_list_head(_queue *queue)
++{
++ return (&(queue->queue));
++}
++
++
++#define LIST_CONTAINOR(ptr, type, member) \
++ ((type *)((char *)(ptr)-(SIZE_T)(&((type *)0)->member)))
++
++
++__inline static void _enter_critical(_lock *plock, _irqL *pirqL)
++{
++ spin_lock_irqsave(plock, *pirqL);
++}
++
++__inline static void _exit_critical(_lock *plock, _irqL *pirqL)
++{
++ spin_unlock_irqrestore(plock, *pirqL);
++}
++
++__inline static void _enter_critical_ex(_lock *plock, _irqL *pirqL)
++{
++ spin_lock_irqsave(plock, *pirqL);
++}
++
++__inline static void _exit_critical_ex(_lock *plock, _irqL *pirqL)
++{
++ spin_unlock_irqrestore(plock, *pirqL);
++}
++
++__inline static void _enter_critical_bh(_lock *plock, _irqL *pirqL)
++{
++ spin_lock_bh(plock, *pirqL);
++}
++
++__inline static void _exit_critical_bh(_lock *plock, _irqL *pirqL)
++{
++ spin_unlock_bh(plock, *pirqL);
++}
++
++__inline static void _enter_critical_mutex(_mutex *pmutex, _irqL *pirqL)
++{
++
++ mtx_lock(pmutex);
++
++}
++
++
++__inline static void _exit_critical_mutex(_mutex *pmutex, _irqL *pirqL)
++{
++
++ mtx_unlock(pmutex);
++
++}
++static inline void __list_del(struct list_head * prev, struct list_head * next)
++{
++ next->prev = prev;
++ prev->next = next;
++}
++static inline void INIT_LIST_HEAD(struct list_head *list)
++{
++ list->next = list;
++ list->prev = list;
++}
++__inline static void rtw_list_delete(_list *plist)
++{
++ __list_del(plist->prev, plist->next);
++ INIT_LIST_HEAD(plist);
++}
++
++static inline void timer_hdl(void *ctx)
++{
++ _timer *timer = (_timer *)ctx;
++
++ rtw_mtx_lock(NULL);
++ if (callout_pending(&timer->callout)) {
++ /* callout was reset */
++ rtw_mtx_unlock(NULL);
++ return;
++ }
++
++ if (!callout_active(&timer->callout)) {
++ /* callout was stopped */
++ rtw_mtx_unlock(NULL);
++ return;
++ }
++
++ callout_deactivate(&timer->callout);
++
++ timer->function(timer->arg);
++
++ rtw_mtx_unlock(NULL);
++}
++
++static inline void _init_timer(_timer *ptimer, _nic_hdl padapter, void *pfunc, void *cntx)
++{
++ ptimer->function = pfunc;
++ ptimer->arg = cntx;
++ callout_init(&ptimer->callout, CALLOUT_MPSAFE);
++}
++
++__inline static void _set_timer(_timer *ptimer,u32 delay_time)
++{
++ if (ptimer->function && ptimer->arg) {
++ rtw_mtx_lock(NULL);
++ callout_reset(&ptimer->callout, delay_time, timer_hdl, ptimer);
++ rtw_mtx_unlock(NULL);
++ }
++}
++
++__inline static void _cancel_timer(_timer *ptimer,u8 *bcancelled)
++{
++ rtw_mtx_lock(NULL);
++ callout_drain(&ptimer->callout);
++ rtw_mtx_unlock(NULL);
++ *bcancelled = 1; /* assume an pending timer to be canceled */
++}
++
++__inline static void _init_workitem(_workitem *pwork, void *pfunc, PVOID cntx)
++{
++ printf("%s Not implement yet! \n",__FUNCTION__);
++}
++
++__inline static void _set_workitem(_workitem *pwork)
++{
++ printf("%s Not implement yet! \n",__FUNCTION__);
++// schedule_work(pwork);
++}
++
++//
++// Global Mutex: can only be used at PASSIVE level.
++//
++
++#define ACQUIRE_GLOBAL_MUTEX(_MutexCounter) \
++{ \
++}
++
++#define RELEASE_GLOBAL_MUTEX(_MutexCounter) \
++{ \
++}
++
++#define ATOMIC_INIT(i) { (i) }
++
++static __inline void thread_enter(char *name);
++
++//Atomic integer operations
++typedef uint32_t ATOMIC_T ;
++
++#define rtw_netdev_priv(netdev) (((struct ifnet *)netdev)->if_softc)
++
++#define rtw_free_netdev(netdev) if_free((netdev))
++
++#define NDEV_FMT "%s"
++#define NDEV_ARG(ndev) ""
++#define ADPT_FMT "%s"
++#define ADPT_ARG(adapter) ""
++#define FUNC_NDEV_FMT "%s"
++#define FUNC_NDEV_ARG(ndev) __func__
++#define FUNC_ADPT_FMT "%s"
++#define FUNC_ADPT_ARG(adapter) __func__
++
++#define STRUCT_PACKED
++
++#endif
++
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/include/osdep_service_ce.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/include/osdep_service_ce.h
+--- linux-5.11.4/3rdparty/rtl8812au/include/osdep_service_ce.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/include/osdep_service_ce.h 2021-03-07 18:16:17.087957613 +0200
+@@ -0,0 +1,200 @@
++/******************************************************************************
++ *
++ * Copyright(c) 2007 - 2017 Realtek Corporation.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of version 2 of the GNU General Public License as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ *****************************************************************************/
++
++#ifndef __OSDEP_CE_SERVICE_H_
++#define __OSDEP_CE_SERVICE_H_
++
++
++#include
++#include
++
++#ifdef CONFIG_SDIO_HCI
++#include "SDCardDDK.h"
++#endif
++
++#ifdef CONFIG_USB_HCI
++#include
++#endif
++
++typedef HANDLE _sema;
++typedef LIST_ENTRY _list;
++typedef NDIS_STATUS _OS_STATUS;
++
++typedef NDIS_SPIN_LOCK _lock;
++
++typedef HANDLE _rwlock; //Mutex
++
++typedef u32 _irqL;
++
++typedef NDIS_HANDLE _nic_hdl;
++
++struct rtw_timer_list {
++ NDIS_MINIPORT_TIMER ndis_timer;
++ void (*function)(void *);
++ void *arg;
++};
++
++struct __queue {
++ LIST_ENTRY queue;
++ _lock lock;
++};
++
++typedef NDIS_PACKET _pkt;
++typedef NDIS_BUFFER _buffer;
++typedef struct __queue _queue;
++
++typedef HANDLE _thread_hdl_;
++typedef DWORD thread_return;
++typedef void* thread_context;
++typedef NDIS_WORK_ITEM _workitem;
++
++
++
++#define SEMA_UPBND (0x7FFFFFFF) //8192
++
++__inline static _list *get_prev(_list *list)
++{
++ return list->Blink;
++}
++
++__inline static _list *get_next(_list *list)
++{
++ return list->Flink;
++}
++
++__inline static _list *get_list_head(_queue *queue)
++{
++ return (&(queue->queue));
++}
++
++#define LIST_CONTAINOR(ptr, type, member) CONTAINING_RECORD(ptr, type, member)
++
++__inline static void _enter_critical(_lock *plock, _irqL *pirqL)
++{
++ NdisAcquireSpinLock(plock);
++}
++
++__inline static void _exit_critical(_lock *plock, _irqL *pirqL)
++{
++ NdisReleaseSpinLock(plock);
++}
++
++__inline static _enter_critical_ex(_lock *plock, _irqL *pirqL)
++{
++ NdisDprAcquireSpinLock(plock);
++}
++
++__inline static _exit_critical_ex(_lock *plock, _irqL *pirqL)
++{
++ NdisDprReleaseSpinLock(plock);
++}
++
++
++__inline static void _enter_hwio_critical(_rwlock *prwlock, _irqL *pirqL)
++{
++ WaitForSingleObject(*prwlock, INFINITE );
++
++}
++
++__inline static void _exit_hwio_critical(_rwlock *prwlock, _irqL *pirqL)
++{
++ ReleaseMutex(*prwlock);
++}
++
++__inline static void rtw_list_delete(_list *plist)
++{
++ RemoveEntryList(plist);
++ InitializeListHead(plist);
++}
++
++static inline void timer_hdl(
++ IN PVOID SystemSpecific1,
++ IN PVOID FunctionContext,
++ IN PVOID SystemSpecific2,
++ IN PVOID SystemSpecific3)
++{
++ _timer *timer = (_timer *)FunctionContext;
++
++ timer->function(timer->arg);
++}
++
++static inline void _init_timer(_timer *ptimer, _nic_hdl nic_hdl, void *pfunc, void *cntx)
++{
++ ptimer->function = pfunc;
++ ptimer->arg = cntx;
++ NdisMInitializeTimer(&ptimer->ndis_timer, nic_hdl, timer_hdl, ptimer);
++}
++
++static inline void _set_timer(_timer *ptimer, u32 delay_time)
++{
++ NdisMSetTimer(ptimer, delay_time);
++}
++
++static inline void _cancel_timer(_timer *ptimer, u8 *bcancelled)
++{
++ NdisMCancelTimer(ptimer, bcancelled);
++}
++
++__inline static void _init_workitem(_workitem *pwork, void *pfunc, PVOID cntx)
++{
++
++ NdisInitializeWorkItem(pwork, pfunc, cntx);
++}
++
++__inline static void _set_workitem(_workitem *pwork)
++{
++ NdisScheduleWorkItem(pwork);
++}
++
++#define ATOMIC_INIT(i) { (i) }
++
++//
++// Global Mutex: can only be used at PASSIVE level.
++//
++
++#define ACQUIRE_GLOBAL_MUTEX(_MutexCounter) \
++{ \
++ while (NdisInterlockedIncrement((PULONG)&(_MutexCounter)) != 1)\
++ { \
++ NdisInterlockedDecrement((PULONG)&(_MutexCounter)); \
++ NdisMSleep(10000); \
++ } \
++}
++
++#define RELEASE_GLOBAL_MUTEX(_MutexCounter) \
++{ \
++ NdisInterlockedDecrement((PULONG)&(_MutexCounter)); \
++}
++
++// limitation of path length
++#define PATH_LENGTH_MAX MAX_PATH
++
++//Atomic integer operations
++#define ATOMIC_T LONG
++
++#define NDEV_FMT "%s"
++#define NDEV_ARG(ndev) ""
++#define ADPT_FMT "%s"
++#define ADPT_ARG(adapter) ""
++#define FUNC_NDEV_FMT "%s"
++#define FUNC_NDEV_ARG(ndev) __func__
++#define FUNC_ADPT_FMT "%s"
++#define FUNC_ADPT_ARG(adapter) __func__
++
++#define STRUCT_PACKED
++
++
++#endif
++
+diff -Nurp linux-5.11.4/3rdparty/rtl8812au/include/osdep_service.h linux-5.11.4-rtl8812au/3rdparty/rtl8812au/include/osdep_service.h
+--- linux-5.11.4/3rdparty/rtl8812au/include/osdep_service.h 1970-01-01 02:00:00.000000000 +0200
++++ linux-5.11.4-rtl8812au/3rdparty/rtl8812au/include/osdep_service.h 2021-03-07 18:16:17.087957613 +0200
@@ -0,0 +1,804 @@
+/******************************************************************************
+ *
@@ -389492,979 +386970,9 @@ index 000000000..d7e375329
+#endif /* !PLATFORM_LINUX */
+
+#endif
-diff --git linux-5.8/3rdparty/rtl8812au/include/osdep_service_bsd.h linux-5.8/3rdparty/rtl8812au/include/osdep_service_bsd.h
-new file mode 100644
-index 000000000..4773f05fd
---- /dev/null
-+++ linux-5.8/3rdparty/rtl8812au/include/osdep_service_bsd.h
-@@ -0,0 +1,756 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __OSDEP_BSD_SERVICE_H_
-+#define __OSDEP_BSD_SERVICE_H_
-+
-+
-+#include
-+#include
-+#include
-+#include
-+#include
-+#include
-+#include
-+#include
-+#include
-+#include
-+#include
-+#include
-+#include
-+#include
-+#include
-+#include
-+#include
-+#include
-+#include
-+#include
-+#include
-+#include
-+#include
-+#include
-+
-+#include
-+#include
-+#include
-+#include
-+#include
-+#include
-+#include
-+#include
-+
-+
-+#include
-+#include
-+#include
-+#include
-+#include
-+
-+#include
-+#include
-+#include
-+#include
-+
-+#include